Introduction to Programming

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Compilers Stack Machines Alex Aiken Stack Machines • Only storage is a stack • An instruction r = F(a1,…an): – Pops n operands from the stack – Computes the operation F using the operands – Pushes the result r on the stack Alex Aiken Stack Machines Alex Aiken Stack Machines • Consider two instructions – push i - push integer i on the stack – add - add two integers – A program: push 7 push 5 add Alex Aiken Stack Machines • Stack machines are a very simple machine model – Leads to a simple, small compiler – But not necessarily one that produces very fast code Alex Aiken Stack Machines • Location of the operands/result is not explicitly stated – Always the top of the stack • In contrast to a register machine – add instead of add r1, r2, r3 – More compact programs • One reason that Java bytecode uses stack evaluation Alex Aiken Stack Machines • There is an intermediate point between a pure stack machine and a pure register machine • An n-register stack machine – Conceptually, keep the top n locations of the pure stack machine’s stack in registers • Consider a 1-register stack machine – The register is called the accumulator Alex Aiken Stack Machines • In a pure stack machine – An add does 3 memory operations – Two reads and one write to the stack • In a 1-register stack machine the add does acc acc + top_of_stack Alex Aiken Stack Machines • Consider an expression op(e1,…,en) – Note e1,…,en are subexpressions • For each ei (0 < i < n) – Compute ei – Push result on the stack • Pop n-1 values from the stack, compute op • Store result in the accumulator Alex Aiken Stack Machines Alex Aiken Stack Machines After evaluating an expression e, the accumulator holds the value of e and the stack is unchanged. Expression evaluation preserves the stack. Alex Aiken Stack Machines Code Acc Stack acc 3 3 <init> push acc 3 3, <init> acc 7 7 3, <init> push acc 7 7, 3, <init> acc 5 5 7, 3, <init> acc acc + top_of_stack 12 7, 3, <init> pop 12 3, <init> acc acc + top_of_stack 15 3, <init> pop 15 <init> Alex Aiken Given the current state of the stack and Stack Machines accumulator, what is the next line of Template Current: block2x2-1 code to generate for the code fragment (2 * 3) + 5? Acc : 5 Ordering of buttons is: Stack: 6,<init> 13 push acc pop 24 acc 6 acc acc + top_of_stack .

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Low-Power Microprocessor Based on Stack Architecture
Girish Aramanekoppa Subbarao Low-power Microprocessor based on Stack Architecture Stack on based Microprocessor Low-power Master’s Thesis Low-power Microprocessor based on Stack Architecture Girish Aramanekoppa Subbarao Series of Master’s theses Department of Electrical and Information Technology LU/LTH-EIT 2015-464 Department of Electrical and Information Technology, http://www.eit.lth.se Faculty of Engineering, LTH, Lund University, September 2015. Department of Electrical and Information Technology Master of Science Thesis Low-power Microprocessor based on Stack Architecture Supervisors: Author: Prof. Joachim Rodrigues Girish Aramanekoppa Subbarao Prof. Anders Ardö Lund 2015 © The Department of Electrical and Information Technology Lund University Box 118, S-221 00 LUND SWEDEN This thesis is set in Computer Modern 10pt, with the LATEX Documentation System ©Girish Aramanekoppa Subbarao 2015 Printed in E-huset Lund, Sweden. Sep. 2015 Abstract There are many applications of microprocessors in embedded applications, where power efficiency becomes a critical requirement, e.g. wearable or mobile devices in healthcare, space instrumentation and handheld devices. One of the methods of achieving low power operation is by simplifying the device architecture. RISC/CISC processors consume considerable power because of their complexity, which is due to their multiplexer system connecting the register file to the func- tional units and their instruction pipeline system. On the other hand, the Stack machines are comparatively less complex due to their implied addressing to the top two registers of the stack and smaller operation codes. This makes the instruction and the address decoder circuit simple by eliminating the multiplex switches for read and write ports of the register file.
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Design and Construction of a PC-Based Stack Machine Simulator for Undergraduate Computer Science & Engineering Courses
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EECS 470 Lecture 2 Instruction Set Architecture
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Code Generation for a Stack Machine •
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Computer Science 160 Translation of Programming Languages
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Second-Generation Stack Computer Architecture
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Stack Machines
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