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Development of Stack Based Central Processing Unit for a FORTH Computer Using FPGA Development of Stack Based Central Processing Unit for a FORTH Computer Using FPGA By KENNETH WONG FATT KONG FINAL YEAR PROJECT REPORT Final Dissertation Submitted to the Electrical & Electronics Engineering Program in Partial Fulfillment of the Requirements for the Degree Bachelor of Engineering (Hons) (Electrical & Electronics Engineering) DECEMBER 2009 Universiti Teknologi Petronas Bandar Seri Iskandar 31750 Tronoh Perak Darul Ridzuan Copyright 2009 by Kenneth Wong Fatt Kong, UTP CERTIFICATION OF APPROVAL Development of Stack Based Central Processing Unit for a FORTH Computer Using FPGA by Kenneth Wong Fatt Kong A project Final Dissertation submitted to the Electrical & Electronics Engineering Program Universiti Teknologi PETRONAS in partial fulfillment of the requirement for the Bachelor of Engineering (Hons) (Electrical & Electronics Engineering) Approved: __________________________ __________________________ Dr. Yap Vooi Voon Mr. Patrick Sebastian Project Supervisor Project Co-Supervisor UNIVERSITI TEKNOLOGI PETRONAS TRONOH, PERAK December 2009 i CERTIFICATION OF ORIGINALITY This is to certify that I am responsible for the work submitted in this project, that the original work is my own except as specified in the references and acknowledgements, and that the original work contained herein have not been undertaken or done by unspecified sources or persons. __________________________ Kenneth Wong Fatt Kong ii ABSTRACT This is the Final Dissertation for Electrical & Electronics Engineering Bachelor Degree Final Year Project (FYP). The title for this FYP is “Development of Stack Based Central Processing Unit for a FORTH Computer Using FPGA”. This project is based on the design by a previous FYP student, Aaron Tang Shen Lee with his title, “Development of a Stack-Based Centre Processing Unit (CPU) using TTL Logic”. Using the same stack architecture and FORTH programming language, this CPU is to be implemented using FPGAs instead of fully TTL. Besides, this project will make reference to the FORTH computer, Mark 1 built by Andrew Holme, just as the previous project did. This Final Dissertation will contain the progress on the implementation of the stack-based CPU into FPGA. The achievements and obstacles arise while completing this project will be recorded in this report. iii TABLE OF CONTENT CERTIFICATION OF APPROVAL ........................................................................ i CERTIFICATION OF ORIGINALITY .................................................................. ii ABSTRACT ............................................................................................................... iii LIST OF FIGURE .................................................................................................. viii LIST OF TABLES .................................................................................................... ix LIST OF ABBREVIATIONS ................................................................................... x CHAPTER 1 INTRODUCTION .............................................................................. 1 1.1 Background of Study .................................................................. 1 1.2 Problem Statement ..................................................................... 2 1.3 Objective ...................................................................................... 2 1.4 Outline of Report ........................................................................ 3 CHAPTER 2 LITERATURE REVIEW AND THEORY ...................................... 4 2.1 Computer System Architecture ................................................. 4 2.1.1 Data Path ........................................................................... 4 2.1.2 Control Path ...................................................................... 5 2.1.3 Instruction Set Architecture (ISA) ................................... 5 2.2 FORTH ........................................................................................ 6 2.3 Stack Machine ............................................................................. 7 2.3.1 What is Stack? ................................................................... 8 2.3.2 Advantages of Stack-Based Machine ............................... 9 2.3.3 Important of Stack-Based Machine.................................. 9 iv 2.4 Stack-Based Machine and FORTH ......................................... 10 2.5 Chapter Summary .................................................................... 10 CHAPTER 3 METHODOLOGY ........................................................................... 11 3.1 Procedure Identification .......................................................... 11 3.2 Tools ........................................................................................... 12 3.2.1 Hardware ......................................................................... 12 3.2.2 Software ........................................................................... 13 3.3 Work Completed ....................................................................... 13 3.3.1 Testing of UP2 Board...................................................... 14 3.3.2 The Power Supply ........................................................... 14 3.3.3 The Expansion Card ....................................................... 14 3.3.4 TTL Module in HDL Design .......................................... 15 3.3.5 Interfacing and Replacing TTL Module with FPGA .... 15 3.4 Chapter Summary .................................................................... 16 CHAPTER 4 RESULTS AND DISCUSSION ....................................................... 17 4.1 Test Result of the UP2 Board .................................................. 17 4.2 Design of the Power Supply ..................................................... 17 4.3 Design and Simulation.............................................................. 18 4.3.1 Instruction Decoder Module ........................................... 18 4.3.2 Diode ROM Module ........................................................ 21 4.3.3 Index Pointer Module ..................................................... 22 4.4 Interfacing Troubleshoot and Discussion ............................... 23 4.4.1 System Clock Derivation ................................................. 24 4.4.2 Short Circuit Test ............................................................ 24 4.4.3 Voltage Drop Test ............................................................ 24 v 4.4.4 Signal Waveform Test ..................................................... 26 4.4.5 Other Test ........................................................................ 26 4.5 Implementation Results and Discussions ............................... 27 4.5.1 Instruction Decoder Module ........................................... 27 4.5.2 Diode ROM Module ........................................................ 27 4.5.3 Index Pointer Module ..................................................... 27 4.6 Design Limitation ....................................................................... 28 4.6.1 Memory Capacity ............................................................. 28 4.6.2 Complexity of Customization ........................................... 29 4.7 Chapter Summary ....................................................................... 29 CHAPTER 5 CONCLUSION AND RECOMMENDATION .............................. 30 5.1 Recommendation for Future Studies ...................................... 30 5.2 Conclusion ................................................................................. 30 REFERENCES ......................................................................................................... 32 APPENDICES .......................................................................................................... 33 Appendix I Mark 1 FPGA Specification .................................... 34 Specification .............................................................................. 34 System Overview ...................................................................... 34 µ-Instruction For ma t ................................................................. 35 FPGA I/O Pins and Back Pane Connection .............................. 37 Appendix II Mark 1 Design Schematics .................................... 38 Appendix III Mark 1 FPGA Module Design in Verilog Codes 43 Appendix IV Test Codes for UP2 Board .................................... 49 Appendix V Photo Collection of The Project ............................ 53 FLEX10K70 FPGA by Altera ................................................... 53 vi Power Supply ............................................................................ 53 Expansion card .......................................................................... 54 Testing stage ............................................................................. 55 Appendix VI Application Notes on FPGA Design .................... 58 TTL Compatibility with FPGA ................................................. 58 Clock Signal Derivation ............................................................ 59 INOUT Port Implementation in Verilog HDL .......................... 59 Use of Buffers for OUTPUT Port ............................................. 60 vii LIST OF FIGURE Figure 1 : Key parts of digital computer architecture (figure from [1] page 44) ........ 1 Figure 2 : Example of data path (figure from [1], page 246) ...................................... 4 Figure 3 : Example
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