Pentium® II Xeon™ Processor/Intel® 450NX Pciset AGTL+ Layout Guidelines

E AP-830 APPLICATION NOTE Pentium® II Xeon™ Processor/Intel® 450NX PCIset AGTL+ Layout Guidelines June 1998 Order Number: 243790-001 6/9/98 2:09 PM 24379001.DOC INTEL CONFIDENTIAL (until publication date) Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Pentium® II Xeon™ processor and the Intel® 450NX PCIset may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548-4725 or by visiting Intel’s website at http://www.intel.com Copyright © Intel Corporation 1998. * Third-party brands and names are the property of their respective owners. 6/9/98 2:09 PM 24379001.DOC INTEL CONFIDENTIAL (until publication date) E AP-830 CONTENTS PAGE PAGE 4.4.2. POTENTIAL TERMINATION 1.0. INTRODUCTION ...............................................5 CROSSTALK PROBLEMS...................23 2.0. ABOUT THIS DOCUMENT...............................5 5.0. MORE DETAILS AND INSIGHTS...................23 2.1. Document Organization..................................5 5.1. Textbook Timing Equations..........................23 2.2. References .....................................................5 5.2. Effective Impedance and Tolerance/ 2.3. Definition of Terms .........................................5 Variation .......................................................24 5.3. Power/Reference Planes, PCB Stackup, and 3.0. AGTL+ DESIGN GUIDELINE ...........................7 High Frequency Decoupling.........................24 3.1. Determine Components..................................7 5.3.1. POWER DISTRIBUTION ......................24 3.2. Initial Timing Analysis.....................................8 5.3.2. REFERENCE PLANES AND PCB 3.3. Determine General Topology, Layout, and STACKUP .............................................24 Routing Desired............................................11 5.3.3. HIGH FREQUENCY DECOUPLING ....26 3.4. Pre-Layout Simulation ..................................13 5.3.4. SLOT 2 CONNECTOR..........................26 3.4.1. METHODOLOGY..................................13 5.4. Clock Routing ...............................................27 3.4.2. SIMULATION CRITERIA ......................14 5.5. Conclusion....................................................27 3.5. Place and Route Board ................................14 3.5.1. ESTIMATE COMPONENT TO 6.0. VREF GUARDBAND.......................................28 COMPONENT SPACING FOR AGTL+ SIGNALS ..............................................14 7.0. OVERDRIVE REGION.....................................28 3.5.2. LAYOUT AND ROUTE BOARD ...........14 8.0. FLIGHT TIME DEFINITION AND 3.6. Post-Layout Simulation.................................15 MEASUREMENT.............................................29 3.6.1. INTERSYMBOL INTERFERENCE.......15 3.6.2. CROSSTALK ANALYSIS......................15 FIGURES 3.6.3. MONTE CARLO ANALYSIS.................15 Figure 1. Example 6-load and 5-load Plus 6th 3.7. Validation......................................................16 Stub Termination Network Topology...12 3.7.1. MEASUREMENTS................................16 Figure 2. Example 5-load Network Topology 3.7.2. FLIGHT TIME SIMULATION.................16 Optimized for 100 MHz Bus................13 3.7.3. FLIGHT TIME HARDWARE Figure 3. Test Load vs. Actual System Load ......16 VALIDATION.........................................17 Figure 4. Rising Edge Noise Margin....................19 Figure 5. Propagation on Aggressor Network .....20 4.0. THEORY ..........................................................17 Figure 6. Aggressor and Victim Networks...........21 4.1. AGTL+ ..........................................................17 Figure 7. Transmission Line Geometry: (A) 4.2. Timing Requirements ...................................17 Microstrip (B) Stripline.........................21 4.3. Noise Margin ................................................17 Figure 8. One Signal Layer and One Reference 4.3.1. FALLING EDGE OR LOW LEVEL Plane ...................................................25 NOISE MARGIN ...................................18 Figure 9. Layer Switch with One Reference 4.3.2. RISING EDGE OR HIGH LEVEL NOISE Plane ...................................................25 MARGIN................................................19 Figure 10. Layer Switch with Multiple Reference 4.4. Crosstalk Theory ..........................................20 Planes (same type) .............................25 4.4.1. CROSSTALK MANAGEMENT .............22 Figure 11. Layer Switch with Multiple Reference Planes .................................................26 3 6/9/98 2:09 PM 24379001.DOC INTEL CONFIDENTIAL (until publication date) E AP-830 Figure 12. One Layer with Multiple Reference Table 2. Example TFLT_MAX Calculations for Planes................................................. 26 100 MHz Bus....................................... 10 Figure 13. Overdrive Region and VREF Table 3. Example TFLT_MAX Calculations for 90 Guardband.......................................... 29 MHz Bus (Cluster Controller Design).. 11 Figure 14. Rising Edge Flight Time Definition..... 29 Table 4. Example TFLT_MIN Calculations (Frequency Independent) .................... 11 Table 5. Example Backward Crosstalk Coupling Factors with εr = 4.5, VOH_MAX = TABLES 1.5 V, and Z0 = 65 Ω ........................... 22 Table 1. Pentium® II Xeon™ Processor and MIOC AGTL+ Parameters..................... 9 4 6/9/98 2:09 PM 24379001.DOC INTEL CONFIDENTIAL (until publication date) E AP-830 1.0. INTRODUCTION 2.2. References The Pentium® II Xeon™ processor is a follow-on to the • Pentium® II Xeon™ Processor at 400 MHz Pentium Pro and Pentium II family of microprocessors • Intel® 450NX PCIset and is the first 100 MHz Slot 2 processor. The design of • ® the external Pentium II Xeon processor bus enables the Pentium II Xeon™ Processor Power Distribution Pentium II Xeon processor to be “multiprocessor Guidelines ready.” To relax timing constraints on a bus that • Slot 2 Processor Bus Terminator Design Guidelines supports up to six loads, the Pentium II Xeon processor • ® implements a synchronous, latched bus protocol that Pentium II Processor Developer’s Manual (Order allows a full clock cycle for signal transmission and a Number 243341) full clock cycle for signal interpretation and generation. • VRM 8.2/8.3 DC-DC Converter Specification This protocol simplifies interconnect timing requirements and supports 100 MHz system designs using conventional interconnect technology. The 2.3. Definition of Terms Pentium II Xeon processor bus uses low-voltage-swing AGTL+ I/O buffers, making high frequency signal Aggressor - a network that transmits a coupled signal to communication between many loads easier. another network is called the aggressor network. The goal of this layout guideline is to provide the AGTL+ - The Pentium II Xeon processor system bus system designer with the information needed for the uses a new bus technology called AGTL+, or Assisted Pentium II Xeon processor and Intel® 450NX PCIset Gunning Transceiver Logic. AGTL+ buffers are open- AGTL+ bus portion of PCB layout. This document drain and require pull-up resistors for providing the provides guidelines and methodologies that are to be high logic level and termination. The Pentium II Xeon used with good engineering practices. See the Pentium® processor AGTL+ output buffers differ from GTL+ II Xeon™ Processor at 400 MHz and Intel® 450NX buffers with the addition of an active pMOS pull-up PCIset for component specific electrical details. Intel transistor to “assist” the pull-up resistors during the first strongly recommends running analog simulations using clock of a low-to-high voltage transition. Additionally, the available I/O buffer models together with layout the Pentium II Xeon processor Single Edge Connector information extracted from your specific design. (S.E.C.) cartridge contains internal 150 Ω pull-up resistors to provide termination at each bus load. 2.0. ABOUT THIS DOCUMENT Bus Agent - a component or group of components that, when combined, represent a single load on the AGTL+ bus. 2.1. Document Organization Corner - describes how a component performs when all This section defines terms used in

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