Pentium® Ii Xeon™ Processor at 400 and 450 Mhz

Total Page:16

File Type:pdf, Size:1020Kb

Pentium® Ii Xeon™ Processor at 400 and 450 Mhz E PENTIUM® II XEON™ PROCESSOR AT 400 AND 450 MHZ Binary compatible with applications Single Edge Contact (S.E.C.) cartridge running on previous members of the packaging technology; the S.E.C. Intel microprocessor family cartridge delivers high performance Optimized for 32-bit applications processing and bus technology in mid running on advanced 32-bit operating range to high end servers and systems workstations Dynamic Execution micro architecture 100 MHz system bus speeds data transfer between the processor and Dual Independent Bus architecture: the system Separate dedicated external 100 MHz System Bus and dedicated internal Integrated high performance 16K cache bus operating at full processor instruction and 16K data, nonblocking, core speed level-one cache Power Management capabilities Available in 512K, 1 M, 2M unified, — System Management mode nonblocking level-two cache — Multiple low-power states Enables systems which are scaleable SMBus interface to advanced up to four processors and 64 GB of manageability features physical memory The Intel® Pentium® II Xeon™ processor is designed for mid-range to high-end servers and workstations, and is binary compatible with previous Intel Architecture processors. The Pentium II Xeon processor provides the best performance available for applications running on advanced operating systems such as Windows* 95, Windows NT, and UNIX*. The Pentium II Xeon processor is scalable to four processors in a multiprocessor system and extends the power of the Pentium Pro processor with new features designed to make this processor the right choice for powerful workstation, advanced server management, and mission-critical applications. Pentium II Xeon processor-based workstations offer the memory architecture required by the most demanding workstation applications and workloads. Specific features of the Pentium II Xeon processor address platform manageability to meet the needs of a robust IT environment, maximize system up time and ensure optimal configuration and operation of servers. The Pentium II Xeon processor enhances the ability of server platforms to monitor, protect, and service the processor and its environment. Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products. Information contained herein supersedes previously published specifications on these devices from Intel. © INTEL CORPORATION 1995 June 1998 Order Number: 243770-003 12/16/98 1:22 PM 24377003.doc PENTIUM® II XEON™ PROCESSOR AT 400 AND 450 MHZ E Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Pentium® II Xeon™ processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548-4725 or by visiting Intel’s website at http://www.intel.com Copyright © Intel Corporation 1998. * Third-party brands and names are the property of their respective owners. 2 12/15/98 5:14 PM 24377002.doc E PENTIUM® II XEON™ PROCESSOR AT 400 AND 450 MHZ CONTENTS PAGE PAGE 3.3.1. 2.5 V TOLERANT BUFFER 1.0. INTRODUCTION............................................... 8 OVERSHOOT/UNDERSHOOT 1.1. Terminology.................................................... 8 GUIDELINES........................................37 1.1.1. S.E.C. Cartridge Terminology................. 8 3.3.2. 2.5 V TOLERANT BUFFER RINGBACK 1.2. References..................................................... 9 SPECIFICATION ..................................38 3.3.3. 2.5 V TOLERANT BUFFER SETTLING 2.0. ELECTRICAL SPECIFICATIONS .................... 9 LIMIT GUIDELINE ................................38 2.1. The Pentium® II Xeon™ Processor System 4.0. PROCESSOR FEATURES.............................38 Bus and VREF ............................................... 9 2.2. Power and Ground Pins............................... 10 4.1. Functional Redundancy Checking Mode.....38 2.3. Decoupling Guidelines ................................. 10 4.2. Low Power States and Clock Control ..........39 2.3.1. PENTIUM® II XEON™ PROCESSOR 4.2.1. NORMAL STATE—STATE 1 ...............39 VCCCORE............................................ 11 4.2.2. AUTO HALT POWER DOWN 2.3.2. LEVEL 2 CACHE DECOUPLING ........ 11 STATE—STATE 2................................39 2.3.3. SYSTEM BUS AGTL+ 4.2.3. STOP-GRANT STATE—STATE 3.......40 DECOUPLING...................................... 11 4.2.4. HALT/GRANT SNOOP STATE— 2.4. System Bus Clock and Processor STATE 4 ...............................................40 Clocking ....................................................... 11 4.2.5. SLEEP STATE—STATE 5 ...................41 2.4.1. MIXING PROCESSORS OF 4.2.6. CLOCK CONTROL ..............................41 DIFFERENT FREQUENCIES AND 4.3. System Management Bus (SMBus) CACHE SIZES...................................... 14 Interface .......................................................41 2.5. Voltage Identification .................................... 14 4.3.1. PROCESSOR INFORMATION ROM ..42 2.6. System Bus Unused Pins and Test Pins ..... 16 4.3.2. SCRATCH EEPROM ...........................45 2.7. System Bus Signal Groups.......................... 16 4.3.3. PROCESSOR INFORMATION ROM 2.7.1. ASYNCHRONOUS VS. AND SCRATCH EEPROM SYNCHRONOUS FOR SYSTEM BUS SUPPORTED SMBUS SIGNALS .............................................. 18 TRANSACTIONS .................................45 2.8. Test Access Port (TAP) Connection............ 18 4.3.4. THERMAL SENSOR ............................46 2.9. Maximum Ratings ........................................ 18 4.3.5. THERMAL SENSOR SUPPORTED 2.10. Processor DC Specifications .................. 19 SMBUS TRANSACTIONS ...................47 2.11. AGTL+ System Bus Specifications......... 23 4.3.6. THERMAL SENSORS REGISTERS ...49 2.12. System Bus AC Specifications ............... 24 4.3.6.1. Thermal Reference Registers........49 4.3.6.2. Thermal Limit Registers .................49 3.0. SIGNAL QUALITY .......................................... 33 4.3.6.3. Status Register ..............................49 3.1. System Bus Clock Signal Quality 4.3.6.4. Configuration Register ...................49 Specifications............................................... 34 4.3.6.5. Conversion Rate Register..............50 3.2. AGTL+ Signal Quality Specifications........... 35 4.3.7. SMBUS DEVICE ADDRESSING .........50 3.2.1. AGTL+ RINGBACK TOLERANCE SPECIFICATIONS ............................... 35 5.0. THERMAL SPECIFICATIONS AND DESIGN 3.2.2. AGTL+ OVERSHOOT/UNDERSHOOT CONSIDERATIONS........................................52 GUIDELINES........................................ 36 5.1. Thermal Specifications.................................52 3.3. Non-AGTL+ Signal Quality Specifications... 37 5.1.1. POWER DISSIPATION ........................53 3 12/16/98 1:23 PM 24377003.doc PENTIUM® II XEON™ PROCESSOR AT 400 AND 450 MHZ E 5.1.2. PLATE FLATNESS 8.1.4.4. Signal Note: TCK ...........................83 SPECIFICATION.................................. 54 8.1.5. USING BOUNDARY SCAN TO 5.2. Processor Thermal Analysis........................ 54 COMMUNICATE TO THE 5.2.1. THERMAL SOLUTION PROCESSOR.......................................85 PERFORMANCE ................................. 54 8.2. Integration Tool (Logic Analyzer) 5.2.2. THERMAL PLATE TO COOLING Considerations .............................................85 SOLUTION INTERFACE 8.2.1. INTEGRATION TOOL MECHANICAL MANAGEMENT GUIDE ....................... 55 KEEPOUTS ..........................................85 5.2.3. MEASUREMENTS FOR THERMAL SPECIFICATIONS ............................... 57 9.0. APPENDIX ......................................................86 5.2.3.1. Thermal Plate Temperature 9.1. Alphabetical Signals Reference....................86 Measurement................................. 57 9.1.1. A[35:03]# (I/O) ......................................86 5.2.3.2. Cover Temperature Measurement 9.1.2. A20M# (I) ..............................................86 Guideline........................................ 58 9.1.3. ADS# (I/O) ............................................86
Recommended publications
  • Inside Intel® Core™ Microarchitecture Setting New Standards for Energy-Efficient Performance
    White Paper Inside Intel® Core™ Microarchitecture Setting New Standards for Energy-Efficient Performance Ofri Wechsler Intel Fellow, Mobility Group Director, Mobility Microprocessor Architecture Intel Corporation White Paper Inside Intel®Core™ Microarchitecture Introduction Introduction 2 The Intel® Core™ microarchitecture is a new foundation for Intel®Core™ Microarchitecture Design Goals 3 Intel® architecture-based desktop, mobile, and mainstream server multi-core processors. This state-of-the-art multi-core optimized Delivering Energy-Efficient Performance 4 and power-efficient microarchitecture is designed to deliver Intel®Core™ Microarchitecture Innovations 5 increased performance and performance-per-watt—thus increasing Intel® Wide Dynamic Execution 6 overall energy efficiency. This new microarchitecture extends the energy efficient philosophy first delivered in Intel's mobile Intel® Intelligent Power Capability 8 microarchitecture found in the Intel® Pentium® M processor, and Intel® Advanced Smart Cache 8 greatly enhances it with many new and leading edge microar- Intel® Smart Memory Access 9 chitectural innovations as well as existing Intel NetBurst® microarchitecture features. What’s more, it incorporates many Intel® Advanced Digital Media Boost 10 new and significant innovations designed to optimize the Intel®Core™ Microarchitecture and Software 11 power, performance, and scalability of multi-core processors. Summary 12 The Intel Core microarchitecture shows Intel’s continued Learn More 12 innovation by delivering both greater energy efficiency Author Biographies 12 and compute capability required for the new workloads and usage models now making their way across computing. With its higher performance and low power, the new Intel Core microarchitecture will be the basis for many new solutions and form factors. In the home, these include higher performing, ultra-quiet, sleek and low-power computer designs, and new advances in more sophisticated, user-friendly entertainment systems.
    [Show full text]
  • Pentium II Processor Performance Brief
    PentiumÒ II Processor Performance Brief January 1998 Order Number: 243336-004 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Pentium® II processor may contain design defects or errors known as errata. Current characterized errata are available on request. MPEG is an international standard for video compression/decompression promoted by ISO. Implementations of MPEG CODECs, or MPEG enabled platforms may require licenses from various entities, including Intel Corporation. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from by calling 1-800-548-4725 or by visiting Intel’s website at http://www.intel.com.
    [Show full text]
  • Intel Architecture Optimization Manual
    Intel Architecture Optimization Manual Order Number 242816-003 1997 5/5/97 11:38 AM FRONT.DOC Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Pentium®, Pentium Pro and Pentium II processors may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Such errata are not covered by Intel’s warranty. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O.
    [Show full text]
  • Multiprocessing Contents
    Multiprocessing Contents 1 Multiprocessing 1 1.1 Pre-history .............................................. 1 1.2 Key topics ............................................... 1 1.2.1 Processor symmetry ...................................... 1 1.2.2 Instruction and data streams ................................. 1 1.2.3 Processor coupling ...................................... 2 1.2.4 Multiprocessor Communication Architecture ......................... 2 1.3 Flynn’s taxonomy ........................................... 2 1.3.1 SISD multiprocessing ..................................... 2 1.3.2 SIMD multiprocessing .................................... 2 1.3.3 MISD multiprocessing .................................... 3 1.3.4 MIMD multiprocessing .................................... 3 1.4 See also ................................................ 3 1.5 References ............................................... 3 2 Computer multitasking 5 2.1 Multiprogramming .......................................... 5 2.2 Cooperative multitasking ....................................... 6 2.3 Preemptive multitasking ....................................... 6 2.4 Real time ............................................... 7 2.5 Multithreading ............................................ 7 2.6 Memory protection .......................................... 7 2.7 Memory swapping .......................................... 7 2.8 Programming ............................................. 7 2.9 See also ................................................ 8 2.10 References .............................................
    [Show full text]
  • PDSM4+ 1.0.Indb
    PDSM4+ PDSME+ USER’S MANUAL Revision 1.0 The information in this User’s Manual has been carefully reviewed and is believed to be accurate. The vendor assumes no responsibility for any inaccuracies that may be contained in this document, makes no commitment to update or to keep current the information in this manual, or to notify any person or organization of the updates. Please Note: For the most up-to-date version of this manual, please see our web site at www.supermicro.com. SUPERMICRO COMPUTER reserves the right to make changes to the product described in this manual at any time and without notice. This product, including software, if any, and documenta- tion may not, in whole or in part, be copied, photocopied, reproduced, translated or reduced to any medium or machine without prior written consent. IN NO EVENT WILL SUPERMICRO COMPUTER BE LIABLE FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING FROM THE USE OR INABILITY TO USE THIS PRODUCT OR DOCUMENTATION, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. IN PARTICULAR, THE VENDOR SHALL NOT HAVE LIABILITY FOR ANY HARDWARE, SOFTWARE, OR DATA STORED OR USED WITH THE PRODUCT, INCLUDING THE COSTS OF REPAIRING, REPLACING, INTEGRATING, INSTALLING OR RECOVERING SUCH HARDWARE, SOFTWARE, OR DATA. Any disputes arising between manufacturer and customer shall be governed by the laws of Santa Clara County in the State of California, USA. The State of California, County of Santa Clara shall be the exclusive venue for the resolution of any such disputes. Supermicro's total liability for all claims will not exceed the price paid for the hardware product.
    [Show full text]
  • VX97 User's Manual ASUS CONTACT INFORMATION Asustek COMPUTER INC
    R VX97 Pentium Motherboard USER'S MANUAL USER'S NOTICE No part of this manual, including the products and softwares described in it, may be repro- duced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means, except documentation kept by the purchaser for backup pur- poses, without the express written permission of ASUSTeK COMPUTER INC. (“ASUS”). ASUS PROVIDES THIS MANUAL “AS IS” WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OR CONDITIONS OF MERCHANTABILITY OR FITNESS FOR A PAR- TICULAR PURPOSE. IN NO EVENT SHALL ASUS, ITS DIRECTORS, OFFICERS, EMPLOYEES OR AGENTS BE LIABLE FOR ANY INDIRECT, SPECIAL, INCIDEN- TAL, OR CONSEQUENTIAL DAMAGES (INCLUDING DAMAGES FOR LOSS OF PROFITS, LOSS OF BUSINESS, LOSS OF USE OR DATA, INTERRUPTION OF BUSI- NESS AND THE LIKE), EVEN IF ASUS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES ARISING FROM ANY DEFECT OR ERROR IN THIS MANUAL OR PRODUCT. Products and corporate names appearing in this manual may or may not be registered trade- marks or copyrights of their respective companies, and are used only for identification or explanation and to the owners’ benefit, without intent to infringe. • Intel, LANDesk, and Pentium are registered trademarks of Intel Corporation. • IBM and OS/2 are registered trademarks of International Business Machines. • Symbios is a registered trademark of Symbios Logic Corporation. • Windows and MS-DOS are registered trademarks of Microsoft Corporation. • Sound Blaster AWE32 and SB16 are trademarks of Creative Technology Ltd. • Adobe and Acrobat are registered trademarks of Adobe Systems Incorporated.
    [Show full text]
  • MICROPROCESSOR REPORT the INSIDERS’ GUIDE to MICROPROCESSOR HARDWARE Slot Vs
    VOLUME 12, NUMBER 1 JANUARY 26, 1998 MICROPROCESSOR REPORT THE INSIDERS’ GUIDE TO MICROPROCESSOR HARDWARE Slot vs. Socket Battle Heats Up Intel Prepares for Transition as Competitors Boost Socket 7 A A look Look by Michael Slater ship as many parts as they hoped, especially at the highest backBack clock speeds where profits are much greater. The past year has brought a great deal The shift to 0.25-micron technology will be central to of change to the x86 microprocessor 1998’s CPU developments. Intel began shipping 0.25-micron A market, with Intel, AMD, and Cyrix processors in 3Q97; AMD followed late in 1997, IDT plans to LookA look replacing virtually their entire product join in by mid-98, and Cyrix expects to catch up in 3Q98. Ahead ahead lines with new devices. But despite high The more advanced process technology will cut power con- hopes, AMD and Cyrix struggled in vain for profits. The sumption, allowing sixth-generation CPUs to be used in financial contrast is stark: in 1997, Intel earned a record notebook systems. The smaller die sizes will enable higher $6.9 billion in net profit, while AMD lost $21 million for the production volumes and make it possible to integrate an L2 year and Cyrix lost $6 million in the six months before it was cache on the CPU chip. acquired by National. New entrant IDT added another com- The processors from Intel’s challengers have lagged in petitor to the mix but hasn’t shipped enough products to floating-point and MMX performance, which the vendors become a significant force.
    [Show full text]
  • Pentium® Ii Processor at 233 Mhz, 266 Mhz, 300
    E PENTIUM® II PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ n Available at 233 MHz, 266 MHz, n Optimized for 32-bit applications 300 MHz, and 333 MHz core running on advanced 32-bit operating frequencies systems n Binary compatible with applications n Single Edge Contact (S.E.C.) cartridge running on previous members of the packaging technology; the S.E.C. Intel microprocessor line cartridge delivers high performance n Dynamic Execution micro architecture with improved handling protection and socketability n Dual Independent Bus architecture: n Separate dedicated external System Integrated high performance 16 KB Bus and dedicated internal high-speed instruction and 16 KB data, cache bus nonblocking, level one cache n n Intel’s highest performance processor Available with integrated 512 KB combines the power of the Pentium® unified, nonblocking, level two cache Pro processor with the capabilities of n Enables systems which are scaleable MMX™ technology up to two processors and 64 GB of n Power Management capabilities physical memory System Management mode n Error-correcting code for System Bus Multiple low-power states data The Intel Pentium® II processor is designed for high-performance desktops, workstations and mainstream servers, and is binary compatible with previous Intel Architecture processors. The Pentium II processor provides the best performance available for applications running on advanced operating systems such as Windows* 95, Windows NT and UNIX*. This is achieved by integrating the best attributes of Intel’s processors — the dynamic execution performance of the Pentium Pro processor plus the capabilities of MMX™ technology — bringing a new level of performance for system buyers.
    [Show full text]
  • MP Assignment V.Pages
    MP Assignment V 1. A. With a neat diagram, explain the internal structure of Pentium Pro. The Pentium Pro is structured d i f f e r e n t l y t h a n e a r l i e r microprocessors. The system buses, which communicate to the memory and I/O, connect to an internal level 2 cache that is often on the main board in most other microprocessor systems. The level 2 cache in the Pentium Pro is either 256K bytes or 512K bytes. The bus interface unit (BIU) controls the access to the system buses through the level 2 cache, which is integrated in Pentium Pro. The BIU generates the memory address and control signals, and passes and fetches data or instructions to either a level 1 data cache or a level 1 instruction cache. The instruction cache is connected to the instruction fetch and decode unit (IFDU). Pentium Pro can process two integer instructions and one floating-point instruction simultaneously. The dispatch and execute unit (DEU) retrieves decoded instructions from the instruction pool when they are complete, and then executes them. Pentium Pro has a RU (Retire unit) which checks the instruction pool and removes decoded instructions that have been executed. B. List the new features added to Pentium Pro when compared with its predecessors with respect to memory system. The memory system for the Pentium Pro microprocessor is 4G bytes in size, similar to 80386DX–Pentium microprocessors, but access to an area between 4G and 64G is made possible by additional address signals A32-35.
    [Show full text]
  • XAPP196 "Interfacing a Virtex-E Device to a Pentium Processor" V1.0
    Product Obsolete/Under Obsolescence Application Note: Virtex Series R Interfacing a Virtex-E Device to a Pentium Processor XAPP196 (v1.0) December 15, 2000 Summary This application note describes a reference design for a Virtex™-E FPGA interface to an Intel Pentium™ processor. The Pentium I system bus, design concerns, and possible applications of this design are discussed. Additionally, the differences between the Pentium I, II, and III busses are discussed. For more information specific to the Intel Pentium family of processors, see the Intel developer website (http://developer.intel.com/). Design General Discussion The design was synthesized using FPGA Express 3.4 (Verilog) and implemented using Foundation ISE version 3.1i. Internally, the FPGA design has been constrained to run at 100 MHz. However, the Intel Pentium processor system bus runs at only 66 MHz. To account for this discrepancy, two asynchronous FIFOs are used allowing the internal design to run at a higher frequency than the bus (Figure 3). Data is taken from the bus at 66 MHz, processed at a higher speed, and returned to the processor over the bus at 66 MHz. For more information, see the Pentium data sheet at (http://developer.intel.com/design/intarch/pentium/pentium.htm). The Pentium I and II system busses run at 66 MHz. The Pentium III system bus runs at either 100MHz or 133 MHz. These processors are used when fast bus transactions are necessary. A discussion of how to adapt the reference design to the Pentium II and III architecture is included on page 4. The reference design was created using an Intel Pentium 166 MHz embedded processor, and a Spartan™-II XC2S50.
    [Show full text]
  • Intel Pentium 4 and Intel Xeon Processor Optimization
    Intel® Pentium® 4 and Intel® Xeon™ Processor Optimization Reference Manual Issued in U.S.A. Order Number: 248966-007 World Wide Web: http://developer.intel.com INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel prod- ucts are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. This Intel Pentium 4 and Intel Xeon Processor Optimization Reference Manual as well as the software described in it is fur- nished under license and may only be used or copied in accordance with the terms of the license. The information in this manual is furnished for informational use only, is subject to change without notice, and should not be construed as a com- mitment by Intel Corporation. Intel Corporation assumes no responsibility or liability for any errors or inaccuracies that may appear in this document or any software that may be provided in association with this document. Except as permitted by such license, no part of this document may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.
    [Show full text]
  • 5 Microprocessors
    Color profile: Disabled Composite Default screen BaseTech / Mike Meyers’ CompTIA A+ Guide to Managing and Troubleshooting PCs / Mike Meyers / 380-8 / Chapter 5 5 Microprocessors “MEGAHERTZ: This is a really, really big hertz.” —DAVE BARRY In this chapter, you will learn or all practical purposes, the terms microprocessor and central processing how to Funit (CPU) mean the same thing: it’s that big chip inside your computer ■ Identify the core components of a that many people often describe as the brain of the system. You know that CPU CPU makers name their microprocessors in a fashion similar to the automobile ■ Describe the relationship of CPUs and memory industry: CPU names get a make and a model, such as Intel Core i7 or AMD ■ Explain the varieties of modern Phenom II X4. But what’s happening inside the CPU to make it able to do the CPUs amazing things asked of it every time you step up to the keyboard? ■ Install and upgrade CPUs 124 P:\010Comp\BaseTech\380-8\ch05.vp Friday, December 18, 2009 4:59:24 PM Color profile: Disabled Composite Default screen BaseTech / Mike Meyers’ CompTIA A+ Guide to Managing and Troubleshooting PCs / Mike Meyers / 380-8 / Chapter 5 Historical/Conceptual ■ CPU Core Components Although the computer might seem to act quite intelligently, comparing the CPU to a human brain hugely overstates its capabilities. A CPU functions more like a very powerful calculator than like a brain—but, oh, what a cal- culator! Today’s CPUs add, subtract, multiply, divide, and move billions of numbers per second.
    [Show full text]