Both 8086 / 8088 are packaged as 40-pin DIPs. In micro-electronics DIP stands for Dual in-line package. DIP packaging refers to a rectangular housing with two parallel rows of electrical connection pins.

DIP chips have a notch one one end to show its correct orientation. The pins are then numbered ACW as shown in the figure below.

5 8086 is a 16 bit microprocessor (announced in 1978)with a 16 bit data bus and the 8088 is a 16 bit microprocessor(announced in 1979) with an 8 bit data bus. So why is 8088 a 16 bit microprocessor if its data bus is 8 bits ? What factor decides how many bits a microprocessor is regarded to be? Differences between 8086 and 8088: • Data bus size is different. • Control signal – M/IO (8086) IO/M (8088) • Hardware Difference – Pin 34 – SSO Pin (8088) BHE/S7 pin (8086) 6 Power Requirements Both Processors manufactured using High-performance metal oxide semiconductor(HMOS) technology. Both Processors require +5.0V with a supply voltage tolerance of ±10%. Both consists of about 29000 transistors packedin 40-pin dual-in- line (DIP) package

8086 draws a maximum current supply of 360mA 8088 draws a maximum current supply of 340mA Ambient temperature for use is 32ºF – 180ºF Not suitable for outdoor use.

7 DC Characteristics

Remember we have been talking about 0 and 1s so far. In every connection we said that we either send a 0 or a 1 through the pins.

So what is 0 and what is 1? How do we represent a 0 and 1 on the pin in real life ? We use voltage. But, then what voltage counts as 1 and what counts as 0?

8 It is also important to know the current of the pins so that we do not interface that may work incorrectly and may even damage the processor.

What do you notice here in regards to the gap between the voltage that represents 0 and 1.

9 I don’t want you to memorize these numbers ? So why do you think I am showing you these ? The gap in the voltage is known as noise immunity. Noise refers to unwanted signal within some signal that you are trying to send.

The noise immunity is the amount of noise the can be tolerated before an error would occur.

The processor has a noise immunity of 350mV. Noise can occur from long connection links or from connecting multiple devices. Long links are hardly used during interfacing but multiple devices are connected to a microprocessor. 10 It is recommended that no more than 10 loads of any type or combination be connected to an output pin without buffering.

We will study this in a while when we speak about buffering in details. First we need to discuss the pin connections that we have on the processor as shown in the diagram previously.

11 MINIMUM AND MAXIMUN MODE • when only one 8086 CPU is used in a microcomputer system– MINIMUM MODE • in this mode CPU issues the control signals required by memory and I/O devices •In a multiprocessor it operates in MAXIMUM MODE •Operation control signals are issued by Intel 8288 bus controller •Pin 24 to 31 have alternate functions according to MN/MX

12 8086 Pin Specification

S3,S4—SEGMENT IDENTIFIER

BUS HIGH ENABLE S5—INTERRUPT STATUS S6—STATUS SIGNAL

13 Inside The 8088/8086

Concepts important to the internal operation of 8088/8086

• Pipelining • Registers Inside The 8088/8086…pipelining • Pipelining – Two ways to make CPU process information faster: • Increase the working frequency – technology dependent • Change the internal architecture of the CPU – Pipelining is to allow CPU to fetch and execute at the same time Inside The 8088/8086…pipelining

Intel implemented the concept of pipelining by splitting the internal structure of the 8088/8086 into two sections that works simultaneously:

• Execution Unit (EU) – executes instructions previously fetched

• Bus Interface Unit (BIU) – accesses memory and peripherals Internal Architecture of 8086 Architecture of 8086 contd… • Fetching the next instruction while current instruction is under execution is called pipelining. • What happens to queue when jump or call instruction is executed ?

• When 8086 is reset the contents of IP are 0000 H and contents of CS are FFFF H. Other registers are cleared to 0000 h. Memory Segmentation Advantages of memory segmentation

} Allow the memory capacity to be 1Mb even though the addresses associated with the individual instructions are only 16 bits wide. } Facilitate the use of separate memory areas for the program, its data and the stack. } Permit a program and/or its data to be put into different areas of memory each time the program is executed. } Multitasking becomes easy. Inside The 8088/8086

AH AL BH BL CH CL DH DL

Inside The 8088/8086…registers • Registers AX – To store information temporarily 16-bit register AH AL 8-bit reg. 8-bit reg.

Category Bits Register Names General 16 AX, BX, CX, DX 8 AH, AL, BH, BL, CH, CL, DH, DL Pointer 16 SP (stack pointer), BP (base pointer) Index 16 SI (source index), DI (destination index) Segment 16 CS (code segment), DS (data segment) SS (stack segment), ES (extra segment) Instruction 16 IP (instruction pointer) Flag 16 FR (flag register)

General Registers I • AX – ‘Accumulator’ • accumulator for operands and results data • usually used to store the return value of a procedure • BX – ‘Base Register’

• pointer to data in the DS segment • CX – ‘Counter’ • counter for string and loop operations • DX – ‘Data Register’ • I/O pointer General Registers II

• SI – ‘Source Index’ • source pointer for string operations • typically a pointer to data in the segment pointed to by the DS register • DI – ‘Destination Index’ • destination pointer for string operations • typically a pointer to data/destination in the segment pointed to by the ES register Overview • Registers – General purpose registers (8) • Operands for logical and arithmetic operations • Operands for address calculations • Memory pointers – Segment registers (6) – FLAGS register – The instruction pointer register • The stack General Registers III

• BP – ‘Base Pointer’ • pointer to data on the stack • points to the current stack frame of a procedure • SP – ‘Stack Pointer’ • pointer to the top address of the stack • holds the stack pointer and as a general rule should not be used for any other purpose Segment Registers • CS – ‘Code Segment’ – contains the segment selector for the code segment where the instructions being executed are stored • DS(ES,FS,GS) – ‘Data Segment’ – contains the segment selectors for the data segment where data is stored • SS – ‘Stack Segment’ – contains the segment selector for the stack segment, where the procedure stack is stored The EFLAGS Register I • – CF (bit 0) – Set if an arithmetic operation generates a carry or a borrow out of the most-significant bit of the result; cleared otherwise. • – PF (bit 2) – Set if the least -significant byte of the result contains an even number of 1 bits; cleared otherwise. • Adjust Flag – AF (bit 4) – Set if an arithmetic operation generates a carry or a borrow out of bit 3 of the result; cleared otherwise. The EFLAGS Register II

• – ZF (bit 6) – Set if the result is zero; cleared otherwise • Sign Flag – SF (bit 7) – Set equal to the most-significant bit of the result, which is the sign bit of a signed integer • – OF (bit 11) – Set if the integer result is too large a positive number or too small a negative number (excluding the sign-bit) to fit in the destination operand; cleared otherwise Instruction Pointer

• IP – ‘Instruction Pointer’ – Contains the offset within the code segment of the next instruction to be executed – Cannot be accessed directly by software The Stack The stack starts in high memory and grows toward low memory

SP Current stack frame BP stack Caller’s growth stack frame Pin Connections AD15 – AD0: Address/Data bus lines. These are multiplexed lines. Line carries address when ALE =1 Line carries data when ALE =0

AD19/S6 – A13/S3: Address/Status bus bits are multiplexed to provide address signals A19-A16 and status bits S6-S3. S6 – always remains 0 S5 – indicates the condition of the S4 and S3 – Indicate the segment being accessed during current bus cycle. 35 RD: When this read signal pin is at logic 0, the data bus is receptive to data from memory or I/O devices. READY: This pin is used to enforce a waiting state. READY pin at 0 – the microprocessor goes into idle state. READY pin at 1 – the microprocessor does normal operation.

36 INTR: Interrupt request pin is used to request a hardware interrupt. If INTR is held at high when IF =1, the processor goes into the interrupt acknowledgement cycle. INTA becomes active when interrupt is being serviced.

TEST: Test pin is an input that is tested by the WAIT instruction. If the test pin is at logic 0 the WAIT instruction functions as NOP. If test is a logic 1, the WAIT instruction wait for TEST to become logic 0. Commonly used with 8087 numeric coprocessor connections.

37 NMI: Non-maskable interrupt input is similar to INTR expect that the NMI interrupt does not check IF or priority. Use Interrupt Vector 2.

RESET: If this reset pin is held high for 4 clock cycles the microprocessor resets. When 8086 or 8088 is reset it begins execution at memory location FFFF0H and clears the IF. CLK: 38 The clock pin is used to connect a clock generator Vcc: The power supply. +5V should be connected to this pin. GND: The ground connection for the microprocessor .

MN/MX: The minimum/maximum mode pin selects the mode for the processor. To select minimum mode processor should be connected directly to +5.0V and to select maximum mode processor should be connected directly to GND.

39 BHE/S7: The bus high enable pin is used in the 8086 to enable the Most significant data bus bits during a read or write operation.

40 Pin Connections ( Minimum)

IO/M This pin indicates whether the address bus contains a memory address or an I/O port address. WR: The write line is a used when the microprocessor is writing data to memory and the memory bus contains a valid address.

41 INTA: Interrupt acknowledgement signals is a response to INTR input pin. This is used when the interrupt vector is placed on the address bus by the microprocessor.

ALE: Address Latch enable shows whether the multiplexed AD lines carry address or data.

DT/R: Data transmit/receive shows that the microprocessor data bus is transmitting(1) or receiving(0) data. This is used to control buffers. 42 DEN: Data Enable bus activates external data bus buffers.

HOLD: HOLD pin is used to input request DMA. Hold set to 1 microprocessor gives up control of buses to DMA controller .

SS0: This is equivalent S0 in the maximum mode pins.

43 Maximum Mode Pins S2, S1 and S0: These signal bits indicate the function of the current bus cycle. These pins are used for special purpose which we will discuss in a bit.

RO/GT1 and R0/GTO: Requests/grants pins request direct memory access during maximum mode operation. LOCK: Lock output is used to lock peripherals off the system.

QS0 and QS1: Queue status bits show the status of the internal instruction queue. 44 Anatomy of a Register

Extended Register Word Register

Bits 16-31 Bits 8-15 Bits 0-7

High Byte Low Byte Register Register General Registers

32 bit Registers 16 bit Registers 8 bit Registers

AX BP AX BP AH AL

BX SI BX SI BH BL

CX DI CX DI CH CL

DX SP DX SP DH DL Bits 16-31 Bits 8-15 Bits 0-7 Clock Generator 8284A

47 Clock Generator

48 Clock/Reset/Ready Circuit • The 8284 chips serves three 8284 8086/8088 purposes: 3MHz X1 PCLK – Generates the main clock 15MHz 15MHz (CLK) for the processor OSC

(fc/3 with 33% duty cycle) 5MHz and the clock for the X2 CLK CLK +5V peripheral devices (fc/5). On/Off – Provides the Reset pulse 10K according to the state of 100 the RC circuit connected RES RESET RESET

at the RES input. Reset – Provides the Ready signal 10uF to insert wait states whenever the processor is READY READY RDY accessing slow memory or peripheral I/O ports. Wait State Circuit

ACOE255 49 Functions of Interest to us now: • Clock generation – The clock generation uses a crystal. Crystal generates square waves at the frequency of the crystal. There is a divide-by-3 counter causing the frequency of the crystal to be divided by 3 at the 8086. So a 15 MHz XTAL causes the 8086 to run at 5MHz. • RESET Synchronization – The reset are synchronized and to reset the processor pin must be held high for 4 cycles. • Ready Synchronization – DMA sync may require clock to be stopped during waiting state. • Peripheral clock signal. – The peripheral frequency has a further divide-by-2 counter. So 15 MHz XTAL gives clock frequency of 2.5MHz at the peripherals. 50 Bus Buffering and Latching The microprocessor has 3 buses: • Control • Address • Data

The address and the data bus are multiplexed due to pin limitations. The ALE pin is used to control the set of latches.

51 Why latch? So that we can control devices that use the same common buses which may carry either data or address information.

Why Buffer? For read and write operations to be correctly implemented the data on the lines need to be stable throughout the instructions. Due to multiplexing and switching between instructions that make different use of buses we need to buffer data in order for us to have stable data through out an instruction. 52 53 Bus Timing In 8086 the concept of machine cycle is no longer applicable. The EU executes instruction in certain clock periods which do not constitute any form of machine cycles. The BIU fetches instructions and operants from the memory. Any external access either to M/IO device require 4 clock periods called bus cycle. So the 8086/8088 microprocessors use the memory and I/O in periods called bus cycles. Each bus cycle consists of 4 clock cycles. Thus for 8086 running at 5MHz it would take 800ns for a complete bus cycle. Each read or write operation take 1 bus cycles. 54 Read Timing

55 Read Timing

During T 1 : •The address is placed on the Address/Data bus. ADO-AD15 carry 16 LSBs of the address and A16-A19 carry four MSBs of the address.The address remains on the address lines only during T1 because these lines operate in multiplexed mode. •During T2 AD0-AD15 lines remain in high impedance state •Control signals M/ IO , ALE and DT/ R specify memory or I/O, latch the address onto the address bus and set the direction MN/MX of data transfer on data bus. 56 Read Timing

During T 2 : •8086 issues the RD or WR signal, DEN , and, for a write, the data. •DEN enables the memory or I/O device to receive the data for writes and the 8086 to receive the data for reads. •During T2,T3 and T4 status signals S3,S4,S5and S6 are carried by A16- A19 lines.

57 During T 3 : •This cycle is provided to allow memory to access data.

•READY is sampled at the end of T 2 . •If low, T 3 becomes a wait state. •Otherwise, the data bus is sampled at the end of T 3 . During T 4 : •All bus signals are deactivated, in preparation for next bus cycle. 58 •Data is sampled for reads, writes occur for writes. During T 4 : •All bus signals are deactivated, in preparation for next bus cycle. •Data is sampled for reads, writes occur for writes. 59 BHE/S7 •DT/R goes low during T1. This signal is used by transceiver 8286 or 8287 if it is used in the system. •DT/R and DEN signals are used to control bidirectional latched buffers. •BHE in conjuction with A0 decides whether a byte or word is to be transferred from/to memory locations. •BHE identifies high order byte of memory word whereas A0 identifies low order byte. •On BHE line the status signal S7 is transmitted during T2,T3 and T4. 60 For word and byte access the status of BHE and A0 as follows

BHE A0

0 0 Whole word is transferred 0 1 Upper byte from/to odd address 1 0 Lower byte from/to even address 1 1 None

S3 and S4 identify the memory segment which is being accessed. S5 is interrupt enable status. For memory access S6 is always zero and S3 and S4 are as follows S4 S3

0 0 Extra segment access 0 1 Stack segment access 1 0 Code segment access or no access 1 1 Data segment access

61 Write Timing

Convert this simple timeline to include all the necessary pins

Do as an EXERCISE ! 62 WRITE CYCLE

‹HERE WE WILL SEE THE ACTIVITIES CARRIED OUT ON 8086 BUS AT VARIOUS TIME INSTANTS WHEN IT WRITES TO A PORT OR A MEMORY LOCATION.

‹HERE WE WILL ASSUME THAT THE 8086 IS OPERATED IN IS MINIMUM MODE. T1 T2 T3 TW T4

CLK

M/IO

ALE ADDR/ DATA A15 -A0 DATA OUT (D15 -D0) ADDR/ A19-A16 STATUS WR READY DT/R DEN MIN and MAX Mode

•Controlled through the MN/ MX pin.

•Minimum mode is cheaper since all control signals for memory and I/O are generated by the microprocessor.

•Maximum mode is designed to be used when a coprocessor (8087) exists in the system.

65 What is the apparent problem ?

66 •Some of the control signals must be generated externally, due to redefinition of certain control pins on the 8086.

•The following pins are lost when the 8086 operates in Maximum mode . •ALE •WR •IO/ M •DT/ R •DEN •INTA

67 Bus Controller

68 Typical -based computer system in Max mode configuration

8288-BUS CONTROLLER

8282

PROM, DMA CONTROLLER ETC.

No need to learn 8288 architecture. Its just for reference! 69 32-bit Instructions • Instructions are represented in memory by a series of “opcode bytes.” • A variance in instruction size means that disassembly is position specific. • Most instructions take zero, one, or two arguments: instruction destination, source

For example: add ax, ex is equivalent to the expression ax = ax + bx

Rule #3: If a value less than FFH is moved into a 1616--bitbit register,register, the rest of the bits are assumed to be all zeros. MOV BX, 5 BX =0005 BH = 00, BL = 05

Program Segments

• A segment is an area of memory that includes up to 64K bytes • Begins on an address evenly divisible by 16 • 8085 could address a max. of 64K bytes of physical memory - it has only 16 pins for the address lines (2 16 = 64K)

• 8088/86 stayed compatible with 8085 - Range of 1MB of memory, it has 20 address pins (2 20 = 1 MB) - Can handle 64KB of code, 64KB of data, 64KB of stack

• A typical Assembly language program consist of three segments: • Code segments • Data segment • Stack segment Program Segments…a sample Program Segments Program Segments Code segment

The 8086 fetches the instructions (opcodes and operands) from the code segments. The 8086 address types: – Physical address – Offset address – Logical address • Physical address – 20-bit address that is actually put on the address pins of 8086 – Decoded by the memory interfacing circuitry – A range of 00000H to FFFFFH – It is the actual physical location in RAM or ROM within 1 MB mem. range • Offset address – A location within a 64KB segment range – A range of 0000H to FFFFH • Logical address – consist of a segment value and an offset address Program Segments…example

Define the addresses for the 8086 when it fetches the instructions (opcodes and operands) from the code segments.

• Logical address : – Consist of a CS (code segment) and an IP (instruction pointer) format is CS:IP

• Offset address – IP contains the offset address

• Physical address – generated by shifting the CS left one hex digit and then adding it to the IP – the resulting 20-bit address is called the physical address give me some numbers…ok Program Segments…example

Suppose we have: CS 2500 IP 95F3

• Logical address : – Consist of a CS (code segment) and an IP (instruction pointer) format is CS:IP 2500:95F3H

• Offset address – IP contains the offset address which is 95F3H

• Physical address – generated by shifting the CS left one hex digit and then adding it to the IP 25000 + 95F3 = 2E5F3H Program Segments Data segment

Data segment refers to an area of memory set aside for data • Format DS:BX or DI or SI • example: DS:0200 = 25 DS:0201 = 12 DS:0202 = 15 DS:0203 = 1F DS:0204 = 2B Program Segments Data segment Example: Add 5 bytes of data: 25H, 12H, 15H, 1FH, 2BH

Not using data segment

MOV AL,00H ;clear AL ADD AL,25H ;add 25H to AL ADD AL,12H ADD AL,15H ADD AL,1FH ADD AL,2BH Program Segments Data segment Example: Add 5 bytes of data: 25H, 12H, 15H, 1FH, 2BH using data segment with a constant offset

Data location in memory: Program: DS:0200 = 25 MOV AL,0 DS:0201 = 12 ADD AL,[0200] DS:0202 = 15 ADD AL,[0201] DS:0203 = 1F ADD AL,[0202] DS:0204 = 2B ADD AL,[0203] ADD AL,[0204] Program Segments Data segment Example: Add 5 bytes of data: 25H, 12H, 15H, 1FH, 2BH

using data segment with an offset register Program: MOV AL,0 MOV BX,0200H ADD AL,[BX] INC BX ;same as “ADD BX+1” ADD AL,[BX] INC BX ADD AL,[BX] INC BX ADD AL,[BX] Endian conversion • Little endian conversion: In the case of 16-bit data, the low byte goes to the low memory location and the high byte goes to the high memory address. (Intel, Digital VAX)

• Big endian conversion: The high byte goes to low address. (Motorola)

Example: Suppose DS:6826 = 48, DS:6827 = 22, Show the contents of register BX in the instruction MOV BX,[6826] Little endian conversion: BL = 48H, and BH = 22H Program Segments Stack segment Stack A section of RAM memory used by the CPU to store information temporarily.

• Registers: SS (Stack Segment) and SP (stack Pointer)

• Operations: PUSH and POP – PUSH – the storing of a CPU register in the stack – POP – loading the contents of the stack back into the CPU

• Logical and offset address format: SS:SP Flag Register

• Flag Register () – 16-bit register – Conditional flags: CF, PF, AF, ZF, SF, OF – Control flags: TF, IF, DF

ZFZF Flag Register and ADD instruction

• Flag Register that may be affected – Conditional flags: CF, PF, AF, ZF, SF, OF Addressing Modes – Accessing operands (data) in various ways

;move contents of DS:2400H into DL ;move contents of DS:SI into CL ;move contents of AH into DS:DI

;moves contents of AX into memory ;locations DS:SI and DS:SI +1 ;move DS:BX+10 & DS:BX+10+1 ;into CX. PA= DS(sl) +BX+10 ;PA = SS (sl) + BP + 5 ;PA = DS (sl) + SI + 5

;PA = DS (sl) + DI + 20 ;PA=DS(sl)+BX+DI +8

;PA=SS(sl)+BP+SI +29 Arithmetic and Logic Instructions and Programs

Use to mask certain bits, test for zero Use to test for zero Use to clear the contents of a register also to see if two register have the same value

Assembly Language Programming Model Definition MODEL directive –selects the size of the memory model

• MODEL MEDIUM • Data must fit into 64KB • Code can exceed 64KB • MODEL COMPACT • Data can exceed 64KB • Code cannot exceed 64KB • MODEL LARGE • Data can exceed 64KB (but no single set of data should exceed 64KB) • Code can exceed 64KB • MODEL HUGE • Data can exceed 64KB (data items i.e. arrays can exceed 64KB) • Code can exceed 64KB • MODEL TINY • Data must fit into 64KB • Code must fit into 64KB • Used with COM files Program Segments…a sample Segments

Segment definition: The 80x86 CPU has four segment registers: CS, DS, SS, ES

Segments of a program: .STACK ; marks the beginning of the stack segment example: .STACK 64 ;reserves 64B of memory for the stack

.DATA ; marks the beginning of the data segment example: .DATA1 DB 52H ;DB directive allocates memory in byte-size chunks Segments .CODE ; marks the beginning of the code segment - starts with PROC (procedures) directive - the PROC directive may have the option FAR or NEAR - ends by ENDP directives Assemble, Link, and Run Program

STEP INPUT PROGRAM OUTPUT 1. Edit the program keyboard editor myfile.asm

2. Assemble the program myfile.asm MASM or TASM myfile.obj myfile.lst myfile.crf

3. Link the program myfile.obj LINK or TLINK myfile.exe myfile.map Assemble, Link, Run Files

.asm – source file .obj – machine language file .lst – list file - it lists all the Opcodes, Offset addresses, and errors that MASM detected .crf – cross-reference file - an alphabetical list of all symbols and labels used in the program as well as the program line numbers in which they are referenced .map – map file - to see the location and number of bytes used when there are many segments for code or data Data Types and Data Definition

• 80x86 data types ° 8-bit or 16-bit ° Positive or negative

° example1:

number 5 10 (101 2) will be 0000 01010

° example2:

number 514 10 (10 0000 0010 2) will be 0000 0010 0000 0010 Data Types and Data Definition

• Assembler data directives

° ORG (origin) – to indicate the beginning of the offset address ° example: ORG 0010H

° DB (define byte) – allocation of memory in byte-sized chunks ° example: DATA1 DB 25 ;decimal DATA2 DB 10001001B ;binary DATA3 DB 12H ;hex DATA4 DB ‘2591’ ;ASCII numbers DATA5 DB ? ;set aside a byte DATA6 DB ‘Hello’ ;ASCII characters DATA7 DB “O’ Hi” ;ASCII characters Data Types and Data Definition

• Assembler data directives

° DUP (duplicate) – to duplicate a given number of characters ° example: DATA1 DB 0FFH, 0FFH, 0FFH, 0FFH ;fill 4 bytes with FF Can be replaced with: DATA2 DB 4 DUP(0FFH) ;fill 4 bytes with FF

DATA3 DB 30 DUP(?) ;set aside 30 bytes

DATA4 DB 5 DUP (2 DUP (99)) ;fill 10 bytes with 99 Data Types and Data Definition

• Assembler data directives

° DW (define word) – allocate memory 2 bytes (one word) at a time ° example: DATA1 DW 342 ;decimal DATA2 DW 01010001001B ;binary DATA3 DW 123FH ;hex DATA4 DW 9,6,0CH, 0111B,’Hi’ ;Data numbers DATA5 DW 8 DUP (?) ;set aside 8 words

° EQU (equate) – define a constant without occupying a memory location ° example: COUNT EQU 25

;COUNT can be used in many places in the program Data Types and Data Definition

• Assembler data directives

° DD (define doubleword) – allocate memory 4 bytes (2 words) at a time ° example: DATA1 DD 1023 ;decimal DATA2 DD 01010001001001110110B ;binary DATA3 DD 7A3D43F1H ;hex DATA4 DD 54H, 65432H,65533 ;Data numbers

° DQ (define quadwordequate) – allocate memory 8 bytes (4 words) at a time ° example: DATA1 DQ 6723F9H ;hex DATA2 DQ ‘Hi’ ;ASCII characters DATA3 DQ ? ;nothing Data Types and Data Definition

• Assembler data directives

° DT (define ten bytes) – allocates packed BCD numbers (used in multibyte addition of BCD numbers) ° example: DATA1 DT 123456789123 ;BCD DATA2 DT ? ;nothing DATA3 DT 76543d ;assembler will convert decimal number to hex and store it Full Segment Definition

° Simple segment definition – refers to newer definition ° Microsoft MASM 5.0 or higher ° Borland’s TASM ver. 1

° Full segment definition – refers to older definition

° SEGMENT directive – indicate to the assembler the beginning of a segment ° END directive – indicate to the assembler the beginning of a segment

Example: label SEGMENT [options] ; statements label ENDS Flow Control I

• JMP location Transfers program control to a different point in the instruction stream without recording return information. jmp eax jmp 0x00934EE4 Flow Control II

• CMP value, value / Jcc location The compare instruction compares two values, setting or clearing a variety of flags (e.g., ZF, SF, OF). Various conditional jump instructions use flags to branch accordingly.

Cmp ax, 4 cmp [bp+10h], ax je 40320020 jne 40DC0020 Flow Control III

• TEST value, value / Jcc location The test instruction does a logical AND of the two values. This sets the SF, ZF, and PF flags. Various conditional jump instructions use these flags to branch.

test ax, ax test dx, 0056FCE2 jnz 40DA0020 jz 56DC0F20 Looping using zero flag

• The zero flag is set (ZF=1), when the counter becomes zero (CX=0)

• Example: add 5 bytes of data

MOV CX,05 ;CX holds the loop count MOV BX,0200H ;BX holds the offset data address MOV AL,00 ;initialize AL ADD_LP: ADD AL,[BX] ;add the next byte to AL INC BX ;increment the data pointer DEC CX ;decrement the loop counter JNZ ADD_LP ;jump to next iteration if counter ;not zero Interrupt Programming with C

• Using C “high-level assembly” • C programmers do need need to have detailed knowledge of 80x86 assembly • C programmers write programs using : – DOS function calls INT 21H – BIOS interrupts • Compilers provide functions: – int86 (calling any of the PC’s interrupts) – intdos (only for INT 21H DOS function calls) 132 Interrupt Programming with C

• Programming BIOS interrupts with C/C++ – Set registers to desired values – Call int86 • Upon return from int86, the 80x86 registers can be accesses – To access the 80x86 registers use union of the REGS structure already defined by C compiler • union REGS regin,regout; • Registers for access are 16-bit (x) or 8-bit (h) format 133 Interrupt Programming with C

Example:

/* C language Assembly language */ union REGS region,regout; regin.h.ah=0x25; /* mov ah,25h ;AH=25H */ regin.x.dx=0x4567; /* mov dx,4567h ;DH=4567H */ regin.x.si=0x1290; /* mov si, 1290h ;SI=1290H */ int86(interrupt#,®in,®out); /* int # */

134 Interrupt Programming with C

• Programming INT 21H DOS function calls with C/C++ – intdos used for DOS function calls • intdos(®in,®out); /* to be used for INT 21H only */

135