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Lecture 1-ST-8086 [Compatibility Mode]

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Lecture 1-ST-8086 [Compatibility Mode] Both 8086 / 8088 are packaged as 40-pin DIPs. In micro-electronics DIP stands for Dual in-line package. DIP packaging refers to a rectangular housing with two parallel rows of electrical connection pins. DIP chips have a notch one one end to show its correct orientation. The pins are then numbered ACW as shown in the figure below. 5 8086 is a 16 bit microprocessor (announced in 1978)with a 16 bit data bus and the 8088 is a 16 bit microprocessor(announced in 1979) with an 8 bit data bus. So why is 8088 a 16 bit microprocessor if its data bus is 8 bits ? What factor decides how many bits a microprocessor is regarded to be? Differences between 8086 and 8088: • Data bus size is different. • Control signal – M/IO (8086) IO/M (8088) • Hardware Difference – Pin 34 – SSO Pin (8088) BHE/S7 pin (8086) 6 Power Requirements Both Processors manufactured using High-performance metal oxide semiconductor(HMOS) technology. Both Processors require +5.0V with a supply voltage tolerance of ±10%. Both consists of about 29000 transistors packedin 40-pin dual-in- line (DIP) package 8086 draws a maximum current supply of 360mA 8088 draws a maximum current supply of 340mA Ambient temperature for use is 32ºF – 180ºF Not suitable for outdoor use. 7 DC Characteristics Remember we have been talking about 0 and 1s so far. In every connection we said that we either send a 0 or a 1 through the pins. So what is 0 and what is 1? How do we represent a 0 and 1 on the pin in real life ? We use voltage. But, then what voltage counts as 1 and what counts as 0? 8 It is also important to know the current of the pins so that we do not interface that may work incorrectly and may even damage the processor. What do you notice here in regards to the gap between the voltage that represents 0 and 1. 9 I don’t want you to memorize these numbers ? So why do you think I am showing you these ? The gap in the voltage is known as noise immunity. Noise refers to unwanted signal within some signal that you are trying to send. The noise immunity is the amount of noise the can be tolerated before an error would occur. The processor has a noise immunity of 350mV. Noise can occur from long connection links or from connecting multiple devices. Long links are hardly used during interfacing but multiple devices are connected to a microprocessor. 10 It is recommended that no more than 10 loads of any type or combination be connected to an output pin without buffering. We will study this in a while when we speak about buffering in details. First we need to discuss the pin connections that we have on the processor as shown in the diagram previously. 11 MINIMUM AND MAXIMUN MODE • when only one 8086 CPU is used in a microcomputer system– MINIMUM MODE • in this mode CPU issues the control signals required by memory and I/O devices •In a multiprocessor it operates in MAXIMUM MODE •Operation control signals are issued by Intel 8288 bus controller •Pin 24 to 31 have alternate functions according to MN/MX 12 8086 Pin Specification S3,S4—SEGMENT IDENTIFIER BUS HIGH ENABLE S5—INTERRUPT STATUS S6—STATUS SIGNAL 13 Inside The 8088/8086 Concepts important to the internal operation of 8088/8086 • Pipelining • Registers Inside The 8088/8086…pipelining • Pipelining – Two ways to make CPU process information faster: • Increase the working frequency – technology dependent • Change the internal architecture of the CPU – Pipelining is to allow CPU to fetch and execute at the same time Inside The 8088/8086…pipelining Intel implemented the concept of pipelining by splitting the internal structure of the 8088/8086 into two sections that works simultaneously: • Execution Unit (EU) – executes instructions previously fetched • Bus Interface Unit (BIU) – accesses memory and peripherals Internal Architecture of 8086 Architecture of 8086 contd… • Fetching the next instruction while current instruction is under execution is called pipelining. • What happens to queue when jump or call instruction is executed ? • When 8086 is reset the contents of IP are 0000 H and contents of CS are FFFF H. Other registers are cleared to 0000 h. Memory Segmentation Advantages of memory segmentation Allow the memory capacity to be 1Mb even though the addresses associated with the individual instructions are only 16 bits wide. Facilitate the use of separate memory areas for the program, its data and the stack. Permit a program and/or its data to be put into different areas of memory each time the program is executed. Multitasking becomes easy. Inside The 8088/8086 AH AL BH BL CH CL DH DL Inside The 8088/8086…registers • Registers AX – To store information temporarily 16-bit register AH AL 8-bit reg. 8-bit reg. Category Bits Register Names General 16 AX, BX, CX, DX 8 AH, AL, BH, BL, CH, CL, DH, DL Pointer 16 SP (stack pointer), BP (base pointer) Index 16 SI (source index), DI (destination index) Segment 16 CS (code segment), DS (data segment) SS (stack segment), ES (extra segment) Instruction 16 IP (instruction pointer) Flag 16 FR (flag register) General Registers I • AX – ‘Accumulator’ • accumulator for operands and results data • usually used to store the return value of a procedure • BX – ‘Base Register’ • pointer to data in the DS segment • CX – ‘Counter’ • counter for string and loop operations • DX – ‘Data Register’ • I/O pointer General Registers II • SI – ‘Source Index’ • source pointer for string operations • typically a pointer to data in the segment pointed to by the DS register • DI – ‘Destination Index’ • destination pointer for string operations • typically a pointer to data/destination in the segment pointed to by the ES register Overview • Registers – General purpose registers (8) • Operands for logical and arithmetic operations • Operands for address calculations • Memory pointers – Segment registers (6) – FLAGS register – The instruction pointer register • The stack General Registers III • BP – ‘Base Pointer’ • pointer to data on the stack • points to the current stack frame of a procedure • SP – ‘Stack Pointer’ • pointer to the top address of the stack • holds the stack pointer and as a general rule should not be used for any other purpose Segment Registers • CS – ‘Code Segment’ – contains the segment selector for the code segment where the instructions being executed are stored • DS(ES,FS,GS) – ‘Data Segment’ – contains the segment selectors for the data segment where data is stored • SS – ‘Stack Segment’ – contains the segment selector for the stack segment, where the procedure stack is stored The EFLAGS Register I • Carry Flag – CF (bit 0) – Set if an arithmetic operation generates a carry or a borrow out of the most-significant bit of the result; cleared otherwise. • Parity Flag – PF (bit 2) – Set if the least -significant byte of the result contains an even number of 1 bits; cleared otherwise. • Adjust Flag – AF (bit 4) – Set if an arithmetic operation generates a carry or a borrow out of bit 3 of the result; cleared otherwise. The EFLAGS Register II • Zero Flag – ZF (bit 6) – Set if the result is zero; cleared otherwise • Sign Flag – SF (bit 7) – Set equal to the most-significant bit of the result, which is the sign bit of a signed integer • Overflow Flag – OF (bit 11) – Set if the integer result is too large a positive number or too small a negative number (excluding the sign-bit) to fit in the destination operand; cleared otherwise Instruction Pointer • IP – ‘Instruction Pointer’ – Contains the offset within the code segment of the next instruction to be executed – Cannot be accessed directly by software The Stack The stack starts in high memory and grows toward low memory SP Current stack frame BP stack Caller’s growth stack frame Pin Connections AD15 – AD0: Address/Data bus lines. These are multiplexed lines. Line carries address when ALE =1 Line carries data when ALE =0 AD19/S6 – A13/S3: Address/Status bus bits are multiplexed to provide address signals A19-A16 and status bits S6-S3. S6 – always remains 0 S5 – indicates the condition of the interrupt flag S4 and S3 – Indicate the segment being accessed during current bus cycle. 35 RD: When this read signal pin is at logic 0, the data bus is receptive to data from memory or I/O devices. READY: This pin is used to enforce a waiting state. READY pin at 0 – the microprocessor goes into idle state. READY pin at 1 – the microprocessor does normal operation. 36 INTR: Interrupt request pin is used to request a hardware interrupt. If INTR is held at high when IF =1, the processor goes into the interrupt acknowledgement cycle. INTA becomes active when interrupt is being serviced. TEST: Test pin is an input that is tested by the WAIT instruction. If the test pin is at logic 0 the WAIT instruction functions as NOP. If test is a logic 1, the WAIT instruction wait for TEST to become logic 0. Commonly used with 8087 numeric coprocessor connections. 37 NMI: Non-maskable interrupt input is similar to INTR expect that the NMI interrupt does not check IF or priority. Use Interrupt Vector 2. RESET: If this reset pin is held high for 4 clock cycles the microprocessor resets. When 8086 or 8088 is reset it begins execution at memory location FFFF0H and clears the IF. CLK: 38 The clock pin is used to connect a clock generator Vcc: The power supply. +5V should be connected to this pin. GND: The ground connection for the microprocessor .
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