Ez8 CPU User Manual

Z8® Microcontrollers

Z8 LXM CPU Core

User Manual

UM018304-0707

Warning: DO NOT USE IN LIFE SUPPORT

LIFE SUPPORT POLICY ZILOG'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION.

As used herein Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness.

Document Disclaimer ©2007 by Zilog, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZILOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZILOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this document has been verified according to the general principles of electrical and mechanical engineering. Z8, Z8 Encore!, Z8 Encore! XP, Z8 Encore! MC, Crimzon, eZ80, and ZNEO are trademarks or registered trademarks of Zilog, Inc. All other product or service names are the property of their respective owners.

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Revision History

Each instance in Revision History reflects a change to this document from its previous revision. For more detail, refer to the corresponding pages or appropriate links given in the table below.

Revision Date Level Description Page No July 2007 04 Implemented Style Guide and updated disclaimer All section. August 2006 03 TM symbol removed from all instances with the All LXM core. November 2005 02 Updated the document, revision number, and xiv, 7, date. 25, 142. August 2005 01 Initial release. All

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Table of Contents

Introduction ...... viii About This Manual ...... viii Intended Audience ...... viii Manual Organization ...... viii Manual Conventions ...... ix Safeguards ...... x Architectural Overview ...... 1 Processor Description ...... 1 Fetch Unit ...... 2 Execution Unit ...... 2 Instruction Cycle Time ...... 2 Program Counter ...... 3 Z8 LXM CPU Control Registers ...... 3 Stack Pointer Register ...... 4 User Data Register ...... 5 Register Pointer ...... 5 Flags Register ...... 6 Interrupt Mask Register ...... 8 Interrupt Request Register ...... 8 Interrupt Priority Register ...... 9 Port 0 Mode Register ...... 10 Port 3 Mode Register ...... 11 Port 2 Mode Register ...... 12 Program/Constant Memory Page Register ...... 12 Address Space ...... 14 Register File ...... 14 Register File Maps ...... 15 Setting the Active Bank and Working Register Group ...... 18 16-Bit Register Pairs ...... 19 Byte Ordering ...... 20 Bit Addressing ...... 20 CPU Control Registers ...... 20 Stack ...... 21 Program/Constant Memory ...... 22 Addressing Modes ...... 24 Register Addressing ...... 24 Register Addressing Using 4-Bit Addresses ...... 24

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Register Addressing Using 8-Bit Addresses ...... 25 Escaped Mode Addressing ...... 26 Indirect Register Addressing ...... 27 Indexed Addressing ...... 29 Direct Addressing ...... 30 Relative Addressing ...... 31 Immediate Data Addressing ...... 32 Interrupts ...... 34 Interrupt Enable and Disable ...... 34 Interrupt Priority ...... 34 Vectored Interrupt Processing ...... 34 Interrupt Latency ...... 36 Nesting of Vectored Interrupts ...... 37 Generating Vectored Interrupts from Software ...... 37 Polled Interrupt Processing ...... 37 Processor Flags ...... 39 Carry Flag ...... 40 Zero Flag ...... 40 Sign Flag ...... 40 Overflow Flag ...... 40 Decimal Adjust Flag ...... 41 Half Carry Flag ...... 41 Condition Codes ...... 41 Z8 LXM CPU Instruction Set Summary ...... 43 Assembly Language Source Program Example ...... 43 Operand Ordering ...... 44 Z8 LXM CPU Instruction Notation ...... 44 Z8 LXM CPU Instruction Classes ...... 47 Z8 LXM CPU Instruction Summary ...... 51 Z8 LXM CPU Instruction Set Description...... 57 ADC ...... 58 ADD ...... 60 AND ...... 62 CALL ...... 65 CCF ...... 67 CLR ...... 68 COM ...... 69 CP ...... 71 DA ...... 73

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DEC ...... 75 DECW ...... 76 DI ...... 78 DJNZ ...... 79 EI ...... 81 HALT ...... 82 INC ...... 83 INCW ...... 85 IRET ...... 87 JP ...... 88 JP cc ...... 89 JR ...... 91 JR cc ...... 92 LD ...... 94 LDC ...... 97 LDCI ...... 99 LDX ...... 101 LDXI ...... 102 NOP ...... 104 OR ...... 105 POP ...... 107 PUSH ...... 109 RCF ...... 111 RET ...... 112 RL ...... 113 RLC ...... 115 RR ...... 117 RRC ...... 119 SBC ...... 121 SCF ...... 123 SRA ...... 124 SRP ...... 126 STOP ...... 127 SUB ...... 128 SWAP ...... 130 TCM ...... 132 TM ...... 134 WDH ...... 136 WDT ...... 137 XOR ...... 138

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Opcode Map ...... 140 Instructions Sorted By Opcode ...... 143 Index ...... 155 Customer Support ...... 160

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Introduction

This user manual describes the architecture and instruction set of the Zilog’s Z8® LXM CPU.

About This Manual

Zilog® recommends you to read and understand everything in this manual before setting up and using the product. This manual is designed to be used as a reference guide to important data.

Intended Audience

This document is written for Zilog customers who are experienced at working with micro- processors or in writing assembly code or compilers.

Manual Organization

This User Manual is divided into the following sections; each section details a specific topic about the product.

Architectural Overview This chapter presents an overview of the Z8 LXM CPU’s features and benefits, and a description of its architecture.

Address Space This chapter describes the two address spaces accessible by the Z8 LXM CPU—the register file and program/constant memory.

Addressing Modes This chapter details the Z8 LXM CPU’s five addressing modes, register, indirect register, indexed, direct, relative, and immediate.

Interrupts This chapter describes Z8 LXM CPU operation in response to interrupt requests from either internal peripherals or external devices.

UM018304-0707 Introduction Z8 LXM CPU Core User Manual

Z8 LXM CPU Instruction Set Summary Defines symbolic notation and lists instructions by functional group and mnemonic.

Z8 LXM CPU Instruction Set Description Describes each assembly language instruction in detail, including assembly language syntax and object code format for each valid opcode.

Opcode Map Presents a one-page map of all valid opcodes with operand format.

Instructions Sorted By Opcode Provides an easy reference for locating instructions by their operational codes.

Manual Conventions

The following assumptions and conventions are adopted to provide clarity and ease of use:

Courier Typeface Commands, code lines and fragments, bits, equations, hexadecimal addresses, and various executable items are distinguished from general text by the use of the Courier typeface. Where the use of the font is not indicated, as in the Index, the name of the entity is presented in upper case. • Example: FLAGS[1] is F2, User Flag 2.

Hexadecimal Values Hexadecimal values are designated by lowercase h and appear in the Courier typeface. • Example: R1 is set to F8h.

Bit Numbering Bits of a binary value in text are numbered right to left, from 0 to n–1 where n indicates the total number of bits. For example, the 8 bits of a register are numbered from 0 to 7, where bit 0 is the least significant bit and bit 7 is the most significant bit.

Brackets and Bit Ranges The square brackets, [ ], indicate a register or bus. A field of bits within a register is designated as: Register[n:n]. • Example: ADDR[15:0] refers to bits 15 through bit 0 of the Address. • Example: For register R1[7:0], R1 is an 8-bit register, R1[7] is the most significant bit, and R1[0] is the least significant bit.

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Braces The curly braces, { }, indicate a single register or bus created by concatenating some combination of smaller registers, buses, or individual bits. • Example: The 12-bit register address {0h, RP[7:4], R1[3:0]} is composed of a 4-bit hexadecimal value (0h) and two 4-bit register values taken from the Register Pointer (RP) and working register R1. 0h is the most significant nibble (4-bit value) of the 12-bit register, and R1[3:0] is the least significant nibble of the 12-bit register.

Use of the Words Set, Reset, and Clear The word set means that a bit contains or is written with a 1. The words clear and reset mean that a bit or value contains or is written with a 0.

Use of the Terms LSB, MSB, lsb, and msb In this document, the terms LSB and MSB, when appearing in upper case, mean least significant byte and most significant byte, respectively. The lowercase forms, lsb and msb, mean least significant bit and most significant bit, respectively.

Use of Initial Uppercase Letters Initial uppercase letters designate settings and conditions in general text. • Example 1: Stop Mode Recovery. • Example 2: The receiver forces the SCL line to Low.

Use of all Uppercase Letters The use of all uppercase letters designates the names of states and commands. • Example 1: The bus is considered busy after the START condition. • Example 2: The CPU enters STOP mode.

Safeguards

It is important that you understand the following safety terms, which are defined here. Caution: Indicates a procedure or file becomes corrupted if you do not follow the directions.

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Architectural Overview

The Z8 LXM CPU is an enhanced version of the Z8 CPU, with the following features: • Up to 128 pages of program/constant memory, 64 KB per page. • Up to 4 KB of register file address space, to access CPU control, peripheral control, and general-purpose registers. • Direct register-to-register architecture. Registers serve as multiple accumulators to speed execution and reduce program memory requirements. • Code compatible with other Z8 CPUs. The only change in assembly code is that the LDE and LDEI instructions are replaced by LDX and LDXI, which are used to linearly address the expanded register file space. • Software stack, which allows much greater depth in subroutine calls and interrupt nesting than a hardware stack. • Pipelined instruction fetch and execution.

Processor Description

The Z8 LXM CPU core consists of a Program Counter (PC), instruction fetch unit, execution unit, and CPU control registers. Figure 1 illustrates the Z8 LXM CPU architecture.

Program Fetch Unit Counter Execution Unit

CPU Control Registers

Program/Constant Memory Register File

Figure 1. Z8 LXM CPU Block Diagram

For detailed information on Program/constant Memory and register file spaces, see Address Space on page 14.

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Fetch Unit The Fetch Unit fetches the program instruction stream from Page 0 of Program/Constant memory. The Fetch Unit performs a partial decoding of the opcode to determine the number of bytes to fetch for the operation. The fetch unit operation sequence is given below: 1. Fetch the opcode. 2. Determine the operand size (number of bytes). 3. Fetch the operands. 4. Send the opcode and operands to the Execution Unit for processing.

Execution Unit After the initial operation decode by the Fetch Unit, the Execution Unit takes control and completes the instruction. The execution unit controls read and write operations in the register file and program/constant memory. The execution unit also handles program flow operations, such as jumps, calls, and interrupt requests.

Instruction Cycle Time Z8 LXM CPU devices have an on-chip crystal oscillator frequency that is divided by two to generate the CPU clock. The instruction cycle times documented in this manual are expressed in CPU clock cycles. The fetch cycle time for an instruction is the number of CPU cycles required to fetch the bytes used by the instruction. The execute cycles time is the number of additional cycles that are needed to complete the operation. The CPU starts to fetch the next instruction 0-3 cycles before the current instruction finishes executing. This is called pipelining. Therefore, the actual time required to fetch and execute an instruction is: Fetchcycle+ Executecycle∠ PipelineCycle

Where pipeline cycles is either 3 or the previous instruction’s execute cycle time, whichever is smaller. There are 0 pipeline cycles following a Reset or vectored interrupt, or following a DJNZ when the jump is taken.

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Program Counter The PC is a 16-bit counter that monitors the address of the current Program memory address and calculates the next program memory address. The PC increments automatically according to the number of bytes fetched by the Fetch Unit. The 16-bit adder increments and handles PC jumps for relative addressing. At system reset, the PC value is initialized to 000Ch in Program memory. This address must contain the first program instruction to be executed.

Z8 LXM CPU Control Registers The Z8 LXM CPU register file is organized in sixteen 256-byte banks. The upper 16 bytes of Bank 0 are reserved to control the Z8 LXM CPU and standard peripherals. For more information, see Address Space on page 14. The Z8 LXM CPU control registers are always located at addresses F0h to FFh as listed in Table 1. Any 4-bit or 8-bit address that falls in this range is directed to the Bank 0 control registers, regardless of the current register bank setting. The LDX and LDXI instructions access the CPU control registers using linear 12-bit addresses 0F0h to 0FFh. Note: Registers marked as Reserved in Table 1 are implemented in some Z8 LXM CPU devices. X indicates an undefined digit, or a digit that is defined differently in different devices. For more information on Reserved registers and bits, refer to device specific product specification for your device.

Table 1. Z8 LXM CPU Control Registers

8-Bit Register Diagram Address Mnemonic Register Description Reset Value Page FFh SPL Stack Pointer XXh 4 FEh USER User data register XXh 5 FDh RP Register Pointer 00h 5 FCh FLAGS Flags 00h 6 FBh IMR Interrupt Mask 0XXX_XXXXb 8 FAh IRQ Interrupt Request 00h 8 F9h IPR Interrupt Priority XXh 9 F8h P01M Port 0, 1 Mode 0100_0001b 10 F7h P3M Port 3 Mode XXXX_XXX0b 11 F6h P2M Port 2 Mode FFh 12 F5h — Reserved — —

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Table 1. Z8 LXM CPU Control Registers (Continued)

8-Bit Register Diagram Address Mnemonic Register Description Reset Value Page F4h — Reserved — — F3h — Reserved — — F2h — Reserved — — F1h — Reserved — — F0h PMPR Program Memory Page 0XXX_XXX0b 12

Stack Pointer Register The Stack Pointer register describes in Table 2, contains an 8-bit value that points to the top of the stack in Bank 0 of the register file. The stack grows downward, its top is the lowest address of its contents. For more information on stack operation, see Stack on page 21. The stack pointer value is undefined at reset, so programs must initialize it before performing any operation that affects the stack (EI, PUSH, POP, CALL, RET, IRET). The address range for stack data is 04h to EFh. The programmer must ensure that the stack does not overwrite other data as it grows downward through Bank 0. The initial stack pointer address is always decremented before a stack write, hence if the stack pointer is initialized to D0h, for example, the first stack address used is CFh.

Table 2. Stack Pointer Register (SPL)

Bit 7 6 5 4 3 2 1 0 Field Stack Pointer Reset XXXXXXXX R/W R/W R/W R/W R/W R/W R/W R/W R/W Address Bank 0: FFh

Bit Position Value Description [7:0] 00h–FFh Stack Pointer

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User Data Register Programs can use Bank 0 register FEh (Table 3) as a user data register. This register is bank independent, so it is accessed with 4- or 8-bit addressing at any time without changing register banks. For more information, see Address Space on page 14.

Table 3. User Data Register (USER)

Bit 7 6 5 4 3 2 1 0 Field User Data Reset XXXXXXXX R/W R/W R/W R/W R/W R/W R/W R/W R/W Address Bank 0: FEh

Bit Position Value Description [7:0] 00h–FFh User Data

Register Pointer The Register Pointer (Table 4) contains address information for the current working register group and the register file bank. For details on using the register pointer, see Setting the Active Bank and Working Register Group on page 18.

Table 4. Register Pointer Register (RP)

Bit 7 6 5 4 3 2 1 0 Field Working Register Pointer Register Bank Pointer Reset 00000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W Address Bank 0: FDh

Bit Position Value Description [7:4] Working Register Pointer. 0h–Fh Determines which 16-byte working group is addressed. [3:0] Register Bank Pointer. 0h–Fh Determines which register bank is active.

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Flags Register The Flags register (Table 5) contains the status information regarding the most recent arithmetic, logical, bit manipulation, or rotate and shift operation. Flags are used in arithmetic calculations or for conditional jump tests. For more information, see Processor Flags on page 39.

Table 5. Flags Register (FLAGS)

Bit 7 6 5 4 3 2 1 0 Field C Z S O D H F2 F1 Reset 00000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W Address Bank 0: FCh

UM018304-0707 Architectural Overview Z8 LXM CPU Core User Manual

Bit Position Value Description [7] Carry Flag (C)—Set when an arithmetic operation generates a carry out of or a borrow into the msb of the result. Also used in rotate and shift instructions. 0 Flag Clear. 1 Flag Set. [6] Zero Flag (Z)—Set when the result of an arithmetic operation is 0. 0 Flag Clear. 1 Flag Set. [5] Sign Flag (S)—Stores a copy of the result msb after an arithmetic, logical, rotate, or shift instruction. 0 Flag Clear. 1 Flag Set. [4] Overflow Flag (O)—Set when the result of an arithmetic operation is greater than 127. 0 Flag Clear. 1 Flag Set. [3] Decimal Adjust Flag (D)—Used for binary-coded decimal (BCD) arithmetic. 0 Flag Clear. 1 Flag Set. [2] Half Carry Flag (H) —Set when a carry out of or borrow into bit 3 of an arithmetic operation occurs. 0 Flag Clear. 1 Flag Set. [1] User Flag 2 (F2)—Available to software for use as a general-purpose bit. 0 Bit Clear. 1 Bit Set. [0] User Flag 1 (F1)—Available to software for use as a general-purpose bit. 0 Bit Clear. 1 Bit Set.

UM018304-0707 Architectural Overview Z8 LXM CPU Core User Manual

Interrupt Mask Register The Interrupt Mask register (Table 6) is used to enable or disable interrupt requests either individually or globally.

Table 6. Interrupt Mask Register (IMR)

Bit 7 6 5 4 3 2 1 0 Master Interrupt Reserved IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 IRQ0 Field Enable Enable Enable Enable Enable Enable Enable Reset 0 XXXXXXX R/W R/W — R/W R/W R/W R/W R/W R/W Address Bank 0: FBh

Bit Position Value Description [7] Master Interrupt Enable—Use only the DI and EI instructions to alter this bit. Always disable interrupts (DI instruction) before writing this register. 0 All interrupts are disabled. 1 Interrupts are enabled/disabled individually in bits [5:0]. [6] 0 Reserved—Reads are undefined; writes must be 0. [5:0] IRQ5–IRQ0 Enable Bits—Each bit enables or disables the corresponding IRQ. 0 Interrupt disabled. 1 Interrupt enabled.

Interrupt Request Register The Interrupt Request register (Table 7) is used to read or clear the status of interrupt requests. It is also used to select the edge triggering configuration for interrupt input pins.

Table 7. Interrupt Request Register (IRQ)

Bit 7 6 5 4 3 2 1 0 Field Interrupt Edge IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 IRQ0 Reset 00000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W Address Bank 0: FAh

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Bit Position Value Description [7:6] — Interrupt Edge—Configure input pins to generate interrupts on rising or falling edge. (For values and affected pins, refer to the product specification.) [5:0] IRQ5–IRQ0 Status—Each bit indicates the status of the corresponding IRQ. Read: 0 Interrupt did not occur. 1 Interrupt occurred. Write: 0 Clear Interrupt. 1 Set Interrupt.

Interrupt Priority Register The Interrupt Priority register (Table 8) defines which interrupts hold the highest priority. Interrupts are divided into three groups of two—Group A, Group B, and Group C. Priority is set for the two registers within each group and for the three groups overall. The assignment of functions to IRQs is device specific. For more details, refer to Product Specification.

Table 8. Interrupt Priority Register (IPR)

Bit 7 6 5 4 3 2 1 0 Reserved Group A Group Priority Group B Group C Group Priority Field Priority [2:1] Priority Priority [0] Reset XXXXXXX X R/W —WWWWW Address Bank 0: F9h

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Bit Position Value Description [7:6] — Reserved—Reads are undefined; writes must be 00b. [5] Group A Priority (IRQ3, IRQ5). 0 IRQ5 > IRQ3 1 IRQ3 > IRQ5 {[4:3], [0]} Group Priority. 000 Reserved 001 C > A > B 010 A > B > C 011 A > C > B 100 B > C > A 101 C > B > A 110 B > A > C 111 Reserved [2] Group B Priority (IRQ0, IRQ2). 0 IRQ2 > IRQ0 1 IRQ0 > IRQ2 [1] Group C Priority (IRQ1, IRQ4). 0 IRQ1 > IRQ4 1 IRQ4 > IRQ1

Port 0 Mode Register The Port 0 Mode register (Table 9) determines the I/O direction of the Port 0 nibbles. Note: Some devices do not implement all Port 0 pins.

Table 9. Port 0 Mode Register (P01M)

Bit 7 6 5 4 3 2 1 0 Field Reserved P07:P04 Mode Reserved P03:P00 Mode Reset X 1 XXXXX 1 R/W — W ————— W Address Bank 0: F8h

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Bit Position Value Description [7] — Reserved—Reads are undefined; for compatibility write 0b. [6] 0 P07:P04 are Outputs. 1 P07:P04 are Inputs. [5:1] — Reserved—Reads are undefined; for compatibility write 00110b. [0] 0 P03:P00 are Outputs. 1 P03:P00 are Inputs.

Port 3 Mode Register The Port 3 Mode register (Table 10) is used to configure Port 3 input functions. Also, bit 0 determines whether Port 2 pins are open drain or push/pull. The definition of other P3M bits is device specific. For more details, refer to product specification.

Table 10. Port 3 Mode Register (P3M)

Bit 7 6 5 4 3 2 1 0 Field Device Specific Port 2 Open-Drain Reset XXXXXXX 0 R/W ——————— W Address Bank 0: F7h

Bit Position Value Description [7:0] — Device Specific—For details, refer to the product specification. [0] 0 Port 2 open-drain. 1 Port 2 push/pull.

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Port 2 Mode Register The Port 2 Mode Register (Table 11) determines the I/O direction of each bit on Port 2. Bit 0 of the Port 3 Mode Register determines whether the output drive is push/pull or open- drain.

Table 11. Port 2 Mode Register (P2M)

Bit 7 6 5 4 3 2 1 0 P27 I/O P26 I/O P25 I/O P24 I/O P23 I/O P22 I/O P21 I/O P20 I/O Field Definition Definition Definition Definition Definition Definition Definition Definition Reset 11111111 R/W R/W R/W R/W R/W R/W R/W R/W R/W Address Bank 0: F6h

Bit Position Value Description [7:0] P27–P20 Definitions—Each bit defines the direction of the corresponding Port 2 pin. 0 Defines pin as output. 1 Defines pin as input.

Program/Constant Memory Page Register The Program/Constant Memory Page register (Table 12) contains the current Program/ Constant memory page number and page toggle enable bit. For details on using this register, see Program/Constant Memory on page 22.

Table 12. Program Memory Paging Register (PMPR)

Bit 7 6 5 4 3 2 1 0 Field Page Toggle Enable Reserved Page Register Reset 0 XXXXXX 0 R/W R/W —————— R/W Address Bank 0: F0h

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Bit Position Value Description [7] Page Toggle Enable. 0 PMPR[0] changes only when written by software. 1 The CPU toggles PMPR[0] when LDCI increments past FFFFh. [6:1] — Reserved—Reads are undefined; for compatibility write 000000b. [0] Page Register. 0 LDC, LDCI instructions access Page 0. 1 LDC, LDCI instructions access Page 1.

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Address Space

The Z8 LXM CPU accesses two distinct address spaces: • The register file space contains addresses for the general-purpose (RAM) registers and control registers for the Z8 LXM CPU, peripherals, and I/O ports. • The Program/constant Memory space contains addresses for all memory locations that contains executable code or constant data.

The Z8 LXM CPU supports a maximum of 4096 addresses in the register file, organized in sixteen 256-register banks numbered 0h to Fh. Most instructions support 8-bit addresses, which accesses any register in the currently active bank. Only one bank is active at a time; the active bank is set by control register bits RP[3:0]. The active bank is further divided into 16 working register groups, 0h to Fh, with 16 registers per group. To reduce program size, most instructions support short 4-bit addresses that access registers in the active working register group. The active working register group is set by control register bits RP[7:4]. For more information on using the RP register, see Setting the Active Bank and Working Register Group on page 18. Most registers are general-purpose registers, which are used by various instructions as accumulators, address pointers, address indexes, stack space, or ordinary RAM space. Other register addresses are reserved for control functions or future expansion. A typical Z8 LXM CPU product implements the following register banks: • Bank 0 is always implemented. In Bank 0, addresses F0h to FFh are reserved for standard control registers, addresses 00h to 03h are reserved for port data registers, and addresses 04h-EFh are available as general-purpose registers. Bank 0 always contains the stack, which starts at address CFh and grows downward. • Zero or more extended banks (Bank 1, 2, 3, and so on), containing additional general purpose registers. • One or more peripheral control banks, (Banks D, F, and perhaps others), reserved for additional control registers. Control banks are located in the high end of the bank numbering. Some 8-bit addresses (and the equivalent 4-bit addresses) are bank independent. Addresses F0h to FFh always access the Bank 0 control registers regardless of the RP[3:0] setting. Addresses 00h to 03h always access the Bank 0 port data registers if RP[3:0] is

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set to a general-purpose register bank. Unimplemented addresses in a peripheral control bank (for example, Banks D and F) always access Bank 0. Also, 8-bit addresses in the range E0h to EFh are subject to redirection to the current working register group. For more details, see Escaped Mode Addressing on page 26. Special LDX and LDXI instructions are provided to load registers in the active bank to or from any other bank without changing the RP register. These instructions use 12-bit addresses that access the 16 possible register banks as a linear space of 4096 addresses. A linear address always accesses the addressed location, regardless of any redirection that affects the corresponding 8-bit or 4-bit address.

Register File Maps Figure 2 on page 16 illustrates a Z8 LXM CPU device register map for 8-bit addressing, showing the banks implemented on an example device. Figure 3 on page 17 illustrates how working registers are accessed in the active bank. Figure 4 on page 18 displays how this example address space is accessed using 12-bit linear addresses (LDX and LDXI instructions only). This example device does not implement Banks 4h–Ch or Eh. Also, a particular device does not implement all I/O ports or control registers. Reading from an unimplemented address, or reserved or write-only bits of a control register, returns an undefined value. Writing to such an address or bit has no effect. Control registers must only be read or written as appropriate for their defined functions. For details on your device’s implemented register banks, control registers, and ports, refer to device-specific product specification.

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Banks 1–3 CPU Control F0h–FFh CPU Control Bank 0 F0h–FFh Bank D Bank F CPU Control CPU Control CPU Control CPU Control F0h–FFh F0h–FFh F0h–FFh F0h–FFh Escaped Mode Escaped Mode E0h–EFh E0h–EFh Typ. ISR Regs* D0h–DFh Typical Stack (Bank 0 Only) Bank 0 Bank 0 General General General Purpose Purpose Purpose General Registers Registers Registers Purpose 04h–EFh 10h–EFh 10h–EFh Registers 04h–EFh

Peripheral Peripheral Control Control Ports 00h–03h Ports 00h–03h 00h–0Fh 00h–0Fh

= Bank-Independent Address (Always Accesses Bank 0) = 8-Bit Escaped Mode Address (Redirects to Current Working Register Group) * Compiler’s default interrupt service routine working registers. Not to Scale

Figure 2. Register File 8-Bit Banked Address Map (Example Device)

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Group Fh R15 R14 R13 Active Register R12 Bank R11 Group R10 Fh F0h–FFh R9 R8 Control Eh E0h–EFh R7 Registers R6 F0h–FFh Dh D0h–DFh R5 (See Page 3) R4 Ch C0h–CFh R3 Group 7h R2 Bh B0h–BFh R15 R1 R14 R0 Ah A0h–AFh R13 9h 90h–9Fh R12 R11 8h 80h–8Fh R10 R9 7h 70h–7Fh R8 General R7 Purpose 6h 60h–6Fh R6 Registers R5 5h 50h–5Fh R4 R3 4h 40h–4Fh R2 Group 0h 3h 30h–3Fh R1 R15 R0 R14 2h 20h–2Fh R13 R12 1h 10h–1Fh R11 General 0h 00h–0Fh R10 Purpose R9 Registers R8 R7 R6 R5 R4 00h = 8-bit Address (In Bank) R3 0h = Working Register Group Number (in Bank) R2 Port 0–3 R0 = 4-bit Register Number (In Working Register Group) R1 Data = Bank-Independent Address R0 = 8-Bit Escaped Mode Address (Redirects to Current Working Register Group) Figure 3. Working Register Group Examples (General-Purpose Bank)

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Banks 1–3

Bank 0 Bank D Bank F CPU Control 0F0h–0FFh

Typical Stack Below 0D0h General Purpose Registers 100h–3FFh Reserved Reserved General D10h–DFFh F10h–FFFh Purpose Registers 004h–0EFh

Peripheral Peripheral Control Control Ports 000h–003h D00h–D0Fh F00h–F0Fh

Not to Scale

Figure 4. Register File LDX, LDXI Linear 12-Bit Address Map (Example Device)

Setting the Active Bank and Working Register Group The Register Pointer (RP) register controls the currently active register bank and working register group. Writing RP[3:0] sets the active register bank used for 8-bit addressing. Writing RP[7:4] sets the active working register group used for 4-bit addressing. The SRP instruction is used to write the RP register directly in any context. If the register file is viewed as a 12-bit linear address space, an 8-bit address is resolved as {RP[3:0], 8-bit address}, and a 4-bit address is resolved as {RP[3:0], RP[7:4], 4-bit address}. However, 8-bit and 4-bit addresses are subject to redirection if they fall in a bank-independent range. 8-bit addresses in the range E0h–EFh are also subject to escaped-mode redirection.

UM018304-0707 Address Space Z8 LXM CPU Core User Manual

Figure 5 illustrates the resolution of a 4-bit working register address.

Bit Register Pointer Bit 7 0

0 1 1 1 0 0 1 1 Working Group Page INC R6

0 1 1 0 1 1 1 0 Working Register 4-bit Address

0 0 1 1 0 1 1 1 0 1 1 0 Bit Bit 11 0 Full 12-bit Register Address (376h)

Figure 5. Working Register Addressing Example

16-Bit Register Pairs Some instructions access register data as a 16-bit word, or register pair. In this case, the MSB of the data is stored in the even numbered register, while the LSB is stored in the next higher odd numbered register (see Figure 6). Address the register pair using the address of the MSB.

MSB LSB

Rn Rn+1

n = Even Address

Figure 6. 16-Bit Register Pair Addressing

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Byte Ordering For multibyte data, the Z8 LXM CPU stores the MSB in the lowest memory address. For example, the value 1 is stored as a 2-byte (16-bit) number in register pair 122h and 123h. The value is stored as 0001h. The MSB (00h) is stored in the lowest memory address at 122h. The LSB (01h) is stored in the higher memory address at 123h. This ordering of multibyte data is often referred to as big endian.

Bit Addressing Some Z8 LXM CPU instructions allow access to individual bits within registers. Figure 7 illustrates how the instruction AND R15, MASK clears an individual bit.

Bit Bit 7 0

0 1 1 1 0 0 0 0R15

1 1 0 1 1 1 1 1 MASK = DFh

AND R15, DFh ; Clear Bit 5 of Working Register 15

0 1 0 1 0 0 0 0R15

Figure 7. Bit Addressing Example

CPU Control Registers The Z8 LXM CPU control registers are located in Bank 0 addresses F0h to FFh. As mentioned before, 8-bit addresses F0h to FFh (or the equivalent 4-bit addresses) always access Bank 0. The LDX and LDXI instructions access the Bank 0 control registers with 12-bit addresses 0F0h to 0FFh. For information on CPU registers, see Z8 LXM CPU Control Registers on page 3.

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Stack

All stack operations occur in the general-purpose registers in Bank 0. Bank 0 control register FFh is the 8-bit Stack Pointer register (SPL) used for all stack operations. The Stack Pointer register holds the current stack address within Bank 0. Programs must initialize the stack pointer before performing any operation that might affect the stack (EI, PUSH, POP, CALL, RET, IRET). The stack grows downward below the initial Stack Pointer address. The Stack Pointer (SP) decrements prior to a PUSH operation and increments after a POP operation. The SP always points to the data stored at the ‘top’ of the stack (the lowest address in the stack). The stack is a return stack for interrupts and CALL instructions. It is also used as a data stack. During a CALL instruction, the contents of the PC are saved in the stack. The PC is restored during execution of a Return (RET). Interrupts save the contents of the PC and the Flags Register on the stack. The Interrupt Return (IRET) instruction restores them. Figure 8 illustrates the contents of the Stack and the location of the Stack Pointer following CALL and Interrupt.

PC[7:0] PC[7:0] PC[15:8] "Top" of Stack PC[15:8] "Top" of Stack Flags

Stack Contents Stack Contents After a After an Call Instruction Interrupt

Figure 8. Stack Operations

Caution: An overflow or underflow occurs when the stack address is incremented or decremented beyond the available address space. You must prevent this occurrence, otherwise, unpredictable operation results. You must also ensure enough unused space is available below the initial stack pointer address so that no stack operation overwrites other data. The required stack space depends on the program design.

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Program/Constant Memory

Microcontrollers based on the Z8 LXM CPU implements one or more 64 KB pages of memory dedicated to program and immediate data, as well as data constants and tables accessed by the LDC and LDCI instructions. The term constant here reflects the read-only implementation of Program/Constant memory. If a Z8 LXM CPU-based device implements Program/Constant memory as read/write memory, LDC and LDCI are used for both read and write operation in this space. Only Page 0 of Program/Constant memory contains program instructions and operands (object code). If the 16-bit PC runs over the Page 0 limit, it rolls over and execution continues in Page 0 at address 0000h. Page 0 also contains constants and data tables accessed using the LDC and LDCI instructions. If any additional pages are implemented, Pages 1 and higher contains only constants and data tables, and therefore is accessed only by LDC or LDCI. To access Page 1 or higher using LDC or LDCI, first write the page number (for example, 000_0001b) to bits [6:0] of the Program Memory Page register (PMPR). To access Page 0 again, write 000_0000b to PMPR[6:0]. Note: A Z8 LXM CPU device implements only the PMPR bits needed to select the implemented pages. The value of unimplemented PMPR[6:0] bits is undefined when read. When written, unimplemented PMPR bits should be cleared to 0 to ensure compatibility with possible future devices.

If the Program/Constant memory is viewed as a linear address space, a 16-bit LDC or LDCI address is resolved as {PMPR[6:0], 16-bit address}. In this model, a program counter address is always resolved as {0, PC[15:0]}. Some devices do not implement all addresses in the implemented pages. Attempts to read or execute from unimplemented addresses return FFh. Attempts to write to unimplemented or read-only addresses produce no effect. To determine the amount of Pro- gram/Constant memory implemented, and whether it is read-only or read-write memory, refer to device-specific product specification for your product. By default, if the LDCI count register increments past FFFFh, it resets to 0000h and the next LDCI access remains on the current page. Setting bit PMPR[7]=1 enables the Page Toggle function. If PMPR[7]=1 and the LDCI counter increments past FFFFh, the value in PMPR[6:0] is incremented as well, so the next LDCI access addresses 0000h on the next Program/Constant memory page. If the last page implemented by the device is active and PMPR[7]=1, incrementing the LDCI count past FFFFh causes the next LDCI instruction to access 0000h on Page 0. At system reset, the implemented PMPR bits are cleared to 0b (Page 0 selected, toggle disabled). Unimplemented bits read back as 1s.

UM018304-0707 Address Space Z8 LXM CPU Core User Manual

Page 0 bytes 0000h to 000Bh are reserved for interrupt vectors IRQ0–IRQ5. On Reset, program execution begins at Page 0 address 000Ch. Figure 9 on page 23 illustrates the Program/Constant memory map for an example device.

Page 0 Page 1 {0, FFFFh} FFFFh {1, FFFFh} FFFFh

Program or Constants Constants Only

000Ch (Reset) IRQ 0–5 {0, 0000h} Vectors {1, 0000h} 0000h

0000h = 16-bit Address (In Page) {0, 0000h} = {PMPR[0], 16-bit address} (LDC, LDCI Only) Not to Scale

Figure 9. Program/Constant Memory Map (Example Device)

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Addressing Modes

The Z8 LXM CPU provides six basic addressing modes: • Register operands address a register or register pair to be used. • Indirect register operands address a register or register pair that points to the location to be used. • Indexed operands address a register and a value, X. The specified register’s contents are added to X to determine the location to be used. • Direct Address (DA) operands specify a location to jump to in program memory. • Relative Address (RA) operands provide a program memory offset to be added to the program counter. • Immediate Data (IM) operands supply the actual value to be used.

Register addresses can be 8, or 4 bits in length, depending on the instruction. Program memory addresses are 16 bits in length. Register pairs are used to designate 16-bit values, or 12- or 16-bit indirect addresses. Working register pairs use 4-bit addresses and must be specified as an even-numbered address in the range of R0, R2, ..., R14. Register pairs use 8-bit addresses and must be specified as an even-numbered address in the range of 0, 2, …, 254. In the following definitions of addressing modes, the term register implies a register, a register pair, a working register, or a working register pair, depending on the context. For details about the available Program/Constant and register file memory, refer to product specification that is specific to your Z8 LXM device.

Most instructions allow register file locations to be specified directly using 4- or 8-bit address operands.

Register Addressing Using 4-Bit Addresses Working registers or working register pairs can be accessed using 4-bit addresses supplied in the operands. A 4-bit destination or source operand specifies one of 16 possible addresses within the current working register group. In assembly language, the 16 working registers in the active group are named R0, R1, R2..., R15. For example, the

UM018304-0707 Addressing Modes Z8 LXM CPU Core User Manual

following assembly statement performs a logical OR of working registers R5 and R11 in the current working register group, and writes the result to R5. OR R5, R11 ;Object Code: 42 5B There are 16 working register groups in each register file bank. The active working register group is specified in register pointer bits RP[7:4]. The active bank is specified in RP[3:0]. The equivalent 12-bit linear address is {RP[3:0], RP[7:4], Address[4:0]}. Figure 10 illustrates 4-bit addressing of the register file.

Program Memory Register File

12-bit address is {RP[3:0], RP[7:4], dst[3:0]} Two 4-bit {dst[3:0], Destination Addresses src[3:0]} Register (dst, src)

One Operand Opcode Instruction (Example)

12-bit address is {RP[3:0], RP[7:4], src[3:0]} Source Register

Figure 10. Register Addressing Using 4-Bit Addresses

Register Addressing Using 8-Bit Addresses Registers or register pairs are accessed using 8-bit addresses supplied in the operands. For example, the following assembly statement increments register 42h in the current register file bank: INC 42h ;Object Code: 20 42 Any of the 256 registers on the current register file bank are accessed using 8-bit addressing. As mentioned before, the current bank is specified in register pointer bits RP[3:0]. For addresses 00h–DFh and F0h–FFh, the equivalent 12-bit linear address is {RP[3:0], Address[7:0]}. Addresses E0h–EFh invoke escaped mode. For more details, see Escaped Mode Addressing on page 26.

UM018304-0707 Addressing Modes Z8 LXM CPU Core User Manual

Figure 11 illustrates register addressing using 8-bit addresses. The destination and/or source address specified corresponds to a register in the register file.

Program Memory Register File

12-bit address is {RP[3:0], dst[7:0]} One 8-bit Address (dst) Destination (Excludes E0h–EFh) dst[7:0] Register

One Operand Opcode Instruction (Example)

Figure 11. Register Addressing Using 8-Bit Addresses (Non-Escaped)

Escaped Mode Addressing Escaped mode addressing is used to access a register in the currently active working register group using an 8-bit register address. This makes it easy in a working register context to use instructions that do not support working register operands directly. If an 8-bit address in the range E0h to EFh is specified in a source or destination operand, a register in the current working register group is used instead. For example, if the register operand ECh is specified, working register R12 (Ch) is addressed instead. Figure 12 on page 27 illustrates 8-bit addressing using escaped mode. Escaped mode only affects the register address specified in an 8-bit operand. For indirect addressing, the address pointed to by the specified register is used explicitly. For example, if working register R4 contains the address E5h, the operand @E4h accesses register E5h, not working register R5. To use 8-bit addressing to access registers E0h to EFh, either set the working group pointer, RP[7:4] to Eh, or use indirect addressing.

UM018304-0707 Addressing Modes Z8 LXM CPU Core User Manual

Program Memory Register File

12-bit address is {RP[3:0], RP[7:4], dst[3:0]} One 8-bit Address (dst) Destination (E0h–EFh) dst[7:0] Register

One Operand Opcode Instruction (Example)

Figure 12. Register Addressing Using 8-Bit Addresses (Escaped Mode)

Indirect Register Addressing

In Indirect register addressing, the register or register pair specified in the operand is not used directly. Instead, it contains the address of another register or register pair to be used for the operation. For example, the following assembly statement increments the value in the location specified in register 42h. Register 42h is not changed. INC @42h ;Object Code: 21 42 This operation is illustrated in Figure 13 on page 28. The following statement loads the contents of working register R11 into the Program/ Constant memory location pointed to by working register pair RR5. R11 and RR5 are both incremented after the operation. LDCI RR5, R11 ;Object Code: D2 5B The destination decoding for this operation is illustrated in Figure 14 on page 29. For most instructions, the specified register points to an 8-bit address in the current bank. For LDX and LDXI, the specified register pair points to a 12-bit register file address. For LDC and LDCI, the specified register pair points to a 16-bit address in the current Program/Constant memory page.

UM018304-0707 Addressing Modes Z8 LXM CPU Core User Manual

Program Memory Register File

Register contains 8-bit address (addr[7:0]) 12-bit address is One 8-bit {RP[3:0], dst[7:0]} Destination Address dst[7:0] Register (dst)

One Operand Opcode Instruction (Example) 12-bit address is {RP[3:0], addr[7:0]} {RP[3:0],

Value used in execution

Figure 13. Indirect Register Addressing to Register File

UM018304-0707 Addressing Modes Z8 LXM CPU Core User Manual

Program Memory Register File

Destination Register Pair Register LSB contains one 12-bit address is 16-bit address Two 4-bit {RP[3:0], RP[7:0], dst[3:0]} {dst[3:0], Destination {addr[15:8], addr[7:0]} Addresses src[3:0]} Register MSB (dst, src) (Source addressing is omitted for clarity.) One Operand Opcode Instruction (Example)

Program/Constant Memory 16-bit address is {addr[15:8], addr[7:0]}

Destination Used

Figure 14. Indirect Register Addressing to Program/Constant Memory

Indexed Addressing

An indexed address consists of an 8-bit base address operand offset by an 8-bit signed index contained in the source working register. Figure 15 on page 30 illustrates indexed addressing. For example, the following statement adds the contents of R11 to 42h to generate an effective address, and then loads R5 with the contents of that address. LD R5, 42h(R11) ;Object Code: C7 5B 42

UM018304-0707 Addressing Modes Z8 LXM CPU Core User Manual

Program Memory Register File

12-bit address is {RP[3:0], RP[7:4], dst[3:0]} Destination Address Register Two 4-bit {dst[3:0], Source Address src[3:0]} Register (dst, src)

Two Operand Opcode Instruction X (Example) + 8-bit value written to Desitnation Register Desitnation to

Value used 12-bit address is in execution {RP[3:0], Address + X}

Figure 15. Indexed Register Addressing

Direct Addressing

Figure 16 on page 31 illustrates the direct addressing mode. This instruction specifies the address of the next instruction to be executed. Only the Jump (JP and JP cc) and Call (CALL) instructions use direct addressing. The 16-bit direct address is written to the PC. For example, the following statement causes a jump to address 0123h in program memory: JP 0123h ;Object Code: 8D 01 23 The direct address for a JP or CALL instruction is also specified in a register pair. For example, the following statement causes a jump to the program memory address contained in register pair B2h: JP @B2h ;Object Code: 30 B2

UM018304-0707 Addressing Modes Z8 LXM CPU Core User Manual

Program Memory

DA[7:0] 16-bit Direct DA[15:0] written to Address Program Counter DA[15:8]

Two Operand Instruction Opcode (Example)

16-bit Program Memory address Next is DA[15:0] Opcode

Figure 16. Direct Addressing

Relative Addressing

Figure 17 on page 32 illustrates the relative addressing mode. In assembly language, the destination is usually specified by a label defined at the destination line in the source file. The assembler calculates the relative offset to use in object code. In object code, the instruction specifies a two’s complement signed displacement in the range of –128 to +127. This instruction, added to the contents of the PC, obtains the address of the next instruction to be executed. Prior to the addition operation, the PC contains the address of the instruction immediately following the current relative addressing instruction. The JR and DJNZ instructions are the only instructions that use this mode.

UM018304-0707 Addressing Modes Z8 LXM CPU Core User Manual

Program Memory

16-bit Program Next Opcode PC[15:0] Memory address if no Jump is PC[15:0] 8-bit Value d If Jump taken, –128 to +127 Displacement + PC[15:0] = PC[15:0] + d[7:0] One Operand Instruction Opcode (Example)

16-bit Program Next Opcode Memory address if Jump is PC[15:0] + d[7:0]

Figure 17. Relative Addressing

Immediate Data Addressing

Immediate data (IM) addressing is the only addressing mode that does not indicate a register or memory address as the operand. The operand value used by the instruction is the value supplied in the operand field itself, because an immediate operand is part of the instruction, it is always located in the Program Memory address space. Figure 18 on page 33 illustrates immediate data addressing. For example, the following instruction loads the immediate value, 51h, into register 42h. LD 42h, #51h ;Object code: E6 42 51

UM018304-0707 Addressing Modes Z8 LXM CPU Core User Manual

Program Memory Register File

8-bit data written Immediate to Destination Data

Destination dst Register Two Operand 12-bit address is {RP[3:0], dst[7:0]} Instruction Opcode (Example)

Figure 18. Immediate Data Addressing

UM018304-0707 Addressing Modes Z8 LXM CPU Core User Manual

Interrupts

Interrupt requests (IRQs) allow peripheral devices to suspend CPU operation and force the CPU to start an interrupt service routine (ISR). The ISR exchanges data, status information, or control information between the CPU and the interrupting peripheral. When the service routine finishes, the CPU returns to the previous operation. The Z8 LXM CPU supports both vectored- and polled-interrupt handling. Interrupt requests are generated from internal peripherals, external devices through the port pins, or software. The Interrupt Controller prioritizes and handles individual interrupt requests before passing them on to the Z8 LXM CPU. The interrupt sources and trigger conditions are device dependent. For more information on available interrupt sources (internal and external), triggering edge options, and exact programming details, refer to device-specific product specification for your product.

Interrupt Enable and Disable

Interrupts are globally enabled and disabled by executing the Enable Interrupts (EI) and Disable Interrupts (DI) instructions, respectively. These instructions affect the master interrupt enable, bit 7 in the Interrupt Mask Register (IMR), Bank 0 register FBh. For IMR details, see Table 6 on page 8. Use IMR[5:0] to enable or disable individual interrupts IRQ5–IRQ0. Always use the DI instruction to disable interrupts before writing to the IMR register.

Interrupt Priority

The Interrupt Controller prioritizes all interrupt requests according to the settings in the Interrupt Priority Register (IPR), Bank 0 register FCh. For more details on IPR, see Table 8 on page 9.

Vectored Interrupt Processing

Each Z8 LXM CPU interrupt is assigned its own vector. When an interrupt occurs, control passes to the ISR pointed to by the contents of the corresponding interrupt vector in Program memory. The sequence of events for a vectored interrupt is as follows: 1. Disable interrupts (clear IMR[7]). 2. Push the Low byte of the PC, PC[7:0], on the stack. 3. Push the High byte of the PC, PC[15:8], on the stack.

UM018304-0707 Interrupts Z8 LXM CPU Core User Manual

4. Push the Flags register on the stack. 5. Fetch the High byte of the interrupt vector. 6. Fetch the Low byte of the interrupt vector. 7. Branch to the ISR pointed to by the interrupt vector.

Figure 19 illustrates the effect of vectored interrupts on the SP and the contents of the stack. Figure 20 on page 36 provides an example of the Program memory during interrupt operation. In the example displayed in Figure 20 on page 36, the interrupt vector is located at address 0004h in Program memory. The 2-byte interrupt vector, stored at program memory addresses 0004h and 0005h, is loaded into the PC. Execution of the ISR begins at Program memory address 4567h, as is stored in the interrupt vector.

Stack Pointer and Stack Stack Pointer and Stack Before an Interrupt After an Interrupt

Stack Pointer "Top" of Stack Stack Pointer PC[7:0] PC[15:8] Flags[7:0]

Figure 19. Effects of an Interrupt on the Stack

UM018304-0707 Interrupts Z8 LXM CPU Core User Manual

Program Memory Address Program Memory

4567h Interrupt Service Routine Origin

Interrupt Vector 0005h Vector[7:0] = 67h Table Vector Selected by Interrupt Controller 0004h Vector[15:8] = 45h

Figure 20. Interrupt Vectoring in Program Memory Example

Interrupt Latency

Interrupt latency is the time required to service an enabled interrupt is variable, with a possible range of 26–48 CPU cycles between event detection and the beginning of the first service routine instruction fetch. This time comprises the following stages: 1. IRQ Assertion—For external interrupt sources, two CPU cycles are required after the external signal is asserted to synchronize flip flops and assert the IRQ signal to the CPU. For internal peripherals, the IRQ is asserted immediately on event detection. 2. IRQ Recognition—Up to 20 cycles are required for the CPU to complete the current instruction and recognize the IRQ. The maximum recognition time is the sum of Fetch and Execution cycles for the slowest instruction in the program. The worst case (20 cycles) is IRQ assertion at the start of a CALL instruction with an empty pipeline (for example, following a NOP). 3. PC Adjustment—10 cycles are required to abandon the opcode fetch in progress and adjust the PC. 4. Context Push—10 cycles are required to push the PC and flags onto the stack. 5. Vector Fetch—Finally, 6 cycles are required to fetch the interrupt vector.

UM018304-0707 Interrupts Z8 LXM CPU Core User Manual

Nesting of Vectored Interrupts

Vectored interrupt nesting allows higher priority requests to interrupt a lower priority request. To initiate vectored interrupt nesting, perform the following steps during the interrupt service routine: 1. Push the old IMR contents onto the stack. 2. Load the IMR with new masks to disable lower priority interrupts. 3. Execute an EI instruction to enable the interrupts. 4. Proceed with the ISR processing. 5. After processing is complete, execute a DI instruction to disable the interrupts. 6. Pop the old IMR contents from the stack. 7. Execute an IRET instruction to return from the interrupt service routine.

Generating Vectored Interrupts from Software

Software generates Z8 LXM CPU interrupt requests by writing to the Interrupt Request (IRQ) register, Bank 0 register FAh. For register details, see Table 7 on page 8. The interrupt controller and Z8 LXM CPU handle these software interrupts in the same manner as hardware-generated interrupt requests. To generate a software interrupt, write 1 to the preferred interrupt request bit in the Interrupt Request register. For example:

OR IRQ, #0000100b

The above instruction writes 1 to bit 2 of the Interrupt Request register. If this interrupt at bit 2 is enabled and there are no higher priority pending interrupt requests, Program control transfers to the ISR specified by the corresponding interrupt vector.

Polled Interrupt Processing

Polled interrupt processing is supported by individually disabling the interrupts to be polled. To initiate polled processing, check the interrupt bits of interest in the interrupt request (IRQ) register using the Test Under Mask (TM) instruction. If the bit is 1, perform a software call or branch to the ISR. Write the service routine to service the request, clear the interrupt request bit in the IRQ register, and return or branch back to the main program. An example of a polling routine is given below:

UM018304-0707 Interrupts Z8 LXM CPU Core User Manual

TM IRQ, #0000100b ; Test for interrupt request in bit 2 of IRQ JR Z, NEXT ; If no interrupt request, go ; to NEXT, otherwise call the ISR. NEXT: ; Other program code here.

SERVICE: ; Process interrupt request ; service routine code here.

DI ; Disable interrupts before writing IRQ AND IRQ, #1111011b ; Clear the interrupt request ; in bit 2 of IRQ EI ; Re-enable vectored interrupts (if ; appropriate). RET ; Return to address following ; the CALL

UM018304-0707 Interrupts Z8 LXM CPU Core User Manual

Processor Flags

The Z8 LXM CPU Flags register contains the status information regarding the most recent arithmetic, logical, bit manipulation, or rotate and shift operation. The Flags register contains six bits of status information that are set or cleared by CPU operations. Four of the bits (C, V, Z, and S) are tested with conditional jump instructions. Two flags (H and D) cannot be tested and are used for Binary-Coded Decimal (BCD) arithmetic. The two remaining bits, User Flags (F1 and F2), are available as general-purpose status bits. User Flags are unaffected by arithmetic operations and must be set or cleared by instructions. The User Flags cannot be used with conditional Jumps. They are undefined at initial power-up and are unaffected by Reset. Figure 21 illustrates the flags and their bit positions in the Flags register.

Bit Bit 7 0

C Z S V D H F2 F1 Flags Register

User Flags Half Carry Flag Decimal Adjust Flag Overflow Flag Sign Flag Zero Flag Carry Flag Figure 21. Flags Register

Interrupts write the value of the Flags register to the stack. Executing an Interrupt Return (IRET) instruction restores the value saved on the stack into the Flags register. If a program explicitly writes to the Flags register, it must do using instructions that do not otherwise affect flags, for example, an immediate LD instruction.

UM018304-0707 Processor Flags Z8 LXM CPU Core User Manual

Carry Flag

The Carry flag (C) is 1 when the result of an arithmetic operation generates a carry out of or a borrow into the msb (bit 7) of the data. Otherwise, the Carry flag is 0. Some bit rotate or shift instructions also affect the Carry flag. Following three instructions are available for directly changing the value of the Carry Flag: • Complement Carry Flag (CCF) • Reset Carry Flag (RCF) • Set Carry Flag (SCF)

Zero Flag

For arithmetic and logical operations, the Zero (Z) flag is 1 if the result is 0. Otherwise, the Zero flag is 0. If the result of testing bits in a register is 00h, the Zero flag is 1; otherwise, the Zero flag is 0. Also, if the result of a rotate or shift operation is 00h, the Zero flag is 1; otherwise, the Zero flag is 0.

Sign Flag

The Sign (S) flag stores the value of the msb of a result following an arithmetic, logical, rotate or shift operation. For signed numbers, the Z8 LXM CPU uses binary two’s complement to represent the data and perform the arithmetic operations. A 0 in the msb (bit 7) identifies a positive number; therefore, the Sign flag is also 0. A 1 in the msb (bit 7) identifies a negative number; therefore, the Sign flag is also 1.

Overflow Flag

For signed arithmetic, rotate or shift operations, the Overflow (V) flag is 1 when the result is greater than the maximum possible number, +127, or less than the minimum possible number, –128, that is represented with 8-bits in two’s complement form. The Overflow flag is 0 if no overflow occurs. Following logical operations, the Overflow flag is 0. Performing addition operations, the Overflow flag is 1 when the operands have the same sign, but the result has the opposite sign. Performing subtraction operations, the Overflow flag is 1 if the two operands are of opposite sign and the sign of the result is same as the sign of the source. Performing rotation operations, the Overflow flag is 1 if the sign bit of the destination operand changed during rotation.

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Decimal Adjust Flag

The Decimal Adjust (D) flag is used for BCD arithmetic operations, because the algorithm for correcting BCD operations is different for addition and subtraction. This flag specifies the type of instruction that was last executed, enabling the subsequent decimal adjust (DA) operation. After a subtraction, the DA flag is 1. Performing an addition, it is 0. The DA flag is tested internally by the DA instruction, so this flag does not affect the state of any condition code.

Half Carry Flag

The Half Carry (H) flag is 1 when an addition generates a carry from bit 3 or a subtraction generates a borrow from bit 4. The DA instruction converts the binary result of a previous addition or subtraction into the correct BCD result using the Half Carry flag. Like the DA flag, the Half Carry flag does not affect the state of any condition code.

Condition Codes

The C, Z, S, and V flags control the operation of the conditional jump (JP cc and JR cc) instructions. Sixteen frequently useful functions of the flag settings are encoded in a 4-bit field called the condition code (cc), which forms bits 7:4 of the first opcode of conditional jump instructions. Table 13 summarizes the condition codes. Some binary condition codes are created using more than one assembly code mnemonic. The result of the flag test operation determines if the conditional jump executes.

Table 13. Condition Codes

Assembly Binary Hex Mnemonic Definition Flag Test Operation 0000 0 F Always False – 0001 1 LT Less Than (S XOR V) = 1 0010 2 LE Less Than or Equal (Z OR (S XOR V)) = 1 0011 3 ULE Unsigned Less Than or Equal (C OR Z) = 1 0100 4 OV Overflow V = 1 0101 5 Ml Minus S = 1 0110 6 Z Zero Z = 1 0110 6 EQ Equal Z = 1 0111 7 C Carry C = 1

UM018304-0707 Processor Flags Z8 LXM CPU Core User Manual

Table 13. Condition Codes (Continued)

Assembly Binary Hex Mnemonic Definition Flag Test Operation 0111 7 ULT Unsigned Less Than C = 1 1000 8 T (or blank) Always True – 1001 9 GE Greater Than or Equal (S XOR V) = 0 1010 A GT Greater Than (Z OR (S XOR V)) = 0 1011 B UGT Unsigned Greater Than (C = 0 AND Z = 0) 1100 C NOV No Overflow V = 0 1101 D PL Plus S = 0 1110 E NZ Non-Zero Z = 0 1110 E NE Not Equal Z = 0 1111 F NC No Carry C = 0 1111 F UGE Unsigned Greater Than or C = 0 Equal

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Z8 LXM CPU Instruction Set Summary

Z8 LXM CPU programs are written in assembly language and then assembled into the numerical object code that the CPU executes. For details on developing Z8 LXM CPU programs, refer to Zilog Developer Studio II—Crimzon User Manual (UM0164). In assembly language, each Z8 LXM CPU instruction is represented by a readable text statement consisting of an instruction mnemonic and possibly one or more operands (symbols, labels, expressions, or numbers) that specify addresses or other values to be used in the operation. In object code, each Z8 LXM CPU instruction consists of one opcode byte and possibly one or two operand bytes. This manual’s instruction set summary and description sections list the valid assembly language syntax and object code formats for each Z8 LXM CPU instruction. An assembly language source program also includes comments that make the program more readable or assembler directives that control the assembly process. Such elements are not translated into object code.

Assembly Language Source Program Example

JP START ; Everything after the semicolon is a ; comment. START: ; A label called "START". The first ; instruction (JP START) in this example ; causes program execution to jump to the ; point within the program where the START ; label occurs. LD R4, R7 ; A Load (LD) instruction with two ; operands. The first operand, working ; register R4, is the destination. ; The second operand, working register R7, ; is the source. The contents of R7 ; are written into R4. LD 34h, #%01 ; Another Load (LD) instruction with ; two operands. The first operand, ; register address 34h, identifies the ; destination. The second operand, ; immediate data value 01h, is the source. ; The value 01h is written into the ; register at address 34h.

UM018304-0707 Z8 LXM CPU Instruction Set Summary Z8 LXM CPU Core User Manual

Operand Ordering

For proper instruction execution, Z8 LXM CPU assembly language syntax requires that the operands be written in the order ‘destination, source’. After assembly, the object code usually places the operands in the order ‘source, destination’, but some opcodes use a different order. When hand-assembling or disassembling object code, always refer to instruction description to determine the correct order for operand bytes.

Example 1 If the contents of registers 43h and 08h are added and the result is stored in 43h, the assembly syntax and resulting object code is:

Table 14. Assembly Language Syntax Example 1

Assembly Language Code ADD 43h, 08h (ADD dst, src) Object Code 04 08 43 (OPC src, dst)

Example 2 In general, when an instruction format requires an 8-bit register address, that address specifies any register location in the range 0–255 or, using escaped mode addressing, a working register R0–R15. If the contents of Register 43h and working register R8 are added and the result is stored in 43h, the assembly syntax and resulting object code is:

Table 15. Assembly Language Syntax Example 2

Assembly Language Code ADD 43h, R8 (ADD dst, src) Object Code 04 E8 43 (OPC src, dst)

Z8 LXM CPU Instruction Notation

Table 16 describes the notation used to represent operands symbolically in most of the reference portions of this manual, with examples to show how the reference notation compares to the operand syntax in assembly language. In reference notation only, lowercase is used to distinguish 4-bit addressed working registers (r1, r2) from 8-bit addressed registers (R1, R2). The numerals 1 and 2, respectively, indicate whether the register is used for destination or source addressing. Except for user-defined labels, assembly language operands are not case sensitive. In Table 16, the text variable n represents a decimal number; aa represents a hexadecimal address; and LABEL represents a label defined elsewhere in the assembly source.

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Examples imply the use of explicit decimal or hexadecimal values, but you can use any notation that the assembler accepts. In actual assembly source, such values are often expressed as labels or expressions. . Table 16. Symbolic Notation for Operands

Assembly Symbol Operand Description cc – Condition Code cc represents a condition code mnemonic. See Condition Codes on page 41. IM #n Immediate Data IM represents an Immediate Data value, prefixed by # in assembly language. The immediate value follows the instruction opcode in program memory. n = 0 to 255. r1 Rn Working Register r2 r1 or r2 represents the name, Rn, of a working register, where n = 0, 1, 2,..., 15. The equivalent 12-bit address is {RP[3:0], RP[7:4], n}. rr1 RRn Working Register Pair rr2 rr1 or rr2 represents the name, Rn, of a working register pair, where n = 0, 2, 4,..., 14. The equivalent 12-bit address is {RP[3:0], RP[7:4], n}. R1 %aa Register R2 R1 or R2 represents an 8-bit register address. For addresses 00h–DFh or F0h–FFh, the equivalent 12-bit address is {RP[3:0], %aa}. For addresses E0h–EFh (escaped mode), the equivalent 12-bit address is {RP[3:0], RP[7:4], %aa[3:0]}. RR1 %aa Register Pair (8-bit Address) RR2 RR1 or RR2 represents the 8-bit address of a register pair. For addresses 00h–DFh or F0h–FFh, the equivalent 12-bit address is {RP[3:0], %aa}. For addresses E0h–EFh (escaped mode), the equivalent 12-bit address is {RP[3:0], RP[7:4], %aa[3:0]}. Irr1 @Rn Indirect Working Register Irr2 Ir1 or Ir2 represents the name of a working register, Rn, where n = 0, 1, 2,..., 15. @ indicates Indirect Working Register addressing using an 8-bit effective address contained in the specified working register. The accessed register’s equivalent 12-bit address is {RP[3:0], 8-bit effective address}. Irr1 @RRn Indirect Working Register Pair Irr2 Irr1 or Irr2 represents the name of a working register pair, RRn, where n = 0, 2, 4,..., 14. @ indicates Indirect Working Register addressing using an effective address in the specified working register pair. Depending on the instruction, the effective address is in the register file (12-bit address) or program/constant memory (16-bit address).

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Table 16. Symbolic Notation for Operands (Continued)

Assembly Symbol Operand Description IR1 @%aa Indirect Register IR2 IR1 or IR2 represents the 8-bit address of a register. @ indicates Indirect Register addressing using an 8-bit effective address contained in the specified register. The accessed register’s equivalent 12-bit address is {RP[3:0], 8-bit effective address}. IRR1 @%aa Indirect Register Pair IRR1 represents the 8-bit address of a register. @ indicates Indirect Register addressing with a 16-bit effective address (in program memory) contained in the specified register pair. X(r1) %aa(Rn) Indexed (X) Addressing X(r2) X represents the 8-bit base address to which the offset is added. r1 or r2 represents the name, Rn, of a working register containing the 8-bit signed offset. The 8-bit effective address is the sum of X and the contents of working register Rn. The accessed register’s equivalent 12-bit address is {RP[3:0], 8-bit effective address}. DA LABEL Direct Address (JP, CALL) In a JP or CALL operand, DA is a 16-bit program memory address in the range of 0000H to FFFFH. DA replaces the contents of the PC to cause execution to continue at a new location in program memory. In assembly source, the address is typically represented as a label. RA LABEL Relative Address (JR, DJNZ) RA is a signed 8-bit program memory offset in the range +127 to –128, relative to the address of the next instruction in program memory. In a JR or DJNZ operation, RA is added to the program counter to cause execution to continue at a new location in program memory. In assembly source, the jump address is typically represented as an absolute label, and the assembler calculates RA.

Table 17 provides additional symbols that are used throughout the instruction set summary and descriptions.

Table 17. Additional Symbols

Symbol Definition dst Destination Operand src Source Operand @ Indirect Address Prefix C Carry Flag

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Table 17. Additional Symbols (Continued)

Symbol Definition SP Stack Pointer Value PC Program Counter FLAGS Flags Register RP Register Pointer # Immediate Operand Prefix b Binary Number Suffix % Hexadecimal Number Prefix h Hexadecimal Number Suffix ← Assignment of a value. For example, dst ← dst + src indicates the result is stored in the destination. ↔ Exchange of two values ~ One’s complement unary operator

Z8 LXM CPU Instruction Classes

Z8 LXM CPU instructions are divided functionally into the following groups: • Arithmetic • Bit Manipulation • Block Transfer • CPU Control • Load • Logical • Program Control • Rotate and Shift

Table 18 through Table 25 describes instructions belonging to each group and the number of operands required for each instruction. Some instructions appear in more than one table as these instructions can be considered as a subset of more than one category. Within these tables, the source operand is identified as ‘src’, the destination operand is ‘dst’ and a condition code is ‘cc’.

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Table 18. Arithmetic Instructions

Mnemonic Operands Instruction ADC dst, src Add with Carry ADD dst, src Add CP dst, src Compare DA dst Decimal Adjust DEC dst Decrement DECW dst Decrement Word INC dst Increment INCW dst Increment Word SBC dst, src Subtract with Carry SUB dst, src Subtract

Table 19. Bit Manipulation Instructions

Mnemonic Operands Instruction CCF – Complement Carry Flag RCF – Reset Carry Flag SCF – Set Carry Flag TCM dst, src Test Complement Under Mask TM dst, src Test Under Mask

Table 20. Block Transfer Instructions

Mnemonic Operands Instruction LDCI dst, src Load Constant to/from Program/Constant Memory and Auto-Increment Addresses LDXI dst, src Load Register to/from Extended Register Bank and Auto-Increment Addresses

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Table 21. CPU Control Instructions

Mnemonic Operands Instruction CCF – Complement Carry Flag DI – Disable Interrupts EI – Enable Interrupts HALT – HALT Mode NOP – No Operation RCF – Reset Carry Flag SCF – Set Carry Flag SRP src Set Register Pointer STOP – STOP Mode WDH – Watchdog Timer During HALT Mode WDT – Watchdog Timer Refresh

Table 22. Load Instructions

Mnemonic Operands Instruction CLR dst Clear LD dst, src Load LDC dst, src Load Constant to/from Program Memory LDCI dst, src Load Constant to/from Program Memory and Auto-Increment Addresses LDX dst, src Load Data to/from Extended Register Bank LDXI dst, src Load Data to/from Extended Register Bank and Auto-Increment Addresses POP dst Pop PUSH src Push

Table 23. Logical Instructions

Mnemonic Operands Instruction AND dst, src Logical AND COM dst Complement

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Table 23. Logical Instructions (Continued)

Mnemonic Operands Instruction OR dst, src Logical OR XOR dst, src Logical Exclusive OR

Table 24. Program Control Instructions

Mnemonic Operands Instruction CALL dst Call Procedure DJNZ dst, RA Decrement and Jump Non-Zero IRET – Interrupt Return JP dst Jump JP cc dst Jump Conditional JR RA Jump Relative JR cc RA Jump Relative Conditional RET – Return

Table 25. Rotate and Shift Instructions

Mnemonic Operands Instruction RL dst Rotate Left RLC dst Rotate Left through Carry RR dst Rotate Right RRC dst Rotate Right through Carry SRA dst Shift Right Arithmetic SWAP dst Swap Nibbles

UM018304-0707 Z8 LXM CPU Instruction Set Summary Z8 LXM CPU Core User Manual

Z8 LXM CPU Instruction Summary

Table 26 summarizes the Z8 LXM CPU instructions. The table identifies the addressing modes used by the instruction, the effect on the Flags register, the number of CPU clock cycles required for the instruction fetch, and the number of CPU clock cycles required for the instruction execution.

Table 26. Z8 LXM CPU Instruction Summary

Address Mode Op- Flags Cycles Assembly code(s) Mnemonic Symbolic Operation dst src(Hex) C Z S V D H Fetch Execute ADC dst, src dst ← dst + src + C r r 12 * * * * 0 * 6 5 rIr13 6 5 R R 14 10 5 RIR15 10 5 RIM16 10 5 IR IM 17 10 5 ADD dst, src dst ← dst + src r r 02 * * * * 0 * 6 5 rIr03 6 5 R R 04 10 5 RIR05 10 5 RIM06 10 5 IR IM 07 10 5 AND dst, src dst ← dst AND src r r 52 – * * 0 – – 6 5 rIr53 6 5 R R 54 10 5 RIR55 10 5 RIM56 10 5 IR IM 57 10 5 CALL dst SP ← SP -2 IRR D4 –––––– 20 0 @SP ← PC DA D6 20 0 PC ← dst CCF C ← ~C EF *––––– 6 5 Flag States: * = State Depends on Result; – = No Change; X = Undefined; 0 = Cleared; 1 = Set

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Table 26. Z8 LXM CPU Instruction Summary (Continued)

Address Mode Op- Flags Cycles Assembly code(s) Mnemonic Symbolic Operation dst src(Hex) C Z S V D H Fetch Execute CLR dst dst ← 00h R B0 –––––– 6 5 IR B1 6 5 COM dst dst ← ~dst R 60 – * * 0 – – 6 5 IR 61 6 5 CP dst, src dst – src – C r r A2 * * * * – – 6 5 rIrA3 6 5 RR A4 105 RIRA5 10 5 RIMA6 10 5 IR IM A7 10 5 DA dst dst ← DA(dst) R 40 * * * X – – 8 5 IR 41 8 5 DEC dst dst ← dst – 1 R 00 – * * * – – 6 5 IR 01 6 5 DECW dst dst ← dst – 1 RR 80 – * * * – – 10 5 IR 81 10 5 DI Disable Interrupts 8F –––––– 6 1 IRQCTL[7] ← 0 DJNZ dst, RA dst ← dst – 1 r 0A–FA–––––– NZ/Z if dst ≠ 0 12/10 5 PC ← PC + X EI Enable Interrupts 9F –––––– 6 1 IRQCTL[7] ← 1 HALT Halt Mode 7F –––––– 7 0 INC dst dst ← dst + 1 R 20 – * * * – – 6 5 IR 21 6 5 r0E–FE 65 Flag States: * = State Depends on Result; – = No Change; X = Undefined; 0 = Cleared; 1 = Set

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Table 26. Z8 LXM CPU Instruction Summary (Continued)

Address Mode Op- Flags Cycles Assembly code(s) Mnemonic Symbolic Operation dst src(Hex) C Z S V D H Fetch Execute INCW dst dst ← dst + 1 RR A0 – * * * – – 10 5 IR A1 10 5 IRET FLAGS ← @SP BF ****** 16 0 SP ← SP + 1 PC ← @SP SP ← SP + 2 IRQCTL[7] ← 1 JP dst PC ← dst DA 8D –––––– 12 0 IRR 30 8 0 JP cc, dst if cc is true DA 0D–FD – – – – – – T/F PC ← dst 12/10 0 JR dst PC ← PC + X RA 8B –––––– 12 0 JR cc, dst if cc is true RA 0B–FB – – – – – – T/F PC ← PC + X 12/10 0 LD dst, src dst ← src r IM 0C–FC – – – – – – 6 5 r R 08–F8 6 5 R r 09–F9 6 5 rX(r)C7 10 5 X(r) r D7 10 5 rIrE3 6 5 RR E4 105 RIRE5 10 5 RIME6 10 5 IR IM E7 10 5 Ir r F3 6 5 IR R F5 10 5 LDC dst, src dst ← src r Irr C2 – – – – – – 12 0 Irr r D2 12 0 Flag States: * = State Depends on Result; – = No Change; X = Undefined; 0 = Cleared; 1 = Set

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Table 26. Z8 LXM CPU Instruction Summary (Continued)

Address Mode Op- Flags Cycles Assembly code(s) Mnemonic Symbolic Operation dst src(Hex) C Z S V D H Fetch Execute LDCI dst, src dst ← src Ir Irr C3 – – – – – – 18 0 r ← r + 1 Irr Ir D3 18 0 rr ← rr + 1 LDX dst, src dst ← src r Irr 82 – – – – – – 12 0 Irr r 92 12 0 LDXI dst, src dst ← src Ir Irr 83 – – – – – – 18 0 r ← r + 1 Irr Ir 93 18 0 rr ← rr + 1 NOP No operation FF – – – – – – 6 0 OR dst, src dst ← dst OR src r r 42 – * * 0 – – 6 5 rIr43 6 5 R R 44 10 5 RIR45 10 5 RIM46 10 5 IR IM 47 10 5 POP dst dst ← @SP R 50 –––––– 10 5 SP ← SP + 1 IR 51 10 5 PUSH src SP ← SP – 1 R 70 –––––– 10 1 @SP ← src IR 71 12 1 RCF C ← 0 CF 0––––– 6 5 RET PC ← @SP AF –––––– 14 0 SP ← SP + 2 RL dst R 90 ****–– 6 5 C D7 D6 D5 D4 D3 D2 D1 D0 dst IR 91 6 5

RLC dst R 10 * * * * – – 6 5 C D7 D6 D5 D4 D3 D2 D1 D0 dst IR 11 6 5

Flag States: * = State Depends on Result; – = No Change; X = Undefined; 0 = Cleared; 1 = Set

UM018304-0707 Z8 LXM CPU Instruction Set Summary Z8 LXM CPU Core User Manual

Table 26. Z8 LXM CPU Instruction Summary (Continued)

Address Mode Op- Flags Cycles Assembly code(s) Mnemonic Symbolic Operation dst src(Hex) C Z S V D H Fetch Execute RR dst R E0 ****–– 6 5 D7 D6 D5 D4 D3 D2 D1 D0 C dst IR E1 6 5

RRC dst R C0 * * * * – – 6 5 D7 D6 D5 D4 D3 D2 D1 D0 C dst IR C1 6 5

SBC dst, src dst ← dst – src – C r r 32 * * * * 1 * 6 5 rIr33 6 5 R R 34 10 5 RIR35 10 5 RIM36 10 5 IR IM 37 10 5 SCF C ← 1 DF 1––––– 6 5 SRA dst R D0 * * * 0 – – 6 5 D7 D6 D5 D4 D3 D2 D1 D0 C dst IR D1 6 5

SRP src RP ← src IM 31 –––––– 6 1 STOP Stop Mode 6F –––––– 6 0 SUB dst, src dst ← dst – src r r 22 * * * * 1 * 6 5 rIr23 6 5 R R 24 10 5 RIR25 10 5 RIM26 10 5 IR IM 27 10 5 SWAP dst dst[7:4] ↔ dst[3:0] R F0 – * * X – – 8 5 IR F1 8 5 Flag States: * = State Depends on Result; – = No Change; X = Undefined; 0 = Cleared; 1 = Set

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Table 26. Z8 LXM CPU Instruction Summary (Continued)

Address Mode Op- Flags Cycles Assembly code(s) Mnemonic Symbolic Operation dst src(Hex) C Z S V D H Fetch Execute TCM dst, src (NOT dst) AND src r r 62 – * * 0 – – 6 5 rIr63 6 5 R R 64 10 5 RIR65 10 5 RIM66 10 5 IR IM 67 10 5 TM dst, src dst AND src r r 72 – * * 0 – – 6 5 rIr73 6 5 R R 74 10 5 RIR75 10 5 RIM76 10 5 IR IM 77 10 5 WDH 4F –––––– 6 0 WDT 5F –––––– 6 0 XOR dst, src dst ← dst XOR src r r B2 – * * 0 – – 6 5 rIrB3 6 5 RR B4 105 RIRB5 10 5 RIMB6 10 5 IR IM B7 10 5 Flag States: * = State Depends on Result; – = No Change; X = Undefined; 0 = Cleared; 1 = Set

UM018304-0707 Z8 LXM CPU Instruction Set Summary Z8 LXM CPU Core User Manual

Z8 LXM CPU Instruction Set Description

This chapter provides a detailed descriptions of the assembly language instructions available with the Z8 LXM CPU. The Z8 LXM CPU instruction set is similar to the original Z8 instruction set, except the external memory instructions LDE and LDEI have been replaced by LDX and LDXI, which provide 12-bit linear addressing for the extended register file. Each instruction in this chapter is organized alphabetically by mnemonic, and follows the convention of the example on the next page. Instruction Mnemonic Instruction Name Summary Syntax Operation Symbolic description of the instruction performed.

Description Detailed description of the instruction operation.

Flags Information on how the CPU Flags are affected by the instruction operation.

Instruction Format and Cycles Table provides information on assembly code, opcode value, and operand ordering.

Escaped Mode Addressing Description of escaped mode addressing applicable to this instruction.

Sample Usage A simple code example using the instruction.

UM018304-0707 Z8 LXM CPU Instruction Set Description Z8 LXM CPU Core User Manual

ADC Add with Carry ADC dst, src Operation dst ← dst + src + C

Description The source operand and the Carry (C) flag are added to the destination operand. Two’s-complement addition is performed. The sum is stored in the destination operand. The contents of the source operand are not affected. In multiple-precision (multi-byte) arithmetic, this instruction permits the carry from the addition of low-order byte operations to be carried into the addition of high-order bytes.

Flags

C Set if there is a carry from bit 7; cleared otherwise Z Set if the result is zero; cleared otherwise S Set if the result is negative; cleared otherwise V Set if an arithmetic overflow occurs; cleared otherwise D Cleared to 0 H Set if there is a carry from bit 3 of the result; cleared otherwise

Instruction Format and Cycles

Opcode Operand Bytes Cycles Assembly Syntax (Hex)123FetchExecute ADC r1, r2 12 {r1, r2} — — 6 5 ADC r1, @r2 13 {r1, r2} — — 6 5 ADC R1, R2 14 R2 R1 — 10 5 ADC R1, @R2 15 R2 R1 — 10 5 ADC R1, IM 16 R1 IM — 10 5 ADC @R1, IM 17 R1 IM — 10 5

UM018304-0707 ADC Instruction Z8 LXM CPU Core User Manual

working register R12 (Ch) is addressed instead. To access registers E0h to EFh, either set the Working Group Pointer, RP[7:4] to Eh, or use indirect addressing.

Sample Usage

Example 1–If working register R3 contains the value 16h, the carry flag is 1, and working register R11 contains the value 20h, the following statement leaves the value 37h in working register R3 and clears the C, Z, S, V, D, and H flags: ADC R3, R11 ;Object Code: 12 3B

Example 2–If working register R15 contains the value 16h, the carry flag is not set, working register R10 contains the value 20h, and register 20h contains the value 11h, the following statement leaves the value 27h in working register R15 and clears the C, Z, S, V, D, and H flags: ADC R15, @R10 ;Object Code: 13 FA

Example 3–If register 34h contains the value 2Eh, the carry flag is set, and register 12h contains the value 1bh, the following statement leaves the value 4Ah in register 34h, sets the H flag, and clears the C, Z, S, V, and D flags: ADC 34h, 12h ;Object Code: 14 12 34

Example 4–Using Escaped Mode Addressing, if working register R4 contains the value 2Eh, the carry flag is set, and register 12h contains the value 1bh, the following statement leaves the value 4Ah in working register R4, sets the H flag, and clears the C, Z, S, V, and D flags: ADC E4h, 12h ;Object Code: 14 12 E4

Example 5–Using Escaped Mode Addressing, if register 4Bh contains the value 82h, the carry flag is set, working register R3 contains the value 10h, and register 10h contains the value 01h, the following statement leaves the value 84h in register 4Bh, sets the S flag, and clears the C, Z, V, D, and H flags: ADC 4Bh, @E3h ;Object Code: 15 E3 4B

Example 6–If register 6Ch contains the value 2Ah, and the carry flag is not set, the following statement leaves the value 2Dh in register 6Ch and clears the C, Z, S, V, D, and H flags: ADC 6Ch, #03h ;Object Code: 16 6C 03

Example 7–If register D4h contains the value 5Fh, register 5Fh contains the value 4Ch, and the carry flag is set, the following statement leaves the value 4Fh in register 5Fh and clears the C, Z, S, V, D, and H flags: ADC @D4h, #02h ;Object Code: 17 D4 02

UM018304-0707 ADC Instruction Z8 LXM CPU Core User Manual

ADD Add ADD dst, src Operation dst ← dst + src

Description Add the source operand to the destination operand. Perform two’s-complement addition. Store the sum in the destination operand. The contents of the source operand are not affected.

Flags

C Set if there is a carry from bit 7; cleared otherwise Z Set if the result is zero; cleared otherwise S Set if the result is negative; cleared otherwise V Set if both operands are of the same sign and the result is of the opposite sign; cleared otherwise D Cleared to 0 H Set if there is a carry from bit 3 of the result; cleared otherwise

Instruction Format and Cycles

Opcode Operand Bytes Cycles Assembly Syntax (Hex) 1 2 3 Fetch Execute ADD r1, r2 02 {r1, r2} — — 6 5 ADD r1, @r2 03 {r1, r2} — — 6 5 ADD R1, R2 04 R2 R1 — 10 5 ADD R1, @R2 05 R2 R1 — 10 5 ADD R1, IM 06 R1 IM — 10 5 ADD @R1, IM 07 R1 IM — 10 5

UM018304-0707 ADD Instruction Z8 LXM CPU Core User Manual

Sample Usage

Example 1–If working register R3 contains the value 16h and working register R11 contains the value 20h, the following statement leaves the value 36h in working register R3 and clears the C, Z, S, V, D, and H flags: ADD R3, R11 ;Object Code: 02 3B

Example 2–If working register R15 contains the value 16h, working register R10 contains 20h, and register 20h contains the value 11h, the following statement leaves the value 27h in working register R15 and clears the C, Z, S, V, D, and H flags: ADD R15, @R10 ;Object Code: 03 FA

Example 3–If register 34h contains the value 2Eh and register 12h contains the value 1bh, the following statement leaves the value 49h in register 34h, sets the H flag, and clears the C, Z, S, V, and D flags: ADD 34h, 12h ;Object Code: 04 12 34

Example 4–Using Escaped Mode Addressing, if register 4Bh contains the value 82h, working register R3 contains the value 10h, and register 10h contains the value 01h, the following statement leaves the value 83h in register 4Bh, sets the S flag, and clears the C, Z, V, D, and H flags: ADD 4Bh, @E3h ;Object Code: 05 E3 4B

Example 5–If register 6Ch contains the value 2Ah, the following statement leaves the value 2Dh in register 6h. The C, Z, S, V, D, and H flags clear. ADD 6Ch, #03h ;Object Code: 06 6C 03

Example 6–If register D4h contains the value 5Fh and register 5Fh contains the value 4Ch, the following statement leaves the value 4Eh in register 5Fh and clears the C, Z, S, V, D, and H flags: ADD @D4h, #02h ;Object Code: 07 D4 02

UM018304-0707 ADD Instruction Z8 LXM CPU Core User Manual

AND Logical AND AND dst, src Operation dst ← dst AND src

Description The source operand is logically ANDed with the destination operand. An AND operation stores a 1 when the corresponding bits in the two operands are both 1; otherwise the operation stores a 0. The destination operand contains the result. The contents of the source bit are unaffected. Table 27 summarizes the AND operation.

Table 27. Truth Table for AND

dst src dst Bit Bit Result 000 010 100 111

Flags

C Unaffected Z Set if the result is zero; cleared otherwise S Set if bit 7 of the result is set; cleared otherwise V Cleared to 0 D Unaffected H Unaffected

UM018304-0707 AND Instruction Z8 LXM CPU Core User Manual

Instruction Format and Cycles

Opcode Operand Bytes Cycles Assembly Syntax (Hex) 1 2 3 Fetch Execute AND r1, r2 52 {r1, r2} — — 6 5 AND r1, @r2 53 {r1, r2} — — 6 5 AND R1, R2 54 R2 R1 — 10 5 AND R1, @R2 55 R2 R1 — 10 5 AND R1, IM 56 R1 IM — 10 5 AND @R1, IM 57 R1 IM — 10 5

Sample Usage

Example 1–If working register R1 contains the value 38h (00111000b) and working register R14 contains the value 8Dh (10001101b), the following statement leaves the value 08h (00001000b) in working register R1 and clears the Z, V, and S flags: AND R1, R14 ;Object Code: 52 1E

Example 2–If working register R4 contains the value F9h (11111001b), working register R13 contains the value 7Bh, and register 7Bh contains the value 6Ah (01101010b), the following statement leaves the value 68h (01101000b) in working register R4 and clears the Z, V, and S flags: AND R4, @R13 ;Object Code: 53 4D

Example 3–If register 3Ah contains the value F5h (11110101b) and register 42h contains the value 0Ah (00001010b), the following statement leaves the value 00h (00000000b) in register 3Ah, sets the Z flag, and clears the V and S flags: AND 3Ah, 42h ;Object Code: 54 42 3A

Example 4–Using Escaped mode addressing, if working register R5 contains the value F0h (11110000b), register 45h contains the value 3Ah, and register 3Ah contains the value 7Fh (01111111b), the following statement leaves the value 70h (01110000b) in working register R5 and clears the Z, V, and S flags: AND E5h, @45h ;Object Code: 55 45 E5

UM018304-0707 AND Instruction Z8 LXM CPU Core User Manual

Example 5–If register 7Ah contains the value F7h (11110111b), the following statement leaves the value F0h (11110000b) in register 7Ah, sets the S flag is set and clears the Z and V flags: AND 7Ah, #F0h ;Object Code: 56 7A F0

Example 6–Using Escaped mode addressing, if working register R3 contains the value 3Eh and register 3Eh contains the value ECh (11101100b), the following statement leaves the value 04h (00000100b) in register 3Eh and clears the Z, V, and S flags: AND @E3h, #05h ;Object Code: 57 E3 05

UM018304-0707 AND Instruction Z8 LXM CPU Core User Manual

CALL Call Procedure CALL dst Operation SP ← SP – 2 @SP ← PC PC ← dst

Description The Stack Pointer decrements by two, the current contents of the Program Counter, which is the address of the first instruction following the CALL instruction, are pushed onto the top of the stack, and the specified destination address is then loaded into the Program Counter. The Program Counter now points to the first instruction of the procedure. At the end of the procedure, a RET instruction is used to return to the original program flow. RET pops the original Program Counter value from the stack and loads it into the Program Counter.

Flags

C Unaffected Z Unaffected S Unaffected V Unaffected D Unaffected H Unaffected

Instruction Format and Cycles

Opcode Operand Bytes Cycles Assembly Syntax (Hex) 1 2 3 Fetch Execute CALL @RR1 D4 RR1 — — 20 0 CALL DA D6 DA[15:8] DA[7:0] — 20 0

Escaped Mode Addressing For an indirect register pair operand (@RR1), an 8-bit address in the range E0h to EFh always addresses the current working register group. For example, if register pair address ECh is specified, working register pair R12 (Ch) is addressed instead. To use register pairs E0h to EEh, first set the Working Group Pointer, RP[7:4] to Eh.

UM018304-0707 CALL Instruction Z8 LXM CPU Core User Manual

Sample Usage

Example 1–If the contents of the Program Counter are 1A47h and the contents of the Stack Pointer are A2h, the following statement causes the Stack Pointer to be decremented to A0h, 1A4Ah (the address following the CALL instruction) to be stored in program memory locations A1h and A0h, and the Program Counter to be loaded with 3521h: CALL 3521h ;Object Code: D6 35 21 The Program Counter now points to the address of the first statement in the called procedure to be executed. The flags are unaffected.

Example 2–If the contents of the Program Counter are 1A47h and the contents of the Stack Pointer are D4h, the contents of register A4h are 34h, and the contents of the register pair 34h are 3521h, the following statement causes the Stack Pointer to decrement to D2h, stores 1A4Ah (the address following the CALL instruction) in program memory locations 3723h and 3722h, and loads the Program Counter with 3521h: CALL @A4h ;Object Code: D4 A4 The Program Counter now points to the address of the first statement in the called procedure to be executed. The flags are unaffected.

UM018304-0707 CALL Instruction Z8 LXM CPU Core User Manual

CCF Complement Carry Flag CCF Operation C ← ~C

Description The Carry (C) flag is complemented. If C = 1, it changes to 0. If C = 0, it changes to 1.

Flags

C Complemented Z Unaffected S Unaffected V Unaffected D Unaffected H Unaffected

Instruction Format and Cycles

Opcode Operand Bytes Cycles Assembly Syntax (Hex) 1 2 3 Fetch Execute CCF EF———65

Sample Usage If the Carry flag contains a 0, the following statement sets the Carry flag to 1: CCF ;Object Code: EF

UM018304-0707 CCF Instruction Z8 LXM CPU Core User Manual

CLR Clear CLR dst Operation dst ← 00h

Description The destination operand is cleared to 00h.

Flags

C Unaffected Z Unaffected S Unaffected V Unaffected D Unaffected H Unaffected

Instruction Format and Cycles

Opcode Operand Bytes Cycles Assembly Syntax (Hex) 1 2 3 Fetch Execute CLR R1 B0 R1 — — 6 5 CLR @R1 B1 R1 — — 6 5

Sample Usage Example 1–Using Escaped mode addressing, if working register R6 contains AFh, the following statement leaves the value 00h in working register R6: CLR E6h ;Object Code: B0 E6 Example 2–If register A5h contains the value 23h, and register 23h contains the value FCh, the following statement leaves the value 00h in register 23h: CLR @A5h ;Object Code: B1 A5

UM018304-0707 CLR Instruction Z8 LXM CPU Core User Manual

COM Complement COM dst Operation dst ← ~dst

Description The contents of the destination operand are complemented (one’s complement). All 1 bits are changed to 0 and all 0 bits are changed to 1.

Flags

C Unaffected Z Set if the result is zero; cleared otherwise S Set if Bit 7 of the result is set; cleared otherwise V Cleared to 0 D Unaffected H Unaffected

Instruction Format and Cycles

Opcode Operand Bytes Cycles Assembly Syntax (Hex) 1 2 3 Fetch Execute COM R1 60 R1 — — 6 5 COM @R1 61 R1 — — 6 5

Sample Usage

Example 1–If register 08h contains 24h (00100100b), the following statement leaves the value DBh (11011011b) in register 08h, sets the S flag, and clears the Z and V flags: COM 08h ;Object Code: 60 08

UM018304-0707 COM Instruction Z8 LXM CPU Core User Manual

Example 2–If register 08h contains the value 24h, and register 24h contains the value FFh (11111111b), the following statement leaves the value 00h (00000000b) in register 24h, sets the Z flag is set and clears the V and S flags: COM @08h ;Object Code: 61 08

UM018304-0707 COM Instruction Z8 LXM CPU Core User Manual

CP Compare CP dst, src Operation dst – src

Description The source operand is compared to (subtracted from) the destination operand and the flags are set according to the results of the operation. The contents of both the source and destination operands are unaffected.

Flags

C Set if a borrow is required by bit 7; cleared otherwise Z Set if the result is zero; cleared otherwise S Set if bit 7 of the result is set; cleared otherwise V Set if an arithmetic overflow occurs; cleared otherwise D Unaffected H Unaffected

Instruction Format and Cycles

Opcode Operand Bytes Cycles Assembly Syntax (Hex) 1 2 3 Fetch Execute CP r1, r2 A2 {r1, r2} — — 6 5 CP r1, @r2 A3 {r1, r2} — — 6 5 CP R1, R2 A4 R2 R1 — 10 5 CP R1, @R2 A5 R2 R1 — 10 5 CP R1, IM A6 R1 IM — 10 5 CP @R1, IM A7 R1 IM — 10 5

UM018304-0707 CP Instruction Z8 LXM CPU Core User Manual

Sample Usage

Example 1–If working register R3 contains the value 16h and working register R11 contains the value 20h, the following statement sets the C and S flags, and clears the Z and V flags: CP R3, R11 ;Object Code: A2 3B

Example 2–If working register R15 contains the value 16h, working register R10 contains the value 20h, and register 20h contains 11h, the following statement clears the C, Z, S, and V flags: CP R15, @R10 ;Object Code: A3 FA

Example 3–If register 34h contains the value 2Eh and register 12h contains the value 1bh, the following statement clears the C, Z, S, and V flags: CP 34h,12h ;Object Code: A4 12 34

Example 4–Using escaped mode, if register 4Bh contains the value 82h, working register R3 contains the value 10h, and register 10h contains the value 01h, the following statement sets the S flag, and clears the C, Z, and V flags: CP 4Bh, @E3h ;Object Code: A5 E3 4B

Example 5–If register 6Ch contains the value 2Ah, the following statement sets the Z flag, and clears the C, S, and V flags: CP 6Ch, #2Ah ;Object Code: A6 6C 2A

Example 6–If register D4h contains the value FCh, and register FCh contains the value 8Fh, the following statement sets the V flag, and clears the C, Z, and S flags: CP @D4h, #FFh ;Object Code: A7 D4 FF

UM018304-0707 CP Instruction Z8 LXM CPU Core User Manual

DA Decimal Adjust DA dst Operation dst ← decimal_adjust(dst)

Description The destination operand is adjusted to form two 4-bit BCD digits following a binary addition or subtraction operation on BCD encoded bytes. For addition (ADD and ADC) or subtraction (SUB and SBC), Table 28 indicates the operation performed. If the destination operand is not the result of a valid addition or subtraction of BCD digits, the operation is undefined.

Table 28. Operation of the DA Instruction

Bits 7–4 Bits 3–0 Number Carry H Flag Value Value Added To Carry Instruction Before DA Before DA (Hex) (Hex) Byte After DA ADD\ADC 0 0 0-9 0-9 00 0 0 0 0-8 A-F 06 0 0 1 0-9 0-3 06 0 00A-F0-9601 009-FA-F661 01A-F0-3661 1 0 0-2 0-9 60 1 1 0 0-2 A-F 66 1 1 1 0-3 0-3 66 1 SUB\SBC 0 0 0-9 0-9 00 0 010-86-FFA0 107-F0-9A01 116-F6-F9A1

Flags

C Set if there is a carry from bit 7; cleared otherwise Z Set if the result is zero; cleared otherwise S Set if Bit 7 of the result is set; cleared otherwise V Undefined D Unaffected H Unaffected

UM018304-0707 DA Instruction Z8 LXM CPU Core User Manual

Instruction Format and Cycles

Opcode Operand Bytes Cycles Assembly Syntax (Hex) 1 2 3 Fetch Execute DA R1 40 R1 — — 8 5 DA @R1 41 R1 — — 8 5

Sample Usage

Example 1–If addition is performed using the BCD value 15 and 27, the result must be 42. The sum is incorrect, however, when the binary representations are added in the destination location using standard binary arithmetic.

0001 0101 = 15h 0010 0111 = 27h 0011 1100 = 3Ch

Example 2–If the result of the addition is stored in register 5Fh, the following statement adjusts this result to obtain the correct BCD representation. DA 5Fh ;Object Code: 40 5F

0011 1100 = 3Ch 0000 0110 = 06h 0100 0010 = 42h

UM018304-0707 DA Instruction Z8 LXM CPU Core User Manual

DEC Decrement DEC dst Operation dst ← dst – 1

Description The contents of the destination operand are decremented by one. Flags

C Unaffected Z Set if the result is zero; cleared otherwise S Set if bit 7 of the result is set; cleared otherwise V Set if an arithmetic overflow occurs; cleared otherwise D Unaffected H Unaffected

Instruction Format and Cycles

Opcode Operand Bytes Cycles Assembly Syntax (Hex) 1 2 3 Fetch Execute DEC R1 00 R1 — — 6 5 DEC @R1 01 R1 — — 6 5

Escaped Mode Addressing For a register or indirect register operand, an 8-bit address in the range E0h to EFh always addresses the current working register group. For example, if register address ECh is specified, working register R12 (Ch) is addressed instead. To access registers E0h to EFh, either set the Working Group Pointer, RP[7:4] to Eh, or use indirect addressing. Sample Usage Example 1–If working register R10 contains 2Ah, the following statement leaves the value 29h in working register R10 and clears the Z, V, and S flags: DEC R10 ;Object Code: 30 EA Example 2–If register B3h contains CBh, and register CBh contains 01h, the following statement leaves the value 00h in register CBh, sets the Z flag, and clears the V and S flags: DEC @B3h ;Object Code: 31 B3

UM018304-0707 DEC Instruction Z8 LXM CPU Core User Manual

DECW Decrement Word DECW dst Operation dst ← dst – 1

Description The 16-bit register-pair value addressed by the destination operand is decremented by one. For a register pair operand (RR1), the operand value must be even. For an indirect register operand (@R1), the operand value is either even or odd, but the indirect register must contain an even effective address (bit 0 of the effective address is ignored).

Flags

C Unaffected Z Set if the result is zero; cleared otherwise S Set if bit 7 of the result is set; cleared otherwise V Set if an arithmetic overflow occurs; cleared otherwise D Unaffected H Unaffected

Instruction Format and Cycles

Opcode Operand Bytes Cycles Assembly Syntax (Hex) 1 2 3 Fetch Execute DECW RR1 80 RR1 — — 10 5 DECW @R1 81 R1 — — 10 5

Escaped Mode Addressing For a register pair (RR1) or indirect register (@R1) operand, an 8-bit address in the range E0h to EFh always addresses the current working register group. For example, if register address ECh is specified, working register or working register pair R12 (Ch) is addressed instead. To access registers E0h to EFh, either set the Working Group Pointer, RP[7:4] to Eh, or use indirect addressing.

UM018304-0707 DECW Instruction Z8 LXM CPU Core User Manual

Sample Usage

Example 1–If register pair 30h and 31h contain the value 0AF2h, the following statement leaves the value 0AF1h in register pair 30h and 31h and clears the Z, V, and S flags: DECW 30h ;Object Code: 80 30

Example 2–Using escaped mode, if working register R0 contains 30h and register pair 30h and 31h contain the value FAF3h, the following statement leaves the value FAF2h in register pair 30h and 31h, sets the S flag, and clears the Z and V flags: DECW @E0h ;Object Code: 81 E0

UM018304-0707 DECW Instruction Z8 LXM CPU Core User Manual

DI Disable Interrupts DI Operation IMR[7] ← 0

Description Bit 7 of the Interrupt Mask register, FBh, is cleared to 0. This disables the Interrupt Controller globally, regardless of the state of individual interrupt level enable bits.

Flags

C Unaffected Z Unaffected S Unaffected V Unaffected D Unaffected H Unaffected

Instruction Format and Cycles

Opcode Operand Bytes Cycles Assembly Syntax (Hex) 1 2 3 Fetch Execute DI 8F — — — 6 1

Sample Usage

Example 1–If bit 7 is set in the IMR (Interrupt Mask register, FBh), interrupts are controlled by their individual enable bits. The following instruction clears IMR[7] and globally disables interrupts. DI ;Object Code: 8Fh

UM018304-0707 DI Instruction Z8 LXM CPU Core User Manual

DJNZ Decrement and Jump if Non-Zero DJNZ dst, DA Operation dst ← dst – 1 if dst ≠ 0 { PC ← PC + X }

where the jump offset, X, is calculated by the Z8 LXM CPU assembler from the Program Counter (PC) value and the destination address (DA). In assembly language, DA is specified by a label.

Description The destination working register is decremented. If the contents of the working register are not zero after being decremented, then the offset X is added to the Program Counter and control passes to the statement whose address is now in the Program Counter. The range of the offset is +127 to –128. The original value of the Program Counter is the address of the instruction byte following the DJNZ statement. When the specified working register counter reaches zero, control falls through to the statement following the DJNZ instruction. The pipeline is cleared when a DJNZ jump is taken. for more information, see Instruction Cycle Time on page 2. Note: The destination working register must be a general-purpose register. The result of using an I/O port, control, or peripheral register for the counter is undefined.

Flags

C Unaffected Z Unaffected S Unaffected V Unaffected D Unaffected H Unaffected

UM018304-0707 DJNZ Instruction Z8 LXM CPU Core User Manual

Instruction Format and Cycles

Opcode Operand Bytes Cycles Assembly Syntax (Hex) 1 2 3 Fetch Execute DJNZ r1, DA {r1, A} X — — NZ/Z: 12/10 5

Sample Usage DJNZ controls a loop of instructions. In this example, 18 bytes are moved from one buffer area in the Register File to another. The steps involved are: 1. Load the R6 counter with 18d (12h). 2. Load the R4 source pointer. 3. Load the R2 destination pointer. 4. Set up the loop to perform moves. 5. End loop with DJNZ.

The assembly listing required for this routine is as follows:

Ld R6, #12h ;Load counter with 12h (18d) Ld R4, #36h ;Load source pointer Ld R2, #24h ;Load destination pointer LOOP: Ld R3, @R4 ;Load byte in R3 from source Ld @R2, R3 ;Write byte to destination dec R4 ;Decrement source pointer dec R2 ;Decrement destination pointer djnz R6, loop ;Decrement and loop until count = 0

UM018304-0707 DJNZ Instruction Z8 LXM CPU Core User Manual

EI Enable Interrupts EI Operation IMR[7] ← 1

Description Bit 7 of the Interrupt Mask register is set to 1. This enables the Interrupt Controller.

Flags

C Unaffected Z Unaffected S Unaffected V Unaffected D Unaffected H Unaffected

Instruction Format and Cycles

Opcode Operand Bytes Cycles Assembly Syntax (Hex) 1 2 3 Fetch Execute EI 9F — — — 6 1

Sample Usage

Example 1–If bit 7 is clear in the IMR (Interrupt Mask register, FBh), interrupts are globally disabled. The following instruction sets IMR[7] and allows interrupts to be controlled by their individual enable bits. EI ;Object Code: 9Fh

UM018304-0707 EI Instruction Z8 LXM CPU Core User Manual

HALT Halt mode HALT Operation HALT mode

Description The HALT instruction places the Z8 LXM CPU into HALT mode. For more information on HALT mode operation, refer to Zilog® Product Specification that is specific to your Z8 Encore!® device. Note: Always execute a NOP instruction immediately before HALT. This flushes the pipeline to ensure the previous instruction completes before HALT mode is entered.

Flags

C Unaffected Z Unaffected S Unaffected V Unaffected D Unaffected H Unaffected

Instruction Format and Cycles

Opcode Operand Bytes Cycles Assembly Syntax (Hex) 1 2 3 Fetch Execute HALT 7F — — — 6 0

Sample Usage

Example 1–The following statements flush the pipeline and place the Z8 LXM CPU in HALT mode. NOP ;Object Code: FF HALT ;Object Code: 7F

UM018304-0707 HALT Instruction Z8 LXM CPU Core User Manual

INC Increment INC dst Operation dst ← dst + 1

Description The contents of the destination operand are incremented by one.

Flags

C Unaffected Z Set if the result is zero; cleared otherwise S Set if Bit 7 of the result is set; cleared otherwise V Set if an arithmetic overflow occurs; cleared otherwise D Unaffected H Unaffected

Instruction Format and Cycles

Opcode Operand Bytes Cycles Assembly Syntax (Hex) 1 2 3 Fetch Execute INC r1 {r1, E} — — — 6 5 INC R1 20 R1 — — 6 5 INC @R1 21 R1 — — 6 5

Sample Usage

Example 1–If working register R10 contains the value 2Ah, the following statement leaves the value 2Bh in working register R10 and clears the Z, V, and S flags: INC R10 ;Object Code: AE

UM018304-0707 INC Instruction Z8 LXM CPU Core User Manual

Example 2–If register B3h contains the value CBh, the following statement leaves the value CCh in register CBh, sets the S flag, and clears the Z and V flags: INC B3h ;Object Code: 20 B3

Example 3–If register B3h contains CBh and register CBh contains FFh, the following statement leaves the value 00h in register CBh, sets the Z flag, and clears the V and S flags: INC @B3h ;Object Code: 21 B3

UM018304-0707 INC Instruction Z8 LXM CPU Core User Manual

INCW Increment Word INCW dst Operation dst ← dst + 1

Description The 16-bit register-pair value addressed by the destination operand increments by one. For a register pair operand (RR1), the operand value must be even. For an indirect register operand (@R1), the operand value can be even or odd, but the indirect register should contain an even effective address (bit 0 of the effective address is ignored).

Flags

C Unaffected Z Set if the result is zero; cleared otherwise S Set if Bit 7 of the result is set; cleared otherwise V Set if an arithmetic overflow occurs; cleared otherwise D Unaffected H Unaffected

Instruction Format and Cycles

Opcode Operand Bytes Cycles Assembly Syntax (Hex) 1 2 3 Fetch Execute INCW RR1 A0 RR1 — — 10 5 INCW @R1 A1 R1 — — 10 5

UM018304-0707 INCW Instruction Z8 LXM CPU Core User Manual

Sample Usage

Example 1–If register pair 30h and 31h contain the value 0AF2h, the following statement leaves the value 0AF3h in register pair 30h and 31h and clears the Z, V, and S flags: INCW 30h ;Object Code: A0 30

Example 2–Using escaped mode, if working register R0 contains 30h, and register pair 30h and 31h contain the value FAF3h, the following statement leaves the value FAF4h in register pair 30h and 31h, sets the S flag, and clears the Z and V flag. INCW @E0h ;Object Code: A1 E0

UM018304-0707 INCW Instruction Z8 LXM CPU Core User Manual

IRET Interrupt Return IRET Operation FLAGS ← @SP SP ← SP + 1 PC ← @SP SP ← SP + 2 IMR[7] ← 1

Description This instruction is issued at the end of an interrupt service routine. Execution of IRET restores the Flags register and the Program Counter, and enables the Interrupt Controller by setting bit 7 of the Interrupt Mask register to 1.

Flags

C Restored to original setting before the interrupt occurred Z Restored to original setting before the interrupt occurred S Restored to original setting before the interrupt occurred V Restored to original setting before the interrupt occurred D Restored to original setting before the interrupt occurred H Restored to original setting before the interrupt occurred

Instruction Format and Cycles

Opcode Operand Bytes Cycles Assembly Syntax (Hex) 1 2 3 Fetch Execute IRET BF — — — 16 0

Sample Usage

Example 1–If the Stack Pointer register, FFh, contains the value 45h, register 45h contains the value 00h, register 46h contains 6Fh, and register 47h contains E4h, the following statement restores the Flags register FCh with the value 00h, restores the PC with the value 6FE4h, reen- ables the interrupts, and sets the Stack Pointer to the value 48h. The next instruction to be executed is at 6FE4h. IRET ;Object Code: BF

UM018304-0707 IRET Instruction Z8 LXM CPU Core User Manual

JP Jump JP dst Operation PC ← dst

Description The unconditional jump replaces the contents of the Program Counter with the contents of the destination. Program control then passes to the instruction addressed by the Program Counter.

Flags

C Unaffected Z Unaffected S Unaffected V Unaffected D Unaffected H Unaffected

Instruction Format and Cycles

Opcode Operand Bytes Cycles Assembly Syntax (Hex) 1 2 3 Fetch Execute JP DA 8D DA[15:8] DA[7:0] — 12 0 JP IRR1 30 RR1 — — 8 0

Escaped Mode Addressing For an indirect register pair operand (IRR1), an 8-bit address in the range E0h to EFh always addresses the current working register group. For example, if register address ECh is specified, working register pair R12 (Ch) is addressed instead. To access register pairs E0h to EEh, set the Working Group Pointer, RP[7:4] to Eh.

Sample Usage

Example 1–If register pair B2 contains the value 3F45h, the following statement replaces the contents of the PC with the value 3F45h and transfers program control to that location. JP B2 ;Object Code: 30 B2

UM018304-0707 JP Instruction Z8 LXM CPU Core User Manual

JP cc Jump Conditionally JP cc, dst Operation if cc (condition code) is true (1){ PC ← dst }

Description A conditional jump transfers program control to the destination address if the condition specified by cc is true (T). If the condition is false (F), the instruction following the JP instruction is executed. For more information, see Condition Codes on page 41.

Flags

C Unaffected Z Unaffected S Unaffected V Unaffected D Unaffected H Unaffected

Instruction Format and Cycles

Opcode Operand Bytes Cycles Assembly Syntax (Hex)123FetchExecute JP F, DA 0D DA[15:8] DA[7:0] — 10 0 JP LT, DA 1D DA[15:8] DA[7:0] — T/F: 12/10 0 JP LE, DA 2D DA[15:8] DA[7:0] — T/F: 12/10 0 JP ULE, DA 3D DA[15:8] DA[7:0] — T/F: 12/10 0 JP OV, DA 4D DA[15:8] DA[7:0] — T/F: 12/10 0 JP MI, DA 5D DA[15:8] DA[7:0] — T/F: 12/10 0 JP Z, DA 6D DA[15:8] DA[7:0] — T/F: 12/10 0 JP C, DA 7D DA[15:8] DA[7:0] — T/F: 12/10 0 JP T, DA 8D DA[15:8] DA[7:0] — 12 0 JP GE, DA 9D DA[15:8] DA[7:0] — T/F: 12/10 0 JP GT, DA AD DA[15:8] DA[7:0] — T/F: 12/10 0

UM018304-0707 JP cc Instruction Z8 LXM CPU Core User Manual

Opcode Operand Bytes Cycles Assembly Syntax (Hex)123FetchExecute JP UGT, DA BD DA[15:8] DA[7:0] — T/F: 12/10 0 JP NOV, DA CD DA[15:8] DA[7:0] — T/F: 12/10 0 JP PL, DA DD DA[15:8] DA[7:0] — T/F: 12/10 0 JP NE, DA ED DA[15:8] DA[7:0] — T/F: 12/10 0 JP NC, DA FD DA[15:8] DA[7:0] — T/F: 12/10 0

Sample Usage

Example 1–If the Carry flag is set, the following statement replaces the contents of the Program Counter with the value 1520h and transfers program control to that location: JP C, 1520h ;Object Code: 7D 15 20 If the Carry flag was not set, control would have passed through to the statement following the JP instruction.

UM018304-0707 JP cc Instruction Z8 LXM CPU Core User Manual

JR Jump Relative JR DA Operation PC ← PC + X

where the jump offset, X, is calculated by the Z8 LXM CPU assembler from the Program Counter (PC) value and the Destination Address (DA). In assembly language, DA is specified by a label.

Description The offset X is added to the Program Counter and control passes to the instruction located at the address specified by the Program Counter. The range of the offset is +127 to –128 and the original value of the Program Counter is taken to be the address of the first instruction byte following the JR instruction.

Flags

C Unaffected Z Unaffected S Unaffected V Unaffected D Unaffected H Unaffected

Instruction Format and Cycles

Opcode Operand Bytes Cycles Assembly Syntax (Hex) 1 2 3 Fetch Execute JR DA 8B X — — 12 0

UM018304-0707 JR Instruction Z8 LXM CPU Core User Manual

JR cc Jump Relative Conditionally JR cc, DA Operation If cc (condition code) is true (1){ PC ← PC + X }

where the jump offset, X, is calculated by the Z8 LXM CPU assembler from the Program Counter (PC) value and the Destination Address (DA). In assembly language, DA is specified by a label.

Description If the condition specified by the cc is true, the offset X is added to the Program Counter and control passes to the instruction located at the address specified by the Program Counter. For more information on control code, see Condition Codes on page 41. Otherwise, the instruction following the JR instruction is executed. The range of the offset is +127 to –128 and the original value of the Program Counter is taken to be the address of the first instruction byte following the JR instruction.

Flags

C Unaffected Z Unaffected S Unaffected V Unaffected D Unaffected H Unaffected

Instruction Format and Cycles

Opcode Operand Bytes Cycles Assembly Syntax (Hex) 1 2 3 Fetch Execute JR F, DA 0B X — — 10 0 JR LT, DA 1B X — — T/F: 12/10 0 JR LE, DA 2B X — — T/F: 12/10 0 JR ULE, DA 3B X — — T/F: 12/10 0 JR OV, DA 4B X — — T/F: 12/10 0 JR MI, DA 5B X — — T/F: 12/10 0

UM018304-0707 JR cc Instruction Z8 LXM CPU Core User Manual

Opcode Operand Bytes Cycles Assembly Syntax (Hex) 1 2 3 Fetch Execute JR Z, DA 6B X — — T/F: 12/10 0 JR C, DA 7B X — — T/F: 12/10 0 JR T, DA 8B X — — 12 0 JR GE, DA 9B X — — T/F: 12/10 0 JR GT, DA AB X — — T/F: 12/10 0 JR UGT, DA BB X — — T/F: 12/10 0 JR NOV, DA CB X — — T/F: 12/10 0 JR PL, DA DB X — — T/F: 12/10 0 JR NE, DA EB X — — T/F: 12/10 0 JR NC, DA FB X — — T/F: 12/10 0

UM018304-0707 JR cc Instruction Z8 LXM CPU Core User Manual

LD Load LD dst, src Operation dst ← src

Description The contents of the source operand are loaded into the destination operand. The contents of the source operand are unaffected.

Flags

C Unaffected Z Unaffected S Unaffected V Unaffected D Unaffected H Unaffected

Instruction Format and Cycles

Opcode Operand Bytes Cycles Assembly Syntax (Hex) 1 2 3 Fetch Execute LD r1, R2 {r1, 8} R2 — — 6 5 LD R1, r2 {r2, 9} R1 — — 6 5 LD r1, IM {r1, C} IM — — 6 5 LD r1, @r2 E3 {r1, r2} — — 6 5 LD R1, R2 E4 R2 R1 — 10 5 LD R1, @R2 E5 R2 R1 — 10 5 LD R1, IM E6 R1 IM — 10 5 LD @R1, IM E7 R1 IM — 10 5 LD @r1, r2 F3 {r1, r2} — — 6 5 LD @R1, R2 F5 R2 R1 — 10 5 LD r1, X(r2) C7 {r1, r2} X — 10 5 LD X(r1), r2 D7 {r2, r1} X — 10 5

UM018304-0707 LD Instruction Z8 LXM CPU Core User Manual

Sample Usage

Example 1–The following statement loads the value 34h into working register R15. LD R15, #34h ;Object Code: FC 34

Example 2–If register 34h contains the value FCh, the following statement loads the value FCh into working register R14. LD R14, 34h ;Object Code: E4 34 EE The contents of register 34h are not affected.

Example 3–If working register R14 contains the value 45h, the following statement loads the value 45h into register 34h: LD 34h, R14 ;Object Code: E4 EE 34 The contents of working register R14 are not affected.

Example 4–If working register R12 contains the value 34h, and register 34h contains the value FFh, the following statement loads the value FFh into working register R13: LD R13, @R12 ;Object Code: E3 DC The contents of working register R12 and register R34 are not affected.

Example 5–If working register R13 contains the value 45h, and working register R12 contains the value 00h the following statement loads the value 00h into register 45h: LD @R13, R12 ;Object Code: F3 DC The contents of working register R12 and working register R13 are not affected.

Example 6–If register 45h contains the value CFh, the following statement loads the value CFh into register 34h: LD 34h, 45h ;Object Code: E4 45 34 The contents of register 45h are not affected.

Example 7–If register 45h contains the value CFh and register CFh contains the value FFh, the following statement loads the value FFh into register 34h: LD 34h, @45h ;Object Code: E5 45 34 The contents of register 45h and register CFh are not affected.

Example 8–The following statement loads the value A4h into register 34h. LD 34h, #A4h ;Object Code: E6 34 A4

UM018304-0707 LD Instruction Z8 LXM CPU Core User Manual

Example 9–If working register R14 contains the value 7Fh, the following statement loads the value FCh into register 7Fh. LD @R14, #FCh ;Object Code: E7 EE FC The contents of working register R14 are not affected.

Example 10–If register 34h contains the value CFh and register 45h contains the value FFh, the following statement loads the value FFh into register CFh: LD @34h, 45h ;Object Code: F5 45 34 The contents of register 34h and register 45h are not affected.

Example 11–If working register R0 contains the value 08h and register 2Ch (24h + 08h = 2Ch) contains the value 4Fh, the following statement loads working register R10 with the value 4Fh: LD R10, 24h(R0) ;Object Code: C7 A0 24

Example 12–The contents of working register R0 and register 2Ch are not affected. If working register R0 contains the value 0bh and working register R10 contains 83h the following statement loads the value 83h into register FBh (F0h + 0bh = FBh): LD F0h(R0), R10 ;Object Code: D7 A0 F0 The contents of working registers R0 and R10 are unaffected by the load.

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LDC Load Constant to/from Program/Constant Memory LDC dst, src Operation dst ← src

Description This instruction loads a byte constant from the current Program/Constant memory page into a working register or vice versa. The address in the Program/Constant memory page is specified by a working register pair. The contents of the source operand are unaffected. The current program/constant memory page is set in Program Memory Page Register, bits [6:0] (PMPR[6:0]). Bits not required to address the implemented pages are ignored. Page 0 is addressed if PMPR[6:0]=0; Page 1 is addressed if PMPR[6:0]=1.

Flags

C Unaffected Z Unaffected S Unaffected V Unaffected D Unaffected H Unaffected

Instruction Format and Cycles

Opcode Operand Bytes Cycles Assembly Syntax (Hex) 1 2 3 Fetch Execute LDC r1, @rr2 C2 {r1, rr2} — — 12 0 LDC @rr1, r2 D2 {r2, rr1} — — 12 0

Sample Usage

Example 1–If working register pair R6 and R7 contain the value 30A2h and program/constant memory location 30A2h contains the value 22h, the following statement loads the value 22h into working register R2: LDC R2, @RR6 ;Object Code: C2 26 The value of Program/Constant memory location 30A2h is unchanged by the load.

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Example 2–If working register R2 contains the value 22h, and working register pair R6 and R7 contains the value 10A2h, the following statement loads the value 22h into Program/Constant memory location 10A2h: LDC @RR6, R2 ;Object Code: D2 26 The value of working register R2 is unchanged by the load.

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LDCI Load Constant to/from Program/Constant Memory and Auto-Increment Addresses LDCI dst, src Operation dst ← src r ← r + 1 rr ← rr + 1

Description This instruction simplifies block transfers of data between the current Program/Constant memory page and the active register file bank. The address in the Program/Constant memory page is specified by a working register pair (rr1 or rr2), and the address of the register file location is specified by a working register (r1 or r2). The contents of the source location are loaded into the destination location. The addresses in both working registers then increment automatically. The contents of the source operand are unaffected. The current Program/Constant memory page is set in Program Memory Page Register, bits [6:0] (PMPR[6:0]). Bits not required to address the implemented pages are ignored. Page 0 is addressed if PMPR[6:0]=0; Page 1 is addressed if PMPR[6:0]=1. If the page toggle enable bit (TG, PMPR[7]) is clear and the address register pair increments past FFFFh, the next LDCI instruction accesses address 0000h of the current page. If PMPR[7] is set and the address register pair increments past FFFFh (to 0000h), the PMPR[6:0] value is incremented so the next LDCI instruction accesses the next higher Program/Constant memory page. If the next page is not implemented, the next access falls on Page 0.

Flags

C Unaffected Z Unaffected S Unaffected V Unaffected D Unaffected H Unaffected

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Instruction Format and Cycles

Opcode Operand Bytes Cycles Assembly Syntax (Hex)123FetchExecute LDCI @r1, @rr2 C3 {r1, rr2} – – 18 0 LDCI @rr1, @r2 D3 {r2, rr1} – – 18 0

Sample Usage

Example 1–If working register pair R6–R7 contains 30A2h, Program/Constant memory locations 30A2h and 30A3h contain 22h and BCh respectively, and working register R2 contains 20h, the following statement loads the value 22h into register 20h: LDCI @R2, @RR6 ;Object Code: C3 26 Working register pair RR6 increments to 30A3h and working register R2 increments to 21h. A second instruction loads the value BCh into register 21h, as follows: LDCI @R2, @RR6 ;Object Code: C3 26 Working register pair RR6 increments to 30A4h and working register R2 increments to 22h.

Example 2–If working register R2 contains 20h, register 20h contains 22h, register 21h contains BCh, and working register pair R6–R7 contains 30A2h, the following statement loads the value 22h into program/constant memory location 30A2h: LDCI @RR6, @R2 ;Object Code: D3 26 Working register R2 increments to 21h and working register pair R6–R7 increments to 30A3h. A second instruction loads the value BCh into Program/Constant memory location 30A3h: LDCI @RR6, @R2 ;Object Code: D3 26 Working register R2 increments to 22h and working register pair R6–R7 increments to 30A4h.

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LDX Load Data to/from Extended Register Space LDX dst, src Operation dst ← src Description This instruction loads a byte from a register in the extended register space into a current working register, or vice versa. The linear address in the extended space is specified by a working register pair. The contents of the source operand are unaffected. The linear address range is 000h to FFFh, but not all addresses are implemented, and some addresses are reserved or have read/write restrictions. For more information, see Register File. Flags

C Unaffected Z Unaffected S Unaffected V Unaffected D Unaffected H Unaffected

Instruction Format and Cycles

Opcode Operand Bytes Cycles Assembly Syntax (Hex) 1 2 3 Fetch Execute LDX r1, @rr2 82 {r1, rr2} — — 12 0 LDX @rr1, r2 92 {r2, rr1} — — 12 0

Sample Usage Example 1–If working register pair R6 and R7 contain the value 3A2h and extended register location 3A2h contains the value 22h, the following statement loads the value 22h into working register R2: LDX R2, @RR6 ;Object Code: 82 26 The value of extended register location 3A2h is unchanged by the load. Example 2–If working register pair R6 and R7 contain the value 34Ah and working register R2 contains the value 22h, the following statement loads the value 22h into extended register location 34Ah. LDX @RR6, R2 ;Object Code: 92 26

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LDXI Load Data to/from Extended Register Space and Auto-Increment Addresses LDXI dst, src Operation dst ← src r ← r + 1 rr ← rr + 1

Description This instruction simplifies block transfers of data between the extended register space and the currently selected bank. The linear address in the extended space is specified by a working register pair (rr1 or rr2), and the address in the current bank is specified by a working register (r1 or r2). The contents of the source location are loaded into the destination location. The addresses in both working registers then increment automatically. The contents of the source are unaffected. The linear address range is 000h to FFFh, but not all addresses are implemented, and some addresses are reserved or have read/write restrictions. For more information, see Register File on page 14. If the linear address working register pair increments past FFFh, the next LDXI access is at 000h.

Flags

C Unaffected Z Unaffected S Unaffected V Unaffected D Unaffected H Unaffected

Instruction Format and Cycles

Opcode Operand Bytes Cycles Assembly Syntax (Hex) 1 2 3 Fetch Execute LDXI @r1, @rr2 83 {r1, rr2} — — 18 0 LDXI @rr1, @r2 93 {r2, rr1} — — 18 0

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Sample Usage Example 1–If working register pair RR6 (R6 and R7) contains the value 34Ah, extended register location 34Ah and 34Bh contain the values ABh and C3h respectively, and working register R2 contains the value 22h, the following statement loads the value ABh into register 22h. LDXI @R2, @RR6 ;Object Code: 83 26 Working register pair RR6 increments to 34Bh and working register R2 increments to 23h. A second instruction loads the value C3h into register 23h: LDXI @R2, @RR6 ;Object Code: 83 26 Working register pair RR6 increments to 34Ch and working register R2 increments to 24h. Example 2–If working register R2 contains the value 22h, register 22h contains the value ABh, register 23h contains the value C3h, and working register pair R6 and R7 contains the value 34Ah, the following statement loads the value ABh into extended register location 34Ah: LDXI @RR6, @R2 ;Object Code: 93 26 Working register R2 increments to 23h and working register pair RR6 increments to 34Bh. A second instruction, LDXI @RR6, @R2 ;Object Code: 93 26 loads the value C3h into extended register location 34Bh. working register R2 increments to 24h and working register pair RR6 increments to 34Ch.

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NOP No Operation NOP Operation None.

Description No action is performed by this instruction. It is used as a cycle timing delay.

Flags

C Unaffected Z Unaffected S Unaffected V Unaffected D Unaffected H Unaffected

Instruction Format and Cycles

Opcode Operand Bytes Cycles Assembly Syntax (Hex) 1 2 3 Fetch Execute NOP FF — — — 6 0

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OR Logical OR OR dst, src Operation dst ← dst OR src

Description The source operand is logically ORed with the destination operand and the destination operand stores the result. The contents of the source operand are unaffected. An OR operation stores a 1 bit when either of the corresponding bits in the two operands is a 1. Otherwise, the OR operation stores a 0 bit. Table 29. summarizes the OR operation.

Table 29. Truth Table for OR

dst src dst Bit Bit Result 000 011 101 111

Flags

C Unaffected Z Set if the result is zero; cleared otherwise S Set if Bit 7 of the result is set; cleared otherwise V Cleared to 0 D Unaffected H Unaffected

Instruction Format and Cycles

Opcode Operand Bytes Cycles Assembly Syntax (Hex) 1 2 3 Fetch Execute OR r1, r2 42 {r1, r2} — — 6 5 OR r1, @r2 43 {r1, r2} — — 6 5 OR R1, R2 44 R2 R1 — 10 5

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Opcode Operand Bytes Cycles Assembly Syntax (Hex) 1 2 3 Fetch Execute OR R1, @R2 45 R2 R1 — 10 5 OR R1, IM 46 R1 IM — 10 5 OR @R1, IM 47 R1 IM — 10 5

Sample Usage Example 1–If working register R1 contains the value 38h (00111000b) and working register R14 contains the value 8Dh (10001101b), the following statement leaves the value BDh (10111101b) in working register R1, sets the S flag, and clears the Z and V flags: OR R1, R14 ;Object Code: 42 1E Example 2–If working register R4 contains the value F9h (11111001b), working register R13 contains 7Bh, and register 7Bh contains the value 6Ah (01101010b), the following statement leaves the value FBh (11111011b) in working register R4, sets the S flag, and clears the Z and V flags: OR R4, @R13 ;Object Code: 43 4D Example 3–If register 3Ah contains the value F5h (11110101b) and register 42h contains the value 0Ah (00001010b), the following statement leaves the value FFh (11111111b) in register 3Ah, sets the S flag, and clears the Z and V flags: OR 3Ah, 42h ;Object Code: 44 42 3A Example 4–Using escaped mode, if working register R5 contains 70h (01110000b), register 45h contains the value 3Ah, and register 3Ah contains the value 7Fh (01111111b), the following statement leaves the value 7Fh (01111111b) in working register R5 and clears the Z, V, and S flags: OR E5h, @45h ;Object Code: 45 45 E5 Example 5–If register 7Ah contains the value F7h (11110111b), the following statement leaves the value F7h (11110111b) in register 7Ah, sets the S flag, and clears the Z and V flags: OR 7Ah, #F0h ;Object Code: 46 7A F0 Example 6–Using escaped mode, if working register R3 contains the value 3Eh and register 3Eh contains the value 0Ch (00001100b), the following statement leaves the value 0Dh (00001101b) in register 3Eh and clears the Z, V, and S flags: OR @E3h, #05h ;Object Code: 47 E3 05

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POP POP POP dst Operation dst ← @SP SP ← SP + 1

Description The POP instruction loads the register value pointed to by the Stack Pointer into the destination register. Then the contents of the SP is incremented by one.

Flags

C Unaffected Z Unaffected S Unaffected V Unaffected D Unaffected H Unaffected

Instruction Format and Cycles

Opcode Operand Bytes Cycles Assembly Syntax (Hex) 1 2 3 Fetch Execute POP R1 50 R1 — — 10 5 POP @R1 51 R1 — — 10 5

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Sample Usage Example 1–If the Stack Pointer (control register FFh) contains the value 70h and register 70h contains the value 44h, the following statement loads the value 44h into register 34h. After the POP operation, the Stack Pointer contains 71h: POP 34h ;Object Code: 50 34 The contents of register 70h are not affected. Example 2–Using escaped mode, if the Stack Pointer (control register FFh) contains the value 80h, register 80h contains the value 55h, and working register R6 contains the value 22h, the following statement loads the value 55h into register 22h: POP @E6h ;Object Code: 51 E6 After the POP operation, the Stack Pointer contains the value 81h. The contents of working register R6 are not affected.

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PUSH Push PUSH src Operation SP ← SP - 1 @SP ← src

Description The Stack Pointer contents decrement by one. Then the source operand contents are loaded into the register addressed by the decremented Stack Pointer, adding a new element to the stack.

Flags

C Unaffected Z Unaffected S Unaffected V Unaffected D Unaffected H Unaffected

Instruction Format and Cycles

Opcode Operand Bytes Cycles Assembly Syntax (Hex) 1 2 3 Fetch Execute PUSH R2 70 R2 — — 10 1 PUSH @R2 71 R2 — — 12 1

Sample Usage Example 1–If the Stack Pointer contains the value 20h, the following statement stores the contents of register FCh in register 1Fh: PUSH FCh ;Object Code: 70 FC

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After the PUSH operation, the Stack Pointer contains the value 1Fh. Example 2–Using escaped mode, if the Stack Pointer contains the value 61h and working register R4 contains FCh, the following statement stores the contents of register FCh in register 60h: PUSH @E4h ;Object Code: 71 E4 After the PUSH operation, the Stack Pointer contains the value 60h.

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RCF Reset Carry Flag RCF Operation C ← 0

Description The Carry (C) flag is cleared to 0, regardless of its previous value.

Flags

C Cleared to 0 Z Unaffected S Unaffected V Unaffected D Unaffected H Unaffected

Instruction Format and Cycles

Opcode Operand Bytes Cycles Assembly Syntax (Hex) 1 2 3 Fetch Execute RCF CF — — — 6 5

Sample Usage Example 1–If the Carry flag is currently set, the following statement clears the Carry flag to 0: RCF ;Object Code: CF

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RET Return RET Operation PC ← @SP SP ← SP + 2

Description This instruction returns from a procedure entered by a CALL instruction. The contents of the location addressed by the Stack Pointer are loaded into the Program Counter. The next statement executed is the one addressed by the new contents of the Program Counter. The Stack Pointer also increments by two.

Flags

C Unaffected Z Unaffected S Unaffected V Unaffected D Unaffected H Unaffected

Note: Any PUSH instruction executed within the subroutine must be countered with a POP instruction to guarantee the Stack Pointer is at the correct location when the RET instruction is executed. Otherwise, the wrong address loads into the Program Counter and the program cannot operate properly.

Instruction Format and Cycles

Opcode Operand Bytes Cycles Assembly Syntax (Hex)123FetchExecute RET AF———140

Sample Usage Example 1–If Stack Pointer contains the value A0h, register memory location A0h contains the value 30h and location A1h contains the value 15h, the following statement leaves the value A2h in the SP, and the PC contains the value 3015h, the address of the next instruction to be executed. RET ;Object Code: AF

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RL Rotate Left RL dst Operation

C D7 D6 D5 D4 D3 D2 D1 D0 dst

Description The destination operand contents rotate left by one bit position. The initial value of bit 7 is moved to the bit 0 position and also into the Carry (C) flag.

Flags

C Set if the bit rotated from the most-significant bit position was 1 (that is, bit 7 was 1) Z Set if the result is zero; cleared otherwise S Set if bit 7 of the result is set; cleared otherwise V Set if an arithmetic overflow occurred (if the sign of the destination operand changed during rotation); cleared otherwise D Unaffected H Unaffected

Instruction Format and Cycles

Opcode Operand Bytes Cycles Assembly Syntax (Hex) 1 2 3 Fetch Execute RL R1 90 R1 — — 6 5 RL @R1 91 R1 — — 6 5

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Sample Usage Example 1–If register C6h contains the value 88h (10001000b), the following statement leaves the value 11h (00010001b) in register C6h., sets the C and V flags and clears the S and Z flags: RL C6h ;Object Code: 90 C6 Example 2–If the contents of register C6h are 88h, and the contents of register 88h are 44h (01000100b), the following statement leaves the value 88h in register 88h (10001000b), sets the S and V flags and clears the C and Z flags: RL @C6h ;Object Code: 91 C6

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RLC Rotate Left through Carry RLC dst Operation

C D7 D6 D5 D4 D3 D2 D1 D0 dst

Description The destination operand contents along with the Carry (C) flag rotate left by one bit position. The initial value of bit 7 replaces the Carry flag, and the initial value of the Carry flag replaces bit 0.

Flags

Instruction Format and Cycles

Opcode Operand Bytes Cycles Assembly Syntax (Hex) 1 2 3 Fetch Execute RLC R1 10 R1 — — 6 5 RLC @R1 11 R1 — — 6 5

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working register R12 (Ch) is addressed instead. To access registers E0h to EFh, either set the Working Group Pointer, RP[7:4] to Eh, or use indirect addressing.

Sample Usage Example 1–If the Carry flag is clear and register C6h contains the value 8F (10001111b), the following statement leaves register C6h with the value 1Eh (00011110b), sets the C and V flags and clears S and Z flags: RLC C6 ;Object Code: 10 C6 Example 2–Using escaped mode, if the Carry flag is clear, working register R4 contains the value C6h, and register C6h contains the value 8F (10001111b), the following statement leaves register C6h with the value 1Eh (00011110b), sets the C and V flags and clears the S and Z flags: RLC @E4h ;Object Code: 11 E4

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RR Rotate Right RR dst Operation

D7 D6 D5 D4 D3 D2 D1 D0 C dst

Description The destination operand contents rotate to the right by one bit position. The initial value of bit 0 is moved to bit 7 and also into the Carry (C) flag.

Flags

C Set if the bit rotated from the least-significant bit position was 1 (that is., bit 0 was 1) Z Set if the result is zero; cleared otherwise S Set if bit 7 of the result is set; cleared otherwise V Set if an arithmetic overflow occurred (if the sign of the destination operand changed during rotation); cleared otherwise D Unaffected H Unaffected

Instruction Format and Cycles

Opcode Operand Bytes Cycles Assembly Syntax (Hex) 1 2 3 Fetch Execute RR R1 E0 R1 — — 6 5 RR @R1 E1 R1 — — 6 5

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Sample Usage Example 1–Using escaped mode, if working register R6 contains the value 31h (00110001b), the following statement leaves the value 98h (10011000b) in working register R6, sets the C, V, and S flags, and clears the Z flag. RR E6h ;Object Code: E0 E6 Example 2–If register C6h contains the value 31h and register 31h contains the value 7Eh (01111110b), the following statement leaves the value 3Fh (00111111b) in register 31h and clears the C, Z, V, and S flags: RR @C6h ;Object Code: E1 C6

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RRC Rotate Right through Carry RRC dst Operation

D7 D6 D5 D4 D3 D2 D1 D0 C dst

Description The destination operand contents along with the Carry (C) flag rotate right by one bit position. The initial value of bit 0 replaces the Carry flag, and the initial value of the Carry flag replaces bit 7.

Flags

C Set if the bit rotated from the least-significant bit position was 1 (that is, bit 0 was 1) Z Set if the result is zero; cleared otherwise S Set if bit 7 of the result is set; cleared otherwise V Set if an arithmetic overflow occurred (if the sign of the destination operand changed during rotation); cleared otherwise D Unaffected H Unaffected

Instruction Format and Cycles

Opcode Operand Bytes Cycles Assembly Syntax (Hex) 1 2 3 Fetch Execute RRC R1 C0 R1 — — 6 5 RRC @R1 C1 R1 — — 6 5

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working register R12 (Ch) is addressed instead. To access registers E0h to EFh, either set the Working Group Pointer, RP[7:4] to Eh, or use indirect addressing.

Sample Usage Example 1–If register C6h contains the value DDh (11011101b) and the Carry flag is clear, the following statement leaves the value 6Eh (01101110b) in register C6h, sets the C and V flags and clears the Z and S flags: RRC C6h ;Object Code: C0 C6 Example 2–If register 2Ch contains the value EDh, register EDh contains the value 00h (00000000b) and the Carry flag is clear, the following statement leaves the value 00h (00000000b) in register EDh and clears the C, Z, S, and V flags: RRC @2Ch ;Object Code: C1 2C

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SBC Subtract with Carry SBC dst, src Operation dst ← dst - src - C

Description This instruction subtracts the source operand and the Carry (C) flag from the destination. The destination stores the result. The contents of the source operand are unaffected. The Z8 LXM CPU performs subtraction by adding the two’s-complement of the source operand to the destination operand. In multiple-precision arithmetic, this instruction permits the carry (borrow) from the subtraction of low-order operands to be subtracted from the subtraction of high-order operands.

Flags

C Set if a borrow is required by bit 7; cleared otherwise Z Set if the result is zero; cleared otherwise S Set if Bit 7 of the result is set; cleared otherwise V Set if an arithmetic overflow occurs; cleared otherwise D Set to 1 H Set if a borrow is required by bit 3; cleared otherwise

Instruction Format and Cycles

Opcode Operand Bytes Cycles Assembly Syntax (Hex) 1 2 3 Fetch Execute SBC r1, r2 32 {r1, r2} — — 6 5 SBC r1, @r2 33 {r1, r2} — — 6 5 SBC R1, R2 34 R2 R1 — 10 5 SBC R1, @R2 35 R2 R1 — 10 5 SBC R1, IM 36 R1 IM — 10 5 SBC @R1, IM 37 R1 IM — 10 5

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Sample Usage Example 1–If working register R3 contains the value 16h, the Carry flag is 1, and working register R11 contains the value 20h, the following statement leaves the value F5h in working register R3, sets the C, S, and D flags and clears the Z, V, and H flags: SBC R3, R11 ;Object Code: 32 3B Example 2–If working register R15 contains the value 16h, the Carry flag is not set, working register R10 contains the value 20h, and register 20h contains the value 11h, the following statement leaves the value 05h in working register R15, sets the D flag, and clears the C, Z, S, V, and H flags: SBC R15, @R10 ;Object Code: 33 FA Example 3–If register 34h contains the value 2Eh, the Carry flag is set, and register 12h contains the value 1bh, the following statement leaves the value 12h in register 34h, sets the D flag, and clears the C, Z, S, V, and H flags: SBC 34h, 12h ;Object Code: 34 12 34 Example 4–Using escaped mode, if register 4Bh contains the value 82h, the Carry flag is set, working register R3 contains the value 10h, and register 10h contains the value 01h, the following statement leaves the value 80h in register 4Bh, sets the D and S flags and clears the C, Z, V, and H flags: SBC 4Bh, @E3h ;Object Code: 35 E3 4B Example 5–If register 6Ch contains the value 2Ah, and the Carry flag is not set, the following statement leaves the value 27h in register 6Ch, sets the D flag, and clears the C, Z, S, V, and H flags: SBC 6Ch, #03h ;Object Code: 36 6C 03 Example 6–If register D4h contains the value 5Fh, register 5Fh contains the value 4Ch, and the Carry flag is set, the following statement leaves the value 49h in register 5Fh, sets the D flag, and clears the C, Z, S, V, and H flags: SBC @D4h, #02h ;Object Code: 37 D4 02

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SCF Set Carry Flag SCF Operation C ← 1

Description The Carry (C) flag is 1, regardless of its previous value.

Flags

C Set to 1 Z Unaffected S Unaffected V Unaffected D Unaffected H Unaffected

Instruction Format and Cycles

Opcode Operand Bytes Cycles Assembly Syntax (Hex) 1 2 3 Fetch Execute SCF DF — — — 6 5

Sample Usage Example 1–If the Carry flag is currently cleared, the following statement sets the Carry flag to 1: SCF ;Object Code: DF

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SRA Shift Right Arithmetic SRA dst Operation

D7 D6 D5 D4 D3 D2 D1 D0 C dst

Description This instruction performs an arithmetic shift to the right by one bit position on the destination operand. Bit 0 replaces the Carry (C) flag. The value of bit 7 (the Sign bit) does not change, but its value shifts into bit 6.

Flags

C Set if the bit shifted from the least-significant bit position was 1 (that is, bit 0 was 1) Z Set if the result is zero; cleared otherwise S Set if bit 7 of the result is set; cleared otherwise V Cleared to 0 D Unaffected H Unaffected

Instruction Format and Cycles

Opcode Operand Bytes Cycles Assembly Syntax (Hex) 1 2 3 Fetch Execute SRA R1 D0 R1 — — 6 5 SRA @R1 D1 R1 — — 6 5

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Sample Usage Example 1–Using escaped mode, if working register R6 contains the value 31h (00110001b), the following statement stores the value 18h (00011000b) in working register R6, sets the Carry flag, and clears the Z, V, and S flags: SRA E6h ;Object Code: D0 E6 Example 2–If register C6h contains the value DFh, and register DFh contains the value B8h (10111000b), the following statement stores the value DCh (11011100b) in register DFh, clears the C, Z and V flags and sets the S flag: SRA @C6h ;Object Code: D1 C6

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SRP Set Register Pointer SRP src Operation RP ← src

Description The immediate value loads into the Register Pointer (RP). RP[7:4] sets the current working register Group. RP[3:0] sets the current register bank.

Flags

C Unaffected Z Unaffected S Unaffected V Unaffected D Unaffected H Unaffected

Instruction Format and Cycles

Opcode Operand Bytes Cycles Assembly Syntax (Hex) 1 2 3 Fetch Execute SRP 31 IM — — 6 1

Sample Usage Example 1–The following statement sets the Register Pointer to access working register Group Fh and Bank 0h in the Register File. SRP F0h ;Object Code: 31 F0 All references to working registers now affect this group of 16 registers. Registers 0F0h to 0FFh can be accessed as working registers R0 to R15.

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STOP Stop Mode STOP Operation STOP mode

Description This instruction places the Z8 LXM CPU into STOP mode. For more information on STOP mode operation, refer to Zilog® Product Specification that is specific to your device. Note: Always execute a NOP instruction immediately before STOP. This flushes the pipeline to ensure the previous instruction completes before STOP mode is entered.

Flags

C Unaffected Z Unaffected S Unaffected V Unaffected D Unaffected H Unaffected

Instruction Format and Cycles

Opcode Operand Bytes Cycles Assembly Syntax (Hex) 1 2 3 Fetch Execute STOP 6F — — — 6 0

Sample Usage The following statements flush the pipeline and place the Z8 LXM CPU in STOP mode. NOP ;Object Code: FF STOP ;Object Code: 6F

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SUB Subtract SUB dst, src Operation dst ← dst - src

Description This instruction subtracts the source operand from the destination operand. The destination operand stores the result. The source operand contents are unaffected. The Z8 LXM CPU performs subtraction by adding the two’s complement of the source operand to the destination operand.

Flags

C Set if a borrow is required by bit 7; cleared otherwise Z Set if the result is zero; cleared otherwise S Set if the result is negative; cleared otherwise V Set if an arithmetic overflow occurs; cleared otherwise D Set to 1 H Set if a borrow is required by bit 3; cleared otherwise

Instruction Format and Cycles

Opcode Operand Bytes Cycles Assembly Syntax (Hex) 1 2 3 Fetch Execute SUB r1, r2 22 {r1, r2} — — 6 5 SUB r1, @r2 23 {r1, r2} — — 6 5 SUB R1, R2 24 R2 R1 — 10 5 SUB R1, @R2 25 R2 R1 — 10 5 SUB R1, IM 26 R1 IM — 10 5 SUB @R1, IM 27 R1 IM — 10 5

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Sample Usage Example 1–If working register R3 contains the value 16h, and working register R11 contains the value 20h, the following statement leaves the value F6h in working register R3, sets the C, S, and D flags and clears the Z, V, and H flags: SUB R3, R11 ;Object Code: 22 3B Example 2–If working register R15 contains the value 16h, working register R10 contains the value 20h, and register 20h contains the value 11h, the following statement leaves the value 05h in working register R15: SUB R15, @R10 ;Object Code: 23 FA The D flag is set, and the C, Z, S, V, and H flags are cleared. Example 3–If register 34h contains the value 2Eh, and register 12h contains the value 1bh, the following statement leaves the value 13h in register 34h, sets the D flag, and clears the C, Z, S, V, and H flags are cleared: SUB 34h, 12h ;Object Code: 24 12 34 Example 4–Using escaped mode, if register 4Bh contains the value 82h, working register R3 contains the value 10h, and register 10h contains the value 01h, the following statement leaves the value 81h in register 4Bh, sets the D and S flags and clears the C, Z, V, and H flags are cleared: SUB 4Bh, @E3h ;Object Code: 25 E3 4B Example 5–If register 6Ch contains the value 2Ah, the following statement leaves the value 27h in register 6Ch, sets the D flag, and clears the C, Z, S, V, and H flags are cleared: SUB 6Ch, #03h ;Object Code: 26 6C 03 Example 6–If register D4h contains the value 5Fh, register 5Fh contains the value 4Ch, the following statement leaves the value 4Ah in register 5Fh, sets the D flag, and clears the C, Z, S, V, and H flags: SUB @D4h, #02h ;Object Code: 27 D4 02

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SWAP Swap Nibbles SWAP dst Operation dst[7:4] ↔ dst[3:0]

Description This instruction swaps the contents of the upper nibble of the destination, dst[7:4], with the lower nibble of the destination, dst[3:0].

Flags

C Unaffected Z Set if the result is zero; cleared otherwise S Set if Bit 7 of the result is set; cleared otherwise V Undefined D Unaffected H Unaffected

Instruction Format and Cycles

Opcode Operand Bytes Cycles Assembly Syntax (Hex) 1 2 3 Fetch Execute SWAP R1 F0 R1 — — 6 5 SWAP @R1 F1 R1 — — 6 5

Sample Usage Example 1–If register BCh contains the value B3h (10110011b), the following statement leaves the value 3Bh (00111011b) in register BCh and clears the Z and S flags: SWAP BCh ;Object Code: F0 BC

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Example 2–Using escaped mode, if working register R5 contains the value BCh and register BCh contains the value B3h (10110011b), the following statement leaves the value 3Bh (00111011b) in register BCh and clears the Z and S flags: SWAP @E5h ;Object Code: F1 E5

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TCM Test Complement Under Mask TCM dst, src Operation (NOT dst) AND src

Description This instruction tests selected bits in the destination operand for a logical 1 value. Specify the bits to be tested by setting a 1 bit in the corresponding bit position in the source operand (the mask). The TCM instruction complements the destination operand and AND’s it with the source mask (operand). Check the Zero flag to determine the result. If the Z flag is set, the tested bits were 1. When a TCM operation is completed, the destination and source operands retain their original values.

Flags

C Unaffected Z Set if the result is zero; cleared otherwise S Set if Bit 7 of the result is set; cleared otherwise V Cleared to 0 D Unaffected H Unaffected

Instruction Format and Cycles

Opcode Operand Bytes Cycles Assembly Syntax (Hex) 1 2 3 Fetch Execute TCM r1, r2 62 {r1, r2} — — 6 5 TCM r1, @r2 63 {r1, r2} — — 6 5 TCM R1, R2 64 R2 R1 — 10 5 TCM R1, @R2 65 R2 R1 — 10 5 TCM R1, IM 66 R1 IM — 10 5 TCM @R1, IM 67 R1 IM — 10 5

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Sample Usage Example 1–If working register R3 contains the value 45h (01000101b) and working register R7 contains the value 01h (00000001b) (testing bit 0 if it is 1), the following statement sets the Z flag indicating bit 0 in the destination operand is 1 and clears the V and S flags: TCM R3, R7 ;Object Code: 62 37 Example 2–Using escaped mode, if working register R14 contains the value F3h (11110011b), working register R5 contains the value CBh, and register CBh contains the value 88h (10001000b; testing bits 7 and 3 if they are 1), the following statement clears the Z flag (because bit 3 in the destination operand is not a 1) and clears the V and S flags: TCM R14, @E5h ;Object Code: 63 E5 Example 3–Using escaped mode, if register D4h contains the value 04h (00000100b), and working register R0 contains the value 80h (10000000b) (testing bit 7 it is 1), the following statement clears the Z flag (because bit 7 in the destination operand is not a 1), sets the S flag, and clears the V flag: TCM D4h, E0h ;Object Code: 64 E0 D4 Example 4–If register DFh contains the value FFh (11111111b), register 07h contains the value 1Fh, and register 1Fh contains the value BDh (10111101b; testing bits 7, 5, 4, 3, 2, and bit 0 if they are 1), the following statement sets the Z flag (indicating the tested bits in the destination operand are 1) and clears the S and V flags: TCM DFh, @07h ;Object Code: 65 07 DF Example 5–If working register R13 contains the value F2h (11110010b), the following statement tests bit 1 of the destination operand for 1, sets the Z flag (indicating bit 1 in the destination operand was 1) and clears the S and V flags: TCM R13, #02h ;Object Code: 66 ED, 02 Example 6–If register 5Dh contains the value A0h, and register A0h contains the value 0Fh (00001111b), the following statement tests bit 4 of the register A0h for 1, clears the Z flag (indicating bit 4 in the destination operand was not 1), and clears the S and V flags: TCM @5D, #10h ;Object Code: 67 5D 10

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TM Test Under Mask TM dst, src Operation dst AND src

Description This instruction tests selected bits in the destination operand for a 0 logical value. Specify the bits to be tested by setting a 1 bit in the corresponding bit position in the source operand (the mask). The TM instruction AND’s the destination operand with the source operand (the mask). Check the Zero flag can to determine the result. If the Z flag is set, the tested bits are 0. When a TM operation is completed, the destination and source operands retain their original values.

Flags

C Unaffected Z Set if the result is zero; cleared otherwise S Set if Bit 7 of the result is set; cleared otherwise V Cleared to 0 D Unaffected H Unaffected

Instruction Format and Cycles

Opcode Operand Bytes Cycles Assembly Syntax (Hex) 1 2 3 Fetch Execute TM r1, r2 72 {r1, r2} — — 6 5 TM r1, @r2 73 {r1, r2} — — 6 5 TM R1, R2 74 R2 R1 — 10 5 TM R1, @R2 75 R2 R1 — 10 5 TM R1, IM 76 R1 IM — 10 5 TM @R1, IM 77 R1 IM — 10 5

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working register R12 (Ch) is addressed instead. To access registers E0h to EFh, either set the Working Group Pointer, RP[7:4] to Eh, or use indirect addressing.

Sample Usage Example 1–If working register R3 contains the value 45h (01000101b) and working register R7 contains the value 02h (00000010b) (testing bit 1 if it is 0), the following statement sets the Z flag (indicating bit 1 in the destination operand is 0), and clears the V and S flags: TM R3, R7 ;Object Code: 72 37 Example 2–Using escaped mode, if working register R14 contains the value F3h (11110011b), working register R5 contains the value CBh, and register CBh contains the value 88h (10001000b) (testing bits 7 and 3 if they are 0), the following statement clears the Z flag (because bit 7 in the destination operand is not a 0), sets the S flag and clears the V flag: TM R14, @E5h ;Object Code: 73 E5 Example 3–Using escaped mode, if register D4h contains the value 08h (00001000b), and working register R0 contains the value 04h (00000100b) (testing bit 2 if it is 0), the following statement sets the Z flag (because bit 2 in the destination operand is a 0) and clears the S and V flags: TM D4h, E0h ;Object Code: 74 E0 D4 Example 4–If register DFh contains the value 00h (00000000b), register 07h contains the value 1Fh, and register 1Fh contains the value BDh (10111101b) (testing bits 7, 5, 4, 3, 2, and 0 if they are 0), the following statement sets the Z flag (indicating the tested bits in the destination operand are 0) and clears the S and V flags: TM DFh, @07h ;Object Code: 75 07 DF Example 5–If working register R13 contains the value F1h (11110001b), the following statement tests bit 1 of the destination operand for 0, sets the Z flag (indicating bit 1 in the destination operand is 0) and clears the S and V flags: TM R13, #02h ;Object Code: 76 ED, 02 Example 6–If register 5Dh contains the value A0h, and register A0h contains the value 0Fh (00001111b), the following statement tests bit 4 of register A0h for 0, sets the Z flag (indicating bit 4 in the destination operand was 0) and clears the S and V flags: TM @5D, #10h ;Object Code: 77 5D 10

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WDH Watchdog Timer Enable During Halt Mode WDH Operation None.

Description Enable the Watchdog Timer (WDT) during HALT mode. If this instruction is not executed, the WDT stops counting when HALT mode is entered. This instruction does not clear the WDT counter. A WDH instruction has no effect until after the WDT instruction is also executed. Note: The WDH instruction does not effect all Z8 LXM devices. For more information on control- ling WDT functions, refer to individual product specifications. The execution of WDH expenses instruction cycles, but has no effect in these devices.

Flags

C Unaffected Z Unaffected S Unaffected V Unaffected D Unaffected H Unaffected

Instruction Format and Cycles

Opcode Operand Bytes Cycles Assembly Syntax (Hex) 1 2 3 Fetch Execute WDH 4F — — — 6 0

Sample Usage Example 1–If WDT has been executed, the following statement enables the Watchdog Timer to count during HALT mode: WDH ;Object Code: 4F

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WDT Watchdog Timer Refresh WDT Operation None.

Description Enable the Watchdog Timer by executing the WDT instruction. Each subsequent execution of the WDT instruction refreshes the timer and prevents the Watchdog Timer from timing out. For more information about the Watchdog Timer, refer to relevant Product Specification for your part.

Flags

C Unaffected Z Unaffected S Unaffected V Unaffected D Unaffected H Unaffected

Instruction Format and Cycles

Opcode Operand Bytes Cycles Assembly Syntax (Hex) 1 2 3 Fetch Execute WDT 5F — — — 6 0

Sample Usage Example 1–The first execution of the following statement enables the Watchdog Timer: WDT ;Object Code: 5F If the Watchdog Timer is enabled, the following statement refreshes the Watchdog Timer: WDT ;Object Code: 5F

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XOR Logical Exclusive OR XOR dst, src Operation dst ← dst XOR src

Description The source operand is logically EXCLUSIVE ORed with the destination operand. An XOR operation stores a 1 in the destination operand when the corresponding bits in the two operands are different; otherwise XOR stores a 0. The contents of the source operand are unaffected. Table 30 summarizes the XOR operation.

Table 30. Truth Table for XOR

dst src dst Bit Bit Result 000 011 101 110

Flags

C Unaffected Z Set if the result is zero; cleared otherwise S Set if bit 7 of the result is set; cleared otherwise V Cleared to 0 D Unaffected H Unaffected

Instruction Format and Cycles

Opcode Operand Bytes Cycles Assembly Syntax (Hex)123FetchExecute XOR r1, r2 B2 {r1, r2} — — 6 5 XOR r1, @r2 B3 {r1, r2} — — 6 5 XOR R1, R2 B4 R2 R1 — 10 5

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Opcode Operand Bytes Cycles Assembly Syntax (Hex)123FetchExecute XOR R1, @R2 B5 R2 R1 — 10 5 XOR R1, IM B6 R1 IM — 10 5 XOR @R1, IM B7 R1 IM — 10 5

Sample Usage Example 1–If working register R1 contains the value 38h (00111000b) and working register R14 contains the value 8Dh (10001101b), the following statement leaves the value B5h (10110101b) in working register R1, sets the S flag, and clears the Z and V flags: XOR R1, R14 ;Object Code: B2 1E Example 2–If working register R4 contains the value F9h (11111001b), working register R13 contains the value 7Bh, and register 7Bh contains the value 6Ah (01101010b), the following statement leaves the value 93h (10010011b) in working register R4, sets the S flag, and clears the Z and V flags: XOR R4, @R13 ;Object Code: B3 4D Example 3–If register 3Ah contains the value F5h (11110101b) and register 42h contains the value 0Ah (00001010b), the following statement leaves the value FFh (11111111b) in register 3Ah, sets the S flag, and clears the Z and V flags: XOR 3Ah, 42h ;Object Code: B4 42 3A Example 4–Using escaped mode, if working register R5 contains the value F0h (11110000b), register 45h contains the value 3Ah, and register 3Ah contains the value 7Fh (01111111b), the following statement leaves the value 8Fh (10001111b) in working register R5, sets the S flag, and clears the C and V flags: XOR E5h, @45h ;Object Code: B5 45 E5 Example 5–If register 7Ah contains the value F7h (11110111b), the following statement leaves the value 07h (00000111b) in register 7Ah and clears the Z, V, and S flags: XOR 7Ah, #F0h ;Object Code: B6 7A F0 Example 6–Using escaped mode, if working register R3 contains the value 3Eh and register 3Eh contains the value 6Ch (01101100b), the following statement leaves the value 69h (01101001b) in register 3Eh and clears the Z, V, and S flags XOR @E3h, #05h ;Object Code: B7 E3 05

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Opcode Map

Figure 22 illustrates an example opcode map cell, and Table 31 lists the abbreviations used in the opcode map illustrated in Figure 23 on page 142.

Opcode Lower Nibble

Fetch Cycles Execute Cycles

10.5

Opcode Upper Nibble A CP

R2,R1

First Operand Second Operand After Assembly After Assembly Figure 22. Opcode Map Cell Description

Table 31. Opcode Map Abbreviations

Operand Abbreviation

Destination Source Description r1 r2 Working register 4-bit operand rr1 rr2 Working register pair 4-bit operand Ir1 Ir2 Indirect working register 4-bit operand Irr1 Ir2 Indirect working register pair 4-bit operand R1 R2 Register 8-bit operand RR1 RR2 Register pair 8-bit operand IR1 IR2 Indirect register 8-bit operand IRR1 IRR2 Indirect register pair 8-bit operand — IM Immediate data value 8- or 16-bit operand — cc Condition code 4-bit operand

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Table 31. Opcode Map Abbreviations (Continued)

Operand Abbreviation

Destination Source Description — X Index or offset 8-bit operand DA — Destination address (JP, CALL) 12-bit operand

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Lower Nibble (Hex) 0123456789ABCDEF

6.5 6.5 6.5 6.5 10.5 10.5 10.5 10.5 6.5 6.5 12/10.5 12/10.0 6.5 12/10.0 6.5 0 DEC DEC ADD ADD ADD ADD ADD ADD LD LD DJNZ JR LD JP INC R1 IR1 r1, r2 r1, Ir2 R2, R1 IR2, R1 R1, IM IR1, IM r1, R2 r2, R1 r1, X cc, X r1, IM cc, DA r1 6.5 6.5 6.5 6.5 10.5 10.5 10.5 10.5 1 RLC RLC ADC ADC ADC ADC ADC ADC R1 IR1 r1, r2 r1, Ir2 R2, R1 IR2, R1 R1, IM IR1, IM 6.5 6.5 6.5 6.5 10.5 10.5 10.5 10.5 2 INC INC SUB SUB SUB SUB SUB SUB R1 IR1 r1, r2 r1, Ir2 R2, R1 IR2, R1 R1, IM IR1, IM 8.0 6.1 6.5 6.5 10.5 10.5 10.5 10.5 3 JP SRP SBC SBC SBC SBC SBC SBC IRR1 IM r1, r2 r1, Ir2 R2, R1 IR2, R1 R1, IM IR1, IM 8.5 8.5 6.5 6.5 10.5 10.5 10.5 10.5 6.0 4 DA DA OR OR OR OR OR OR WDH R1 IR1 r1, r2 r1, Ir2 R2, R1 IR2, R1 R1, IM IR1, IM 10.5 10.5 6.5 6.5 10.5 10.5 10.5 10.5 6.0 5 POP POP AND AND AND AND AND AND WDT R1 IR1 r1, r2 r1, Ir2 R2, R1 IR2, R1 R1, IM IR1, IM 6.5 6.5 6.5 6.5 10.5 10.5 10.5 10.5 6.0 6 COM COM TCM TCM TCM TCM TCM TCM STOP R1 IR1 r1, r2 r1, Ir2 R2, R1 IR2, R1 R1, IM IR1, IM 10.1 12.1 6.5 6.5 10.5 10.5 10.5 10.5 7.0 7 PUSH PUSH TM TM TM TM TM TM HALT R2 IR2 r1, r2 r1, Ir2 R2, R1 IR2, R1 R1, IM IR1, IM 10.5 10.5 12.0 18.0 6.1 8 DECW DECW LDX LDXI DI RR1 IR1 r1, lrr2 lr1, lrr2 6.5 6.5 12.0 18.0 6.1 Upper Nibble (Hex) Nibble Upper 9 RL RL LDX LDXI EI R1 IR1 r2, lrr1 lr2, lrr1 10.5 10.5 6.5 6.5 10.5 10.5 10.5 10.5 14.0 A INCW INCW CP CP CP CP CP CP RET RR1 IR1 r1, r2 r1, Ir2 R2, R1 IR2, R1 R1, IM IR1, IM 6.5 6.5 6.5 6.5 10.5 10.5 10.5 10.5 16.0 B CLR CLR XOR XOR XOR XOR XOR XOR IRET R1 IR1 r1, r2 r1, Ir2 R2, R1 IR2, R1 R1, IM IR1, IM 6.5 6.5 12.0 18.0 10.5 6.5 C RRC RRC LDC LDCI LD RCF R1 IR1 r1, Irr2 Ir1, Irr2 r1,X,R2 6.5 6.5 12.0 18.0 20.0 20.0 10.5 6.5 D SRA SRA LDC LDCI CALL* CALL LD SCF R1 IR1 lrr1, r2 lrr1, Ir2 IRR1 DA r2,X,R1 6.5 6.5 6.5 10.5 10.5 10.5 10.5 6.5 E RR RR LD LD LD LD LD CCF R1 IR1 r1, IR2 R2, R1 IR2, R1 R1, IM IR1, IM 8.5 8.5 6.5 10.5 6.0 F SWAP SWAP LD LD NOP R1 IR1 Ir1, r2 R2, IR1

2 3231 Bytes Per Instruction*

*CALL IRR1 is an exception; it is a 2-byte instruction. Figure 23. Opcode Map

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Instructions Sorted By Opcode

Table 32 lists the Z8 LXM CPU instructions in opcode order. This table identifies the addressing modes employed by the instruction, the effect upon the Flags register, the number of CPU clock cycles required for the instruction fetch, and the number of CPU clock cycles required for the instruction execution.

Table 32. Z8 LXM CPU Instructions Sorted By Opcode

Address Mode Flags Cycles Opcode Assembly (Hex) Mnemonic dst srcSymbolic Operation C Z S V D H Fetch Execute 00 DEC dst R dst ← dst – 1 –***–– 6 5 01 IR 6 5 02 ADD dst, src r r dst ← dst + src ****0* 6 5 03 r Ir 6 5 04 R R 10 5 05 R IR 10 5 06 R IM 10 5 07 IR IM 10 5 08 LD dst, src r R dst ← src –––––– 6 5 09 R r 6 5 0A DJNZ dst, RA r dst ← dst – 1 –––––– NZ/Z if dst ≠ 0 12/10 5 PC ← PC + X 0B JR F, dst RA if cc is true –––––– T/F PC ← PC + X 12/10 0 0C LD dst, src r IM dst ← src –––––– 6 5 0D JP F, dst DA if cc is true –––––– T/F PC ← dst 12/10 0 0E INC dst r dst ← dst + 1 –***–– 6 5 10 RLC dst R ****–– 6 5 C D7 D6 D5 D4 D3 D2 D1 D0 11 IRdst 6 5

Flag States: * = State Depends on Result; – = No Change; X = Undefined; 0 = Cleared; 1 = Set

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Table 32. Z8 LXM CPU Instructions Sorted By Opcode (Continued)

Address Mode Flags Cycles Opcode Assembly (Hex) Mnemonic dst srcSymbolic Operation C Z S V D H Fetch Execute 12 ADC dst, src r r dst ← dst + src + C ****0* 6 5 13 r Ir 6 5 14 R R 10 5 15 R IR 10 5 16 R IM 10 5 17 IR IM 10 5 18 LD dst, src r R dst ← src –––––– 6 5 19 R r 6 5 1A DJNZ dst, RA r dst ← dst – 1 –––––– NZ/Z if dst ≠ 0 12/10 5 PC ← PC + X 1B JR LT, dst RA if cc is true –––––– T/F PC ← PC + X 12/10 0 1C LD dst, src r IM dst ← src –––––– 6 5 1D JP LT, dst DA if cc is true –––––– T/F PC ← dst 12/10 0 1E INC dst r dst ← dst + 1 –***–– 6 5 20 R 6 5 21 IR 6 5 22 SUB dst, src r r dst ← dst – src ****1* 6 5 23 r Ir 6 5 24 R R 10 5 25 R IR 10 5 26 R IM 10 5 27 IR IM 10 5 28 LD dst, src r R dst ← src –––––– 6 5 29 R r 6 5 Flag States: * = State Depends on Result; – = No Change; X = Undefined; 0 = Cleared; 1 = Set

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Table 32. Z8 LXM CPU Instructions Sorted By Opcode (Continued)

Address Mode Flags Cycles Opcode Assembly (Hex) Mnemonic dst srcSymbolic Operation C Z S V D H Fetch Execute 2A DJNZ dst, RA r dst ← dst – 1 –––––– NZ/Z if dst ≠ 0 12/10 5 PC ← PC + X 2B JR LE, dst RA if cc is true –––––– T/F PC ← PC + X 12/10 0 2C LD dst, src r IM dst ← src –––––– 6 5 2D JP LE, dst DA if cc is true –––––– T/F PC ← dst 12/10 0 2E INC dst r dst ← dst + 1 –***–– 6 5 30 JP dst IRR PC ← dst –––––– 8 0 31 SRP src IM RP ← src –––––– 6 1 32 SBC dst, src r r dst ← dst – src – C ****1* 6 5 33 r Ir 6 5 34 R R 10 5 35 R IR 10 5 36 R IM 10 5 37 IR IM 10 5 38 LD dst, src r R dst ← src –––––– 6 5 39 R r 6 5 3A DJNZ dst, RA r dst ← dst – 1 –––––– NZ/Z if dst ≠ 0 12/10 5 PC ← PC + X 3B JR ULE, dst RA if cc is true –––––– T/F PC ← PC + X 12/10 0 3C LD dst, src r IM dst ← src –––––– 6 5 3D JP ULE, dst DA if cc is true –––––– T/F PC ← dst 12/10 0 3E INC dst r dst ← dst + 1 –***–– 6 5 Flag States: * = State Depends on Result; – = No Change; X = Undefined; 0 = Cleared; 1 = Set

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Table 32. Z8 LXM CPU Instructions Sorted By Opcode (Continued)

Address Mode Flags Cycles Opcode Assembly (Hex) Mnemonic dst srcSymbolic Operation C Z S V D H Fetch Execute 40 DA dst R dst ← DA(dst) ***X–– 8 5 41 IR 8 5 42 OR dst, src r r dst ← dst OR src – * * 0 – – 6 5 43 r Ir 6 5 44 R R 10 5 45 R IR 10 5 46 R IM 10 5 47 IR IM 10 5 48 LD dst, src r R dst ← src –––––– 6 5 49 R r 6 5 4A DJNZ dst, RA r dst ← dst – 1 –––––– NZ/Z if dst ≠ 0 12/10 5 PC ← PC + X 4B JR OV, dst RA if cc is true –––––– T/F PC ← PC + X 12/10 0 4C LD dst, src r IM dst ← src –––––– 6 5 4D JP OV, dst DA if cc is true –––––– T/F PC ← dst 12/10 0 4E INC dst r dst ← dst + 1 –***–– 6 5 4F WDH –––––– 6 0 50 POP dst R dst ← @SP –––––– 10 5 SP ← SP + 1 51 IR 10 5 Flag States: * = State Depends on Result; – = No Change; X = Undefined; 0 = Cleared; 1 = Set

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Table 32. Z8 LXM CPU Instructions Sorted By Opcode (Continued)

Address Mode Flags Cycles Opcode Assembly (Hex) Mnemonic dst srcSymbolic Operation C Z S V D H Fetch Execute 52 AND dst, src r r dst ← dst AND src –* *0–– 6 5 53 r Ir 6 5 54 R R 10 5 55 R IR 10 5 56 R IM 10 5 57 IR IM 10 5 58 LD dst, src r R dst ← src –––––– 6 5 59 R r 6 5 5A DJNZ dst, RA r dst ← dst – 1 –––––– NZ/Z if dst ≠ 0 12/10 5 PC ← PC + X 5B JR MI, dst RA if cc is true –––––– T/F PC ← PC + X 12/10 0 5C LD dst, src r IM dst ← src –––––– 6 5 5D JP MI, dst DA if cc is true –––––– T/F PC ← dst 12/10 0 5E INC dst r dst ← dst + 1 –***–– 6 5 5F WDT –––––– 6 0 60 COM dst R dst ← ~dst –* *0–– 6 5 61 IR 6 5 62 TCM dst, src r r (NOT dst) AND src – * * 0 – – 6 5 63 r Ir 6 5 64 R R 10 5 65 R IR 10 5 66 R IM 10 5 67 IR IM 10 5 Flag States: * = State Depends on Result; – = No Change; X = Undefined; 0 = Cleared; 1 = Set

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Table 32. Z8 LXM CPU Instructions Sorted By Opcode (Continued)

Address Mode Flags Cycles Opcode Assembly (Hex) Mnemonic dst srcSymbolic Operation C Z S V D H Fetch Execute 68 LD dst, src r R dst ← src –––––– 6 5 69 R r 6 5 6A DJNZ dst, RA r dst ← dst – 1 –––––– NZ/Z if dst ≠ 0 12/10 5 PC ← PC + X 6B JR Z, dst RA if cc is true –––––– T/F PC ← PC + X 12/10 0 6C LD dst, src r IM dst ← src –––––– 6 5 6D JP Z, dst DA if cc is true –––––– T/F PC ← dst 12/10 0 6E INC dst r dst ← dst + 1 –***–– 6 5 6F STOP Stop Mode –––––– 6 0 70 PUSH src R SP ← SP – 1 –––––– 10 1 71 IR @SP ← src 12 1 72 TM dst, src r r dst AND src – * * 0 – – 6 5 73 r Ir dst AND src – * * 0 – – 6 5 74 R R dst AND src – * * 0 – – 10 5 75 R IR dst AND src – * * 0 – – 10 5 76 R IM dst AND src – * * 0 – – 10 5 77 IR IM dst AND src – * * 0 – – 10 5 78 LD dst, src r R dst ← src –––––– 6 5 79 R r 6 5 7A DJNZ dst, RA r dst ← dst – 1 –––––– NZ/Z if dst ≠ 0 12/10 5 PC ← PC + X 7B JR C, dst RA if cc is true –––––– T/F PC ← PC + X 12/10 0 7C LD dst, src r IM dst ← src –––––– 6 5 Flag States: * = State Depends on Result; – = No Change; X = Undefined; 0 = Cleared; 1 = Set

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Table 32. Z8 LXM CPU Instructions Sorted By Opcode (Continued)

Address Mode Flags Cycles Opcode Assembly (Hex) Mnemonic dst srcSymbolic Operation C Z S V D H Fetch Execute 7D JP C, dst DA if cc is true –––––– T/F PC ← dst 12/10 0 7E INC dst r dst ← dst + 1 –***–– 6 5 7F HALT Halt Mode –––––– 7 0 80 DECW dst RR dst ← dst – 1 – * * * – – 10 5 81 IR 10 5 82 LDX dst, src r Irr dst ← src –––––– 12 0 83 LDXI dst, src Ir Irr dst ← src –––––– 18 0 r ← r + 1 rr ← rr + 1 88 LD dst, src r R dst ← src –––––– 6 5 89 R r 6 5 8A DJNZ dst, RA r dst ← dst – 1 –––––– NZ/Z if dst ≠ 0 12/10 5 PC ← PC + X 8B JR T, dst RA if cc is true –––––– T/F PC ← PC + X 12/10 0 8B JR dst RA PC ← PC + X –––––– 12 0 8C LD dst, src r IM dst ← src –––––– 6 5 8D JP T, dst DA if cc is true –––––– T/F PC ← dst 12/10 0 8D JP dst DA PC ← dst –––––– 12 0 8E INC dst r dst ← dst + 1 –***–– 6 5 8F DI Disable Interrupts –––––– 6 1 IRQCTL[7] ← 0 90 RL dst R ****–– 6 5 C D7 D6 D5 D4 D3 D2 D1 D0 91 IRdst 6 5

92 LDX dst, src Irr r dst ← src –––––– 12 0 Flag States: * = State Depends on Result; – = No Change; X = Undefined; 0 = Cleared; 1 = Set

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Table 32. Z8 LXM CPU Instructions Sorted By Opcode (Continued)

Address Mode Flags Cycles Opcode Assembly (Hex) Mnemonic dst srcSymbolic Operation C Z S V D H Fetch Execute 93 LDXI dst, src Irr Ir dst ← src –––––– 18 0 r ← r + 1 rr ← rr + 1 98 LD dst, src r R dst ← src –––––– 6 5 99 R r 6 5 9A DJNZ dst, RA r dst ← dst – 1 –––––– NZ/Z if dst ≠ 0 12/10 5 PC ← PC + X 9B JR GE, dst RA if cc is true –––––– T/F PC ← PC + X 12/10 0 9C LD dst, src r IM dst ← src –––––– 6 5 9D JP GE, dst DA if cc is true –––––– T/F PC ← dst 12/10 0 9E INC dst r dst ← dst + 1 –***–– 6 5 9F EI Enable Interrupts –––––– 6 1 IRQCTL[7] ← 1 A0 INCW dst RR dst ← dst + 1 –***–– 10 5 A1 IR 10 5 A2 CP dst, src r r dst – src – C ****–– 6 5 A3 r Ir 6 5 A4 R R 10 5 A5 R IR 10 5 A6 R IM 10 5 A7 IR IM 10 5 A8 LD dst, src r R dst ← src –––––– 6 5 A9 R r 6 5 AA DJNZ dst, RA r dst ← dst – 1 –––––– NZ/Z if dst ≠ 0 12/10 5 PC ← PC + X Flag States: * = State Depends on Result; – = No Change; X = Undefined; 0 = Cleared; 1 = Set

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Table 32. Z8 LXM CPU Instructions Sorted By Opcode (Continued)

Address Mode Flags Cycles Opcode Assembly (Hex) Mnemonic dst srcSymbolic Operation C Z S V D H Fetch Execute AB JR GT, dst RA if cc is true –––––– T/F PC ← PC + X 12/10 0 AC LD dst, src r IM dst ← src –––––– 6 5 AD JP GT, dst DA if cc is true –––––– T/F PC ← dst 12/10 0 AE INC dst r dst ← dst + 1 –***–– 6 5 AF RET PC ← @SP –––––– 14 0 SP ← SP + 2 B0 CLR dst R dst ← 00h –––––– 6 5 B1 IR 6 5 B2 XOR dst, src r r dst ← dst XOR src –* *0–– 6 5 B3 r Ir 6 5 B4 R R 10 5 B5 R IR 10 5 B6 R IM 10 5 B7 IR IM 10 5 B8 LD dst, src r R dst ← src –––––– 6 5 B9 R r 6 5 BA DJNZ dst, RA r dst ← dst – 1 –––––– NZ/Z if dst ≠ 0 12/10 5 PC ← PC + X BB JR UGT, dst RA if cc is true –––––– T/F PC ← PC + X 12/10 0 BC LD dst, src r IM dst ← src –––––– 6 5 BD JP UGT, dst DA if cc is true –––––– T/F PC ← dst 12/10 0 BE INC dst r dst ← dst + 1 –***–– 6 5 Flag States: * = State Depends on Result; – = No Change; X = Undefined; 0 = Cleared; 1 = Set

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Table 32. Z8 LXM CPU Instructions Sorted By Opcode (Continued)

Address Mode Flags Cycles Opcode Assembly (Hex) Mnemonic dst srcSymbolic Operation C Z S V D H Fetch Execute BF IRET FLAGS ← @SP ****** 16 0 SP ← SP + 1 PC ← @SP SP ← SP + 2 IRQCTL[7] ← 1 C0 RRC dst R ****–– 6 5 D7 D6 D5 D4 D3 D2 D1 D0 C C1 IRdst 6 5

C2 LDC dst, src r Irr dst ← src –––––– 12 0 C3 LDCI dst, src Ir Irr dst ← src –––––– 18 0 r ← r + 1 rr ← rr + 1 C7 LD dst, src r X(r) dst ← src –––––– 10 5 C8 r R 6 5 C9 R r 6 5 CA DJNZ dst, RA r dst ← dst – 1 –––––– NZ/Z if dst ≠ 0 12/10 5 PC ← PC + X CB JR NOV, dst RA if cc is true –––––– T/F PC ← PC + X 12/10 0 CC LD dst, src r IM dst ← src –––––– 6 5 CD JP NOV, dst DA if cc is true –––––– T/F PC ← dst 12/10 0 CE INC dst r dst ← dst + 1 –***–– 6 5 CF RCF C ← 0 0––––– 6 5 D0 SRA dst R * * * 0 – – 6 5 D7 D6 D5 D4 D3 D2 D1 D0 C D1 IRdst 6 5

D2 LDC dst, src Irr r dst ← src –––––– 12 0 Flag States: * = State Depends on Result; – = No Change; X = Undefined; 0 = Cleared; 1 = Set

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Table 32. Z8 LXM CPU Instructions Sorted By Opcode (Continued)

Address Mode Flags Cycles Opcode Assembly (Hex) Mnemonic dst srcSymbolic Operation C Z S V D H Fetch Execute D3 LDCI dst, src Irr Ir dst ← src –––––– 18 0 r ← r + 1 rr ← rr + 1 D4 CALL dst IRR SP ← SP -2 –––––– 20 0 @SP ← PC D6 DA 20 0 PC ← dst D7 LD dst, src X(r) r dst ← src –––––– 10 5 D8 r R 6 5 D9 R r 6 5 DA DJNZ dst, RA r dst ← dst – 1 –––––– NZ/Z if dst ≠ 0 12/10 5 PC ← PC + X DB JR PL, dst RA if cc is true –––––– T/F PC ← PC + X 12/10 0 DC LD dst, src r IM dst ← src –––––– 6 5 DD JP PL, dst DA if cc is true –––––– T/F PC ← dst 12/10 0 DE INC dst r dst ← dst + 1 –***–– 6 5 DF SCF C ← 1 1––––– 6 5 E0 RR dst R ****–– 6 5 D7 D6 D5 D4 D3 D2 D1 D0 C E1 IRdst 6 5

E3 LD dst, src r Ir dst ← src –––––– 6 5 E4 R R 10 5 E5 R IR 10 5 E6 R IM 10 5 E7 IR IM 10 5 E8 r R 6 5 E9 R r 6 5 Flag States: * = State Depends on Result; – = No Change; X = Undefined; 0 = Cleared; 1 = Set

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Table 32. Z8 LXM CPU Instructions Sorted By Opcode (Continued)

Address Mode Flags Cycles Opcode Assembly (Hex) Mnemonic dst srcSymbolic Operation C Z S V D H Fetch Execute EA DJNZ dst, RA r dst ← dst – 1 –––––– NZ/Z if dst ≠ 0 12/10 5 PC ← PC + X EB JR NZ, dst RA if cc is true –––––– T/F PC ← PC + X 12/10 0 EC LD dst, src r IM dst ← src –––––– 6 5 ED JP NZ, dst DA if cc is true –––––– T/F PC ← dst 12/10 0 EE INC dst r dst ← dst + 1 –***–– 6 5 EF CCF C ← ~C *––––– 6 5 F0 SWAP dst R dst[7:4] ↔ dst[3:0] – * * X – – 8 5 F1 IR 8 5 F3 LD dst, src Ir r dst ← src –––––– 6 5 F5 IR R 10 5 F8 r R 6 5 F9 R r 6 5 FA DJNZ dst, RA r dst ← dst – 1 –––––– NZ/Z if dst ≠ 0 12/10 5 PC ← PC + X FB JR NC, dst RA if cc is true –––––– T/F PC ← PC + X 12/10 0 FC LD dst, src r IM dst ← src –––––– 6 5 FD JP NC, dst DA if cc is true –––––– T/F PC ← dst 12/10 0 FE INC dst r dst ← dst + 1 –***–– 6 5 FF NOP No operation –––––– 6 0 Flag States: * = State Depends on Result; – = No Change; X = Undefined; 0 = Cleared; 1 = Set

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Index

Numerics bit addressing 20 16-bit register pair 19 bit manipulation instruction class 48 4-bit register addressing 25 bit numbering ix 8-bit register addressing 25 bit range, convention ix block diagram 1 block transfer instruction class 48 A braces, convention x brackets, convention ix abbreviations, opcode map 140 byte ordering 20 active bank 14 ADC instruction 58 ADD instruction 60 add with carry instruction 58 C address space 14 CALL instruction 65 addressing carry flag 40 4-bit 25 caution symbol x 8-bit 25 CCF 67 bit 20 CCF instruction 67 direct 31 cell, opcode map 140 escaped mode 26, 27 clear instruction 68 immediate data 33 clear, meaning of x indexed 29 CLR instruction 68 indirect 27 COM instruction 69 mode 24 compare instruction 71 register 24 complement carry flag instruction 67 relative 31 complement instruction 69 summary 45 condition codes 41 working register 19 conditional jump 89, 92 working register examples 17 constant memory AND instruction 62 description 22 architecture, overview 1 indirect addressing 29 arithmetic instruction class 48 constant, load 97, 99 assembly language 43 control registers, CPU 20 audience viii control registers, description 3 control, program, instruction class 50 convention B bit numbering ix bit range ix bank braces x register 14 brackets ix setting 18 courier type ix

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hexadecimal ix F initial uppercase x fetch cycles 2 LSB, MSB, lsb, msb x fetch unit, CPU 2 manual ix flag set, reset, clear x carry 40 uppercase x decimal adjust 41 courier type, convention ix descriptions 39 CP instruction 71 half carry 41 CPU overflow 40 control instruction class 49 sign 40 control registers 20 zero 40 description 1 flags register execution unit 2 description 39 fetch unit 2 diagram 6 cycle time, instruction 2

G D general-purpose register 14 DA instruction 73 group, register 14 DEC instruction 75 group, setting 18 decimal adjust flag 41 decimal adjust instruction 73 decrement and jump instruction 79 H decrement instruction 75 half carry flag 41 decrement word instruction 76 HALT instruction 82 DECW instruction 76 halt mode, WDT enable 136 DI instruction 78 hexadecimal, convention ix direct addressing 31 history, revision iii disable interrupt 34 disable interrupts instruction 78 DJNZ instruction 79 I immediate data addressing 33 E IMR register 8 INC instruction 83 EI instruction 81 increment instruction 83 enable interrupt 34 increment word instruction 85 enable interrupts instruction 81 INCW instruction 85 escaped mode addressing 26, 27 indexed addressing 29 execute cycles 2 indirect addressing 27 execution unit, CPU 2 initial uppercase, convention x extended register space, load 101, 102 instruction cycle time 2 instruction notation 44 instructions

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by opcode 143 load constant and increment instruction 99 class 47 load constant instruction 97 description 57 load extended register space 101 sorted by opcode 143 load extended register space and increment 102 summary table 51 load instruction 94 interrupt load instruction class 49 description 34 logical instruction enable and disable 34 AND 62 latency 36 class 49 mask register 8 OR 105 nesting 37 XOR 138 polled 37 LSB and lsb convention x priority 34 priority register 9 request 8 M request register 8 map, opcodes 142 software 37 map, program/constant memory 23 vector 36 map, register file 15, 16, 18 vectored 34 mask register, interrupt 8 interrupt return instruction 87 mode, address 24 interrupt, stack effect 35 MSB and msb convention x IPR register 9 IRET instruction 87 IRQ register 8 N nesting interrupts 37 no operation instruction 104 J NOP instruction 104 JP cc instruction 89 notation, instruction 44 JP instruction 88 notation, symbolic 45 JR cc instruction 92 JR instruction 91 jump conditional 89, 92 O jump instruction 88 objectives, manual viii jump relative 91, 92 opcode map 142 opcode-sorted instructions 143 operand ordering 44 L operand, notation 45 latency, interrupt 36 OR instruction 105 LD instruction 94 ordering, bytes 20 LDC instruction 97 ordering, operands 44 LDCI instruction 99 organization, manual viii LDX and LDXI address map 18 overflow flag 40 LDX instruction 101 LDXI instruction 102

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P stack pointer 4 P01M register 10 user data 5 P2M register 12 register file P3M register 11 12-bit address map 18 pair, register 19 8-bit address map 16 pipeline cycles 2 address maps 15 PMPR register 12 description 14 pointer, register 5 indirect addressing 28 polled interrupt 37 relative addressing 31 POP instruction 107 relative jump 91, 92 port 0 mode register 10 request, interrupt 8 port 2 mode register 12 reserved registers and bits 3 port 3 mode register 11 reset carry flag instruction 111 priority, interrupt 9, 34 reset, meaning of x procedure call instruction 65 RET instruction 112 processor, description 1 return from interrupt 87 program control instruction class 50 return instruction 112 program counter 3 revision history iii program memory RL instruction 113 indirect addressing 29 RLC instruction 115 paging register 12 rotate and shift instruction class 50 program/constant memory 22 rotate left instruction 113 PUSH instruction 109 rotate left through carry instruction 115 rotate right instruction 117 rotate right through carry instruction 119 R RP register 5 RP register, setting 18 RCF instruction 111 RR instruction 117 register RRC instruction 119 4-bit addressing 25 8-bit addressing 25 addressing 24 bank 14 S general-purpose 14 safeguards x group 14 SBC instruction 121 group, setting 18 SCF instruction 123 interrupt priority 9 set carry flag instruction 123 interrupt request 8 set, meaning of x P01M 10 shift right arithmetic instruction 124 P2M 12 sign flag 40 P3M 11 software interrupts 37 pair 19 SPL register 4 pointer 5 SRA instruction 124 program memory paging 12 SRP instruction 126 RP, setting 18 stack

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and interrupts 35 USER register 5 description 21 pointer register diagram 4 STOP instruction 127 V stop mode instruction 127 vector, interrupt 36 SUB instruction 128 vectored interrupt processing 34 subtract instruction 128 subtract with carry instruction 121 SWAP instruction 130 W swap nibbles instruction 130 watch-dog timer enable during halt mode symbol definitions 46 instruction 136 symbolic notation 45 watch-dog timer refresh instruction 137 syntax, assembly language 44 WDH instruction 136 WDT instruction 137 working register T addressing 19 TCM instruction 132 examples 17 test complement under mask instruction 132 group 14 test under mask instruction 134 group, setting 18 time, instruction 2 TM instruction 134 truth table X AND 62 X in register tables 3 OR 105 XOR instruction 138 XOR 138

Z U zero flag 40 uppercase, convention x user data register 5

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