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Alpha 21264 Microprocessor Hardware Reference Manual

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Alpha 21264 Microprocessor Hardware Reference Manual Alpha 21264 Microprocessor Hardware Reference Manual Order Number: EC–RJRZA–TE This manual is directly derived from the internal 21264 Specifications, Revision 4.2. You can access this hardware reference manual in PDF format from the following website: ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html Revision/Update Information: This is a new document. Compaq Computer Corporation July 1999 The information in this publication is subject to change without notice. COMPAQ COMPUTER CORPORATION SHALL NOT BE LIABLE FOR TECHNICAL OR EDITORIAL ERRORS OR OMISSIONS CONTAINED HEREIN, NOR FOR INCIDENTAL OR CONSEQUENTIAL DAM- AGES RESULTING FROM THE FURNISHING, PERFORMANCE, OR USE OF THIS MATERIAL. THIS INFORMATION IS PROVIDED “AS IS” AND COMPAQ COMPUTER CORPORATION DISCLAIMS ANY WARRANTIES, EXPRESS, IMPLIED OR STATUTORY AND EXPRESSLY DISCLAIMS THE IMPLIED WAR- RANTIES OF MERCHANTABILITY, FITNESS FOR PARTICULAR PURPOSE, GOOD TITLE AND AGAINST INFRINGEMENT. This publication contains information protected by copyright. No part of this publication may be photocopied or reproduced in any form without prior written consent from Compaq Computer Corporation. © 1999 Digital Equipment Corporation. All rights reserved. Printed in the U.S.A. COMPAQ, the Compaq logo, the Digital logo, and VAX Registered in United States Patent and Trademark Office. Pentium is a registered trademark of Intel Corporation. Other product names mentioned herein may be trademarks and/or registered trademarks of their respective compa- nies. Alpha 21264 Hardware Reference Manual Table of Contents Preface 1 Introduction 1.1 The Architecture . 1–1 1.1.1 Addressing . 1–2 1.1.2 Integer Data Types. 1–2 1.1.3 Floating-Point Data Types . 1–2 1.2 21264 Microprocessor Features . 1–3 2 Internal Architecture 2.1 21264 Microarchitecture . 2–1 2.1.1 Instruction Fetch, Issue, and Retire Unit . 2–2 2.1.1.1 Virtual Program Counter Logic . 2–2 2.1.1.2 Branch Predictor . 2–3 2.1.1.3 Instruction-Stream Translation Buffer . 2–5 2.1.1.4 Instruction Fetch Logic . 2–5 2.1.1.5 Register Rename Maps . 2–6 2.1.1.6 Integer Issue Queue . 2–6 2.1.1.7 Floating-Point Issue Queue . 2–7 2.1.1.8 Exception and Interrupt Logic . 2–8 2.1.1.9 Retire Logic. 2–8 2.1.2 Integer Execution Unit . 2–8 2.1.3 Floating-Point Execution Unit. 2–10 2.1.4 External Cache and System Interface Unit . 2–11 2.1.4.1 Victim Address File and Victim Data File . 2–11 2.1.4.2 I/O Write Buffer . 2–11 2.1.4.3 Probe Queue. 2–11 2.1.4.4 Duplicate Dcache Tag Array . 2–11 2.1.5 Onchip Caches. 2–11 2.1.5.1 Instruction Cache . 2–11 2.1.5.2 Data Cache . 2–12 2.1.6 Memory Reference Unit . 2–12 2.1.6.1 Load Queue . 2–13 2.1.6.2 Store Queue . 2–13 2.1.6.3 Miss Address File . 2–13 2.1.6.4 Dstream Translation Buffer . 2–13 2.1.7 SROM Interface . 2–13 2.2 Pipeline Organization . 2–13 2.2.1 Pipeline Aborts . 2–16 2.3 Instruction Issue Rules . 2–16 Alpha 21264 Hardware Reference Manual iii 2.3.1 Instruction Group Definitions . 2–17 2.3.2 Ebox Slotting . 2–18 2.3.3 Instruction Latencies . 2–19 2.4 Instruction Retire Rules . 2–21 2.4.1 Floating-Point Divide/Square Root Early Retire . 2–21 2.5 Retire of Operate Instructions into R31/F31 . 2–22 2.6 Load Instructions to R31 and F31 . 2–22 2.6.1 Normal Prefetch: LDBU, LDF, LDG, LDL, LDT, LDWU Instructions . 2–22 2.6.2 Prefetch with Modify Intent: LDS Instruction . 2–22 2.6.3 Prefetch, Evict Next: LDQ Instruction. 2–23 2.7 Special Cases of Alpha Instruction Execution. 2–23 2.7.1 Load Hit Speculation . 2–23 2.7.2 Floating-Point Store Instructions . 2–25 2.7.3 CMOV Instruction. 2–25 2.8 Memory and I/O Address Space Instructions . 2–26 2.8.1 Memory Address Space Load Instructions . 2–26 2.8.2 I/O Address Space Load Instructions. 2–26 2.8.3 Memory Address Space Store Instructions . 2–27 2.8.4 I/O Address Space Store Instructions . 2–28 2.9 MAF Memory Address Space Merging Rules . 2–29 2.10 Instruction Ordering. 2–29 2.11 Replay Traps . 2–30 2.11.1 Mbox Order Traps . 2–30 2.11.1.1 Load-Load Order Trap . 2–30 2.11.1.2 Store-Load Order Trap . 2–30 2.11.2 Other Mbox Replay Traps . 2–31 2.12 I/O Write Buffer and the WMB Instruction . 2–31 2.12.1 Memory Barrier (MB/WMB/TB Fill Flow) . 2–31 2.12.1.1 MB Instruction Processing . 2–32 2.12.1.2 WMB Instruction Processing. 2–32 2.12.1.3 TB Fill Flow . ..
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