Wideband IQ Demodulator with IIP2 and DC Offset Control

LTC5585 Wideband IQ Demodulator with IIP2 and DC Offset Control FEATURES DESCRIPTION n 700MHz to 3GHz Operating Frequency The LTC®5585 is a direct conversion quadrature demodu- n High IIP3: 28.7dBm at 700MHz, 25.7dBm at 1.95GHz lator optimized for high linearity receiver applications in n High IIP2: 70dBm at 700MHz, 60dBm at 1.95GHz the 700MHz to 3GHz frequency range. It is also usable in n User Adjustable IIP2 Up to 80dBm the 400MHz to 700MHz and 3GHz to 4GHz ranges with n User Adjustable DC Offset Null reduced performance. It is suitable for communications n High Input P1dB: 16dBm at 1950MHz receivers where an RF signal is directly converted into I n I/Q Bandwidth of 530MHz or Higher and Q baseband signals with bandwidth of 530MHz or n Image Rejection: 43dB at 1950MHz higher. The LTC5585 incorporates balanced I and Q mix- n Noise Figure: 13.5dB at 700MHz ers, LO buffer amplifiers and a precision, high frequency 12.7dB at 1.95GHz quadrature phase shifter. The integrated on-chip broadband n Conversion Gain: 2.0dB at 700MHz transformer provides a single-ended interface at the RF 2.4dB at 1.95GHz input with simple off-chip L-C matching. In addition, the n Single-Ended RF with On-Chip Transformer LTC5585 provides four analog control voltage interface n Shutdown Mode pins for IIP2 and DC offset correction, greatly simplifying n Operating Temperature Range (TC): –40°C to 105°C system calibration. n 24-Lead 4mm × 4mm QFN Package The high linearity of the LTC5585 provides excellent spur- APPLICATIONS free dynamic range for the receiver. This direct conversion demodulator can eliminate the need for intermediate fre- n LTE/W-CDMA/TD-SCDMA Base Station Receivers quency (IF) signal processing, as well as the corresponding n Wideband DPD Receivers requirements for image filtering and IF filtering. These n Point-To-Point Broadband Radios I/Q outputs can interface directly to channel-select filters n High Linearity Direct Conversion I/Q Receivers (LPFs) or to baseband amplifiers. n Image Rejection Receivers L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.

TYPICAL APPLICATION Direct Conversion Receiver with IIP2 and DC Offset Calibration 5V BPF LNA BPF RF V CC + LPF VGA INPUT RF I IIP2 vs IP2I, IP2Q Trim Voltage I– A/D 120 I, –40°C Q, –40°C fRF = 700MHz I, 25°C Q, 25°C 110 I, 85°C Q, 85°C D/A IP2 ADJUST I, 105°C Q, 105°C IP2 AND DC 100 OFFSET CAL DC OFFSET 90 D/A LO 0° 80 LO INPUT LTC5585 90° IIP2 (dBm) 70 D/A DC OFFSET IP2 AND DC 60 OFFSET CAL IP2 ADJUST 50 D/A 40 LPF VGA 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Q+ ENABLE EN IP2I, IP2Q (V) – A/D Q 5585 G09

5585 TA01a 5585f 1 LTC5585 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Note 1) TOP VIEW VCC Supply Voltage...... –0.3V to 5.5V + – + – VCAP Voltage...... VCC ±0.05V REF I I Q Q CMI – + + – 24 23 22 21 20 19 I , I , Q , Q , CMI, CMQ Voltage...... 2.5V to VCC + 0.3V IP2Q 1 18 CMQ Voltage on Any Other Pin...... –0.3V to VCC + 0.3V + – DCOQ 2 17 VCAP LO , LO , RF Input Power...... 20dBm – DCOI 3 25 16 LO RF Input DC Voltage...... ±0.1V IP2I 4 GND 15 LO+ Maximum Junction Temperature (TJMAX)...... 150°C RF 5 14 GND Operating Temperature Range (TC)...... –40°C to 105°C GND 6 13 GND Storage Temperature Range...... –65°C to 150°C 7 8 9 10 11 12 CC EN V EDC BIAS GND EIP2 V UF PACKAGE 24-LEAD (4mm × 4mm) PLASTIC QFN TJMAX = 150°C, θJC = 7°C/W EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO PCB

ORDER INFORMATION

LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC5585IUF#PBF LTC5585IUF#TRPBF 5585 24-Lead (4mm x 4mm) Plastic QFN –40°C to 105°C Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

ELECTRICAL CHARACTERISTICS TC = 25°C, VCC = 5V, EN = 5V, EDC = EIP2 = 0V, REF = IP2I = IP2Q = DCOI = DCOQ = 0.5V, PRF = –5dBm (–5dBm/tone for 2-tone IIP2 and IIP3 tests), PLO = 6dBm, unless otherwise noted. (Notes 2, 3, 5, 6, 9) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS fRF(RANGE) RF Input Frequency Range (Note 12) 0.4 to 4.0 GHz fLO(RANGE) LO Input Frequency Range (Note 12) 0.4 to 4.0 GHz PLO(RANGE) LO Input Power Range (Note 12) 0 to 10 dBm fRF1 = 700MHz, fRF2 = 701MHz, fLO = 690MHz, L6 = 2.7pF, C19 = 1.0pF, L5 = 12nH, C14 = 5.6pF fRF(MATCH) RF Input Frequency Range Return Loss > 10dB 680 to 870 MHz fLO(MATCH) LO Input Frequency Range Return Loss > 10dB 690 to 820 MHz GV Voltage Conversion Gain Loaded with 100Ω Pull-Up (Note 8) 2.0 dB NF Noise Figure Double-Side Band (Note 4) 13.5 dB

NFBLOCKING Noise Figure Under Blocking Conditions Double-Side Band, PRF = 0dBm (Note 7) 15.5 dB IIP3 Input 3rd Order Intercept 28.7 dBm IIP2 Input 2nd Order Intercept Unadjusted, EIP2 = 0V 70 dBm

IIP2OPT Optimized Input 2nd Order Intercept EIP2 = 5V, IP2I, IP2Q Adjusted for Minimum IM2 80 dBm P1dB Input 1dB Compression 16 dBm

DCOFFSET DC Offset at I/Q Outputs Unadjusted, EDC = 0V (Note 13) 4 mV ∆G I/Q Gain Mismatch 0.05 dB ∆φ I/Q Phase Mismatch 0.3 Deg

5585f 2 LTC5585

ELECTRICAL CHARACTERISTICS TC = 25°C, VCC = 5V, EN = 5V, EDC = EIP2 = 0V, REF = IP2I = IP2Q = DCOI = DCOQ = 0.5V, PRF = –5dBm (–5dBm/tone for 2-tone IIP2 and IIP3 tests), PLO = 6dBm, unless otherwise noted. (Notes 2, 3, 5, 6, 9) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS IRR Image Rejection Ratio (Note 10) 45 dB LO-RF LO to RF Leakage –64 dBm RF-LO RF to LO Isolation 60 dB fRF1 = 1950MHz, fRF2 = 1951MHz, fLO = 1940MHz, L6 = 4.7nH, C19 = 0.5pF, L5 = 0.8pF, C13 = 5.1nH fRF(MATCH) RF Input Frequency Range Return Loss > 10dB 1.6 to 2.1 GHz fLO(MATCH) LO Input Frequency Range Return Loss > 10dB 1.85 to 2.05 GHz GV Voltage Conversion Gain Loaded with 100Ω Pull-Up (Note 8) 2.4 dB NF Noise Figure Double-Side Band (Note 4) 12.7 dB IIP3 Input 3rd Order Intercept 25.7 dBm IIP2 Input 2nd Order Intercept Unadjusted, EIP2 = 0V 60 dBm

IIP2OPT Optimized Input 2nd Order Intercept EIP2 = 5V, IP2I, IP2Q Adjusted for Minimum IM2 80 dBm P1dB Input 1dB Compression 16 dBm

DCOFFSET DC Offset at I/Q Outputs Unadjusted, EDC = 0V (Note 13) 7 mV ∆G I/Q Gain Mismatch 0.05 dB ∆φ I/Q Phase Mismatch 0.7 Deg IRR Image Rejection Ratio (Note 10) 43 dB LO-RF LO to RF Leakage –49 dBm RF-LO RF to LO Isolation 58 dB fRF1 = 2150MHz, fRF2 = 2151MHz, fLO = 2140MHz, C17 = 1.5pF, L6 = 4.7nH, C19 = 0.5pF, L5 = 5.1nH, C14 = 0.7pF fRF(MATCH) RF Input Frequency Range Return Loss > 10dB 2.03 to 2.36 GHz fLO(MATCH) LO Input Frequency Range Return Loss > 10dB 2.05 to 2.18 GHz GV Voltage Conversion Gain Loaded with 100Ω Pull-Up (Note 8) 2.3 dB NF Noise Figure Double-Side Band (Note 4) 13.0 dB

NFBLOCKING Noise Figure Under Blocking Conditions Double-Side Band, PRF = 0dBm (Note 7) 14.6 dB IIP3 Input 3rd Order Intercept 25.9 dBm IIP2 Input 2nd Order Intercept Unadjusted, EIP2 = 0V 56 dBm

IIP2OPT Optimized Input 2nd Order Intercept EIP2 = 5V, IP2I, IP2Q Adjusted for Minimum IM2 80 dBm P1dB Input 1dB Compression 15 dBm

DCOFFSET DC Offset at I/Q Outputs Unadjusted, EDC = 0V (Note 13) 6 mV ∆G I/Q Gain Mismatch 0.05 dB ∆φ I/Q Phase Mismatch 1.0 Deg IRR Image Rejection Ratio (Note 10) 40 dB LO-RF LO to RF Leakage –50 dBm RF-LO RF to LO Isolation 60 dB fRF1 = 2600MHz, fRF2 = 2601MHz, fLO = 2590MHz, C17 = 0.5pF, L6 = 2.7nH, L5 = 1.2nH, C14 = 1pF fRF(MATCH) RF Input Frequency Range Return Loss > 10dB 2.35 to 3.1 GHz fLO(MATCH) LO Input Frequency Range Return Loss > 10dB 2.47 to 2.65 GHz GV Voltage Conversion Gain Loaded with 100Ω Pull-Up (Note 8) 2.3 dB NF Noise Figure Double-Side Band (Note 4) 13.6 dB

NFBLOCKING Noise Figure Under Blocking Conditions Double-Side Band, PRF = 0dBm (Note 7) 15.2 dB IIP3 Input 3rd Order Intercept 27.5 dBm IIP2 Input 2nd Order Intercept Unadjusted, EIP2 = 0V 60 dBm

IIP2OPT Minimum Input 2nd Order Intercept EIP2 = 5V, IP2I, IP2Q Adjusted for Minimum IM2 80 dBm P1dB Input 1dB Compression 15.5 dBm

DCOFFSET DC Offset at I/Q Outputs Unadjusted, EDC = 0V (Note 13) 8 mV 5585f 3 LTC5585

VCC Supply Voltage 4.75 5.0 5.25 V ICC Supply Current 180 200 220 mA ICC(LOW) Supply Current EDC = EIP2 = 0V 170 190 210 mA ICC(OFF) Shutdown Current EN < 0.3V 11 900 μA tON Turn-On Time EN Transition from Logic Low to High (Note 14) 0.2 µs tOFF Turn-Off Time EN Transition from Logic High to Low (Note 15) 0.8 µs VEH EN, EDC, EIP2 Input High Voltage (On) 2.0 V VEL EN, EDC, EIP2 Input Low Voltage (Off) 0.3 V IENH EN Pin Input Current EN = 5.0V 52 μA IEDCH EDC Pin Input Current EDC = 5.0V 33 μA IEIP2H EIP2 Pin Input Current EIP2 = 5.0V 50 μA VREF REF Pin Voltage With REF Pin Unloaded 0.5 V VREF(RANGE) REF Pin Voltage Range When Driven with External Source 0.4 to 0.7 V ZREF REF Input Impedance (Note 11) 2||1 kΩ||pF DCOI, DCOQ, IP2I, IP2Q Pin Voltage Unloaded 0.5 V

DCOI, DCOQ, IP2I, IP2Q Voltage Range When Driven with External Source 0 to 2VREF V DCOI, DCOQ, IP2I, IP2Q Impedance (Note 11) 8||1 kΩ||pF DCOI, DCOQ, IP2I, IP2Q Settling Time For Step Input, Output with 90% of Final Value 20 ns DC Offset Adjustment Range DCOI, DCOQ Swept from 0V to 1V, EDC = 5V ±20 mV DC Offset Drift Over Temperature Unadjusted, EDC = 0V 20 μV/°C + – + – VCM I , I , Q , Q Common Mode Voltage VCC – 1.5 V + – + – ZOUT I , I , Q , Q Output Impedance Single Ended 100||6 Ω||pF + – + – BWBB I , I , Q , Q Output Bandwidth 100Ω External Pull-Up, –3dB Corner Frequency 530 MHz

Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 7: Noise figure under blocking conditions (NFBLOCKING) is measured may cause permanent damage to the device. Exposure to any Absolute at an output frequency of 60MHz with RF input signal at fLO + 1MHz. Both Maximum Rating condition for extended periods may affect device RF and LO input signals are appropriately filtered, as well as the baseband reliability and lifetime. output. NFBLOCKING measured at 840MHz, 2140MHz and 2500MHz only. Note 2: Tests are performed with the test circuit of Figure 1. Note 8: Voltage conversion gain is calculated from the average measured Note 3: The LTC5585 is guaranteed to be functional over the –40°C to power conversion gain of the I and Q outputs using the test circuit shown 105°C case temperature operating range. in Figure 1. Power conversion gain is measured with a 100Ω differential Note 4: DSB noise figure is measured at the baseband frequency of 15MHz load impedance on the I and Q outputs. with a small-signal noise source without any filtering on the RF input and Note 9: Baseband outputs have a 100Ω external pull-up resistor to VCC as no other RF signal applied. shown in the test circuit shown in Figure 1. Note 5: Performance at the RF frequencies listed is measured with external Note 10: Image rejection is calculated from the measured gain error and RF and LO impedance matching, as shown in the table of Figure 1. phase error using the method listed in the appendix. Note 6: The complementary outputs (I+, I– and Q+, Q–) are combined Note 11: The DCOI, DCOQ, IP2I, IP2Q pins have an 8k internal resistor to using a 180° phase-shift combiner. ground. The REF pin has a 2k internal resistor to ground. If unconnected, these pins will float up to 500mV through internal current sources. A low output resistance voltage source is recommended for driving these pins.

5585f 4 LTC5585 ELECTRICAL CHARACTERISTICS Note 12: This is the recommended operating range, operation outside the Note 14: Baseband amplitude is within 10% of final value. listed range is possible with degraded performance to some parameters. Note 15: Baseband amplitude is at least 30dB down from its on state. Note 13: DC offset measured differentially between I+ and I– and between Q+ and Q–. The reported value is the mean of the absolute values of the characterization data distribution.

DC PERFORMANCE CHARACTERISTICS EN = 5V, EDC = 0V and EIP2 = 0V. Test circuit shown in Figure 1

Supply Current vs Supply Voltage REF Voltage vs Temperature 260 550 TC = –40°C V = 4.75V 250 545 CC TC = 25°C VCC = 5V 240 TC = 85°C 540 VCC = 5.25V TC = 105°C 230 535 220 530 210 525 200 520

190 REF VOLTAGE (mV) 515 SUPPLY CURRENT (mA) 180 510 170 505 160 500 4.75 5 5.25 –40 –20 0 20 40 60 80 100 SUPPLY VOLTAGE (V) TEMPERATURE (°C)

5585 G01 5585 G02

TYPICAL PERFORMANCE CHARACTERISTICS 700MHz application. VCC = 5V, EN = 5V, EDC = 0V, EIP2 = 0V, REF = 0.5V, TC = 25°C, PLO = 6dBm, fLO = 690MHz, fRF1 = 700MHz, fRF2 = 701MHz, fBB = 10MHz, PRF1 = PRF2 = –5dBm, DC Blocks and Mini-Circuits PSCJ-2-1 180° combiner at baseband outputs de-embedded from measurement unless otherwise noted. Test circuit with RF and LO ports impedance matched as in Figure 1.

IIP3, P1dB vs Temperature (TC) IIP3, P1dB vs Supply Voltage (VCC) IIP3 vs LO Power 50 50 50 I, –40°C Q, –40°C I, 4.75V Q, 4.75V TC = 25°C I, 0dBm Q, 0dBm TC = 25°C 46 I, 25°C Q, 25°C 46 I, 5.0V Q, 5.0V 46 I, 6dBm Q, 6dBm I, 85°C Q, 85°C I, 5.25V Q, 5.25V I, 10dBm Q, 10dBm 42 I, 105°C Q, 105°C 42 42 38 38 38

34 IIP3 34 34 30 30 IIP3 30

26 26 IIP3 (dBm) 26 IIP3, P1dB (dBm) 22 IIP3, IP1dB (dBm) 22 22 18 P1dB 18 P1dB 18 14 14 14 10 10 10 600 700 800 900 1000 600 700 800 900 1000 600 700 800 900 1000 LO FREQUENCY (MHz) LO FREQUENCY (MHz) LO FREQUENCY (MHz)

5585 G03 5585 G04 5585 G05

5585f 5 LTC5585

Uncalibrated IIP2 vs Temperature 2-Tone IIP3 vs RF Power (TC) Uncalibrated IIP2 vs LO Power 50 120 120 48 I, –40°C Q, –40°C fRF1 = 700MHz I, –40°C Q, –40°C I, 0dBm Q, 0dBm TC = 25°C I, 25°C Q, 25°C f = 701MHz I, 25°C Q, 25°C I, 6dBm Q, 6dBm 46 RF2 I, 85°C Q, 85°C f = 690MHz 110 I, 85°C Q, 85°C 110 I, 10dBm Q, 10dBm 44 I, 105°C Q, 105°C LO I, 105°C Q, 105°C 42 100 100 40 38 90 90 36 34 80 80 IIP3 (dBm) 32 IIP2 (dBm) IIP2 (dBm) 30 28 70 70 26 24 60 60 22 20 50 50 –10 –8 –6 –4–2 0 2 4 600 700 800 900 1000 600 700 800 900 1000 RF POWER (dBm) LO FREQUENCY (MHz) LO FREQUENCY (MHz)

5585 G06 5585 G07 5585 G08 2x2 Half-IF IIP2 IIP2 vs IP2I, IP2Q Trim Voltage IIP2 vs RF Tone Spacing vs RF to LO Tone Spacing 120 100 100 I, –40°C Q, –40°C fRF = 700MHz TC = 25°C I (UNCALIBRATED) TC = 25°C I, 25°C Q, 25°C 95 I (NULLED AT 1MHz) 95 110 fRF1 = 700MHz fLO = 690MHz I, 85°C Q, 85°C 90 f = 690MHz Q (UNCALIBRATED) I, 105°C Q, 105°C LO Q (NULLED AT 1MHz) 90 100 85 85 80 90 75 80 Q 80 70 75 I IIP2 (dBm) IIP2 (dBm) 65 IIP2 (dBm) 70 70 60 65 60 55 60 50 50 45 55 40 40 50 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 50 100 150 200 250 300 350 400 0 50100 150 200 250 300 350 400 IP2I, IP2Q (V) RF TONE SPACING (MHz) RF TO LO TONE SPACING (MHz)

5585 G09 5585 G10 5585 G11 Noise Figure and Conversion Noise Figure and Conversion Noise Figure vs RF Power and Gain vs Temperature (TC) Gain vs LO Power IP2I, IP2Q Trim Voltage 24 24 20 I, –40°C Q, –40°C T = 25°C 22 22 I, 0dBm Q, 0dBm C I, –20dBm Q, –20dBm I, 25°C Q, 25°C I, 6dBm Q, 6dBm 19 I, 0dBm Q, 0dBm 20 I, 85°C Q, 85°C 20 I, 10dBm Q, 10dBm 18 I, 105°C Q, 105°C 18 18 16 NF 16 17 14 14 NF 16 12 12 10 10 15 8 8 14 GAIN, NF (dB) 6 GAIN, NF (dB) 6 4 GAIN 4 13 TC = 25°C

GAIN DSB NOISE FIGURE (dB) 2 2 fRF = 890MHz 12 f = 900MHz 0 0 LO 11 fNOISE = 3.4MHz –2 –2 EIP2 = 5V –4 –4 10 600 700 800 900 1000 600 700 800 900 1000 0 0.20.1 0.40.3 0.5 0.6 0.70.8 0.9 1.0 LO FREQUENCY (MHz) LO FREQUENCY (MHz) IP2I, IP2Q TRIM VOLTAGE (V)

5585 G12 5585 G13 5585 G14

5585f 6 LTC5585

Noise Figure vs RF Input Power Noise Figure vs RF Input Power DC Offset vs DCOI, DCOQ Control with fNOISE = 60MHz with fNOISE = 3.4MHz Voltage 25 25 40 24 PLO = 0dBm 24 PLO = 0dBm fLO = 700MHz I, –40°C Q, –40°C PLO = 6dBm PLO = 6dBm 35 I, 25°C Q, 25°C 23 PLO = 10dBm 23 PLO = 10dBm 30 I, 85°C Q, 85°C 22 22 I, 105°C Q, 105°C TC = 25°C TC = 25°C 25 21 21 fLO = 840MHz fLO = 900MHz 20 20 fRF = 841MHz 20 fRF = 890MHz 15 19 fNOISE = 60MHz 19 fNOISE = 3.4MHz 18 18 10 17 17 5 16 16 0 15 15 DC OFFSET (mV) –5

DSB NOISE FIGURE (dB) 14 DSB NOISE FIGURE (dB) 14 –10 13 13 12 12 –15 11 11 –20 10 10 –25 –20 –15 –10 –5 0 5 10 –20 –15 –10 –5 0 5 10 0 0.10.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 RF INPUT POWER (dBm) RF INPUT POWER (dBm) DCOI, DCOQ (V)

5585 G15 5585 G16 5585 G17

LO to RF Leakage and RF to LO Image Rejection vs Temperature DC Offset vs LO Power Isolation (Note 10) 10 –30 100 9 I, 0dBm Q, 0dBm TC = 25°C –35 L-R, –40°C R-L, –40°C TC = –40°C I, 6dBm Q, 6dBm L-R, 25°C R-L, 25°C TC = 25°C 8 I, 10dBm Q, 10dBm –40 L-R, 85°C R-L, 85°C 90 TC = 85°C 7 –45 L-R, 105°C R-L, 105°C 80 TC = 105°C 6 –50 5 –55 4 70 –60 3 –65 60 2 –70 1 –75 50 DC OFFSET (mV) 0

–80 IMAGE REJECTION (dB) –1 40 –2 –85

–3 LEAKAGE (dBm), –ISOLATION (dBc) –90 30 –4 –95 –5 –100 20 600 650 700 750800 850 900 950 1000 600 650 700 750 800 850 900 950 1000 600 650 700 750 800 850 900 950 1000 LO FREQUENCY (MHz) LO FREQUENCY (MHz) LO FREQUENCY (MHz)

5585 G18 5585 G19 5585 G20

5585f 7 LTC5585

TYPICAL PERFORMANCE CHARACTERISTICS 1950MHz application. VCC = 5V, EN = 5V, EDC = 0V, REF = 0.5V, EIP2 = 0V, TC = 25°C, PLO = 6dBm, fLO = 1940MHz, fRF1 = 1950MHz, fRF2 = 1951MHz, fBB = 10MHz, PRF1 = PRF2 = –5dBm, DC Blocks and Mini-Circuits PSCJ-2-1 180° combiner at baseband outputs de-embedded from measurement unless otherwise noted. Test circuit with RF and LO ports impedance matched as in Figure 1.

IIP3, P1dB vs Temperature (TC) IIP3, P1dB vs Supply Voltage IIP3 vs LO Power 50 50 50 I, –40°C Q, –40°C I, 4.75V Q, 4.75V TC = 25°C I, 0dBm Q, 0dBm TC = 25°C 46 I, 25°C Q, 25°C 46 I, 5.0V Q, 5.0V 46 I, 6dBm Q, 6dBm I, 85°C Q, 85°C I, 5.25V Q, 5.25V I, 10dBm Q, 10dBm 42 I, 105°C Q, 105°C 42 42 38 38 38 34 34 34 IIP3 30 30 30 IIP3

26 26 IIP3 (dBm) 26

IIP3, P1dB (dBm) 22 IIP3, P1dB (dBm) 22 22

18 P1dB 18 P1dB 18 14 14 14 10 10 10 1500 1600 1700 1800 1900 2000 2100 2200 1500 1600 1700 1800 1900 2000 2100 2200 1500 1600 1700 1800 1900 2000 2100 2200 LO FREQUENCY (MHz) LO FREQUENCY (MHz) LO FREQUENCY (MHz)

5585 G21 5585 G22 5585 G23 Uncalibrated IIP2 vs Temperature 2-Tone IIP3 vs RF Power (TC) Uncalibrated IIP2 vs LO Power 50 130 130 48 I, –40°C Q, –40°C I, –40°C Q, –40°C I, 0dBm Q, 0dBm TC = 25°C I, 25°C Q, 25°C 120 I, 25°C Q, 25°C 120 I, 6dBm Q, 6dBm 46 I, 85°C Q, 85°C I, 85°C Q, 85°C I, 10dBm Q, 10dBm 44 I, 105°C Q, 105°C 110 I, 105°C Q, 105°C 110 42 fRF1 = 1950MHz 40 fRF2 = 1951MHz 100 100 38 fLO = 1940MHz 36 90 90 34 80 80 IIP3 (dBm) 32 IIP2 (dBm) IIP2 (dBm) 30 70 70 28 26 60 60 24 50 50 22 20 40 40 –10 –8 –6 –4–2 0 2 4 1500 1600 1700 1800 1900 2000 2100 2200 1500 1600 1700 1800 1900 2000 2100 2200 RF POWER (dBm) LO FREQUENCY (MHz) LO FREQUENCY (MHz)

5585 G24 5585 G25 5585 G26 2x2 Half-IF IIP2 IIP2 vs IP2I, IP2Q Trim Voltage IIP2 vs RF Tone Spacing vs RF to LO Tone Spacing 120 100 100 I, –40°C Q, –40°C TC = 25°C I (UNCALIBRATED) TC = 25°C I, 25°C Q, 25°C 95 I (NULLED AT 1MHz) 95 110 fRF1 = 1950MHz fLO = 1940MHz I, 85°C Q, 85°C 90 f = 1940MHz Q (UNCALIBRATED) I, 105°C Q, 105°C LO Q (NULLED AT 1MHz) 90 100 85 fRF = 1950MHz 80 85 90 75 80 80 70 75 IIP2 (dBm) IIP2 (dBm) 65 IIP2 (dBm) 70 70 60 65 I 60 55 60 50 Q 50 45 55 40 40 50 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 50 100 150 200 250 300 350 400 0 50100 150 200 250 300 350 400 IP2I, IP2Q (V) RF TONE SPACING (MHz) RF TO LO TONE SPACING (MHz)

5585 G27 5585 G28 5585 G29 5585f 8 LTC5585

Noise Figure and Conversion Noise Figure and Conversion DC Offset vs DCOI, DCOQ Control Gain vs Temperature (TC) Gain vs LO Power Voltage 24 24 40 22 I, –40°C Q, –40°C 22 I, 0dBm Q, 0dBm TC = 25°C fLO = 1950MHz I, –40°C Q, –40°C I, 25°C Q, 25°C I, 6dBm Q, 6dBm 35 I, 25°C Q, 25°C 20 I, 85°C Q, 85°C 20 I, 10dBm Q, 10dBm 30 I, 85°C Q, 85°C 18 I, 105°C Q, 105°C 18 25 I, 105°C Q, 105°C 16 16 NF 20 14 14 NF 15 12 12 10 10 10 5 8 8 0 GAIN, NF (dB) 6 GAIN, NF (dB) 6 GAIN DC OFFSET (mV) 4 4 GAIN –5 2 2 –10 0 0 –15 –2 –2 –20 –4 –4 –25 1500 1600 1700 1800 1900 2000 2100 2200 1500 1600 1700 1800 1900 2000 2100 2200 0 0.10.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 LO FREQUENCY (MHz) LO FREQUENCY (MHz) DCOI, DCOQ (V)

5585 G30 5585 G31 5585 G32 LO to RF Leakage and RF to LO Image Rejection vs Temperature DC Offset vs LO Power Isolation (Note 10) 15 –20 100 L-R, –40°C R-L, –40°C 14 I, 0dBm Q, 0dBm TC = 25°C –25 TC = –40°C I, 6dBm Q, 6dBm L-R, 25°C R-L, 25°C 13 –30 90 TC = 25°C I, 10dBm Q, 10dBm L-R, 85°C R-L, 85°C T = 85°C 12 –35 L-R, 105°C R-L, 105°C C TC = 105°C 11 –40 80 10 –45 70 9 –50 8 –55 60 7 –60 6 –65 50 DC OFFSET (mV) 5 –70 4 IMAGE REJECTION (dB) 40 3 –75

LEAKAGE (dBm), –ISOLATION (dBc) –80 2 30 1 –85 0 –90 20 1500 1600 1700 18001900 2000 22002100 1500 1600 1700 1800 1900 2000 2100 2200 1500 1600 1700 1800 1900 2000 2100 2200 LO FREQUENCY (MHz) LO FREQUENCY (MHz) LO FREQUENCY (MHz)

5585 G33 5585 G34 5585 G35

Conversion Gain Distribution IIP3 Distribution, I Side IIP3 Distribution, Q Side 50 100 100 TC = –40°C TC = –40°C TC = –40°C TC = 25°C 90 TC = 25°C 90 TC = 25°C T = 85°C T = 85°C T = 85°C 40 C 80 C 80 C TC = 105°C TC = 105°C TC = 105°C 70 70 30 60 60 50 50 20 40 40 30 30 10 20 20 PERCENTAGE DISTRIBUTION (%) PERCENTAGE DISTRIBUTION (%) PERCENTAGE DISTRIBUTION (%) 10 10 0 0 0 2 2.2 2.4 2.6 2.8 3.0 3.2 20 22 24 26 28 30 32 20 22 24 26 28 30 32 CONVERSION GAIN (dB) IIP3 (dBm) IIP3 (dBm)

5585 G36 5585 G37 5585 G38 5585f 9 LTC5585

DSB Noise Figure Distribution, DSB Noise Figure Distribution, I Side Q Side IIP2 Distribution, I Side 100 100 100 TC = –40°C TC = –40°C TC = –40°C 90 TC = 25°C 90 TC = 25°C 90 TC = 25°C T = 85°C T = 85°C T = 85°C 80 C 80 C 80 C TC = 105°C TC = 105°C TC = 105°C 70 70 70 60 60 60 50 50 50 40 40 40 30 30 30 20 20 20 PERCENTAGE DISTRIBUTION (%) PERCENTAGE DISTRIBUTION (%) PERCENTAGE DISTRIBUTION (%) 10 10 10 0 0 0 11 12 13 14 15 16 17 11 12 13 14 15 16 17 70 75 80 85 90 95 100 DSB NOISE FIGURE (dB) DSB NOISE FIGURE (dB) IIP2 (dBm)

5585 G39 5585 G40 5585 G41

IIP2 Distribution, Q Side Gain Error Distribution 100 70 TC = –40°C TC = –40°C 90 T = 25°C T = 25°C C 60 C T = 85°C T = 85°C 80 C C TC = 105°C TC = 105°C 70 50 60 40 50 30 40

30 20 20 PERCENTAGE DISTRIBUTION (%) PERCENTAGE DISTRIBUTION (%) 10 10 0 0 70 75 80 85 90 95 100 –0.1 –0.06 –0.02 0.02 0.06 0.1 IIP2 (dBm) GAIN ERROR (dB)

5585 G42 5585 G43

Image Rejection Distribution Phase Error Distribution (Note 10) 30 50 TC = –40°C TC = –40°C TC = 25°C TC = 25°C T = 85°C T = 85°C C 40 C TC = 105°C TC = 105°C 20 30

20 10

10 PERCENTAGE DISTRIBUTION (%) PERCENTAGE DISTRIBUTION (%)

0 0 –1 –0.8 –0.6 0.4 0.2 0 40 42.545 47.5 50 52.555 57.5 60 PHASE ERROR (DEGREES) IMAGE REJECTION (dBc)

5585 G44 5585 G45

5585f 10 LTC5585

TYPICAL PERFORMANCE CHARACTERISTICS 2150MHz application. VCC = 5V, EN = 5V, EDC = 0V, EIP2 = 0V, REF = 0.5V, TC = 25°C, PLO = 6dBm, fLO = 2140MHz, fRF1 = 2150MHz, fRF2 = 2151MHz, fBB = 10MHz, PRF1 = PRF2 = –5dBm, DC Blocks and Mini-Circuits PSCJ-2-1 180° combiner at baseband outputs de-embedded from measurement unless otherwise noted. Test circuit with RF and LO ports impedance matched as in Figure 1.

IIP3, P1dB vs Supply Voltage IIP3, P1dB vs Temperature (TC) (VCC) IIP3 vs LO Power 50 50 50 I, –40°C Q, –40°C I, 4.75V Q, 4.75V TC = 25°C I, 0dBm Q, 0dBm TC = 25°C 46 I, 25°C Q, 25°C 46 I, 5.0V Q, 5.0V 46 I, 6dBm Q, 6dBm I, 85°C Q, 85°C I, 5.25V Q, 5.25V I, 10dBm Q, 10dBm 42 I, 105°C Q, 105°C 42 42 38 38 38 34 34 34 IIP3 IIP3 30 30 30

26 26 IIP3 (dBm) 26 IIP3, P1dB (dBm) 22 IIP3, P1dB (dBm) 22 22 18 P1dB 18 P1dB 18 14 14 14 10 10 10 1750 18501950 2050 2150 2250 2350 2450 2550 1750 18501950 2050 2150 2250 2350 2450 2550 1750 18501950 2050 2150 2250 2350 2450 2550 LO FREQUENCY (MHz) LO FREQUENCY (MHz) LO FREQUENCY (MHz)

5585 G46 5585 G47 5585 G48 Uncalibrated IIP2 vs Temperature 2-Tone IIP3 vs RF Power (TC) Uncalibrated IIP2 vs LO Power 50 130 130 48 I, –40°C Q, –40°C I, –40°C Q, –40°C I, 0dBm Q, 0dBm TC = 25°C I, 25°C Q, 25°C 120 I, 25°C Q, 25°C 120 I, 6dBm Q, 6dBm 46 I, 85°C Q, 85°C I, 85°C Q, 85°C I, 10dBm Q, 10dBm 44 I, 105°C Q, 105°C 110 I, 105°C Q, 105°C 110 42 fRF1 = 2150MHz 40 fRF2 = 2151MHz 100 100 38 fLO = 2140MHz 36 90 90 34 80 80 IIP3 (dBm) IIP2 (dBm) 32 IIP2 (dBm) 30 70 70 28 26 60 60 24 50 50 22 20 40 40 –10 –8 –6 –4–2 0 2 4 1750 1850 1950 2050 2150 2250 2350 2450 2550 1750 1850 1950 2050 2150 2250 2350 2450 2550 RF POWER (dBm) LO FREQUENCY (MHz) LO FREQUENCY (MHz)

5585 G49 5585 G50 5585 G51 2x2 Half-IF IIP2 IIP2 vs IP2I, IP2Q Trim Voltage IIP2 vs RF Tone Spacing vs RF to LO Tone Spacing 120 100 100 I, –40°C Q, –40°C TC = 25°C I (UNCALIBRATED) TC = 25°C I, 25°C Q, 25°C 95 I (NULLED AT 1MHz) 95 110 fRF1 = 2150MHz fLO = 2140MHz I, 85°C Q, 85°C 90 f = 2140MHz Q (UNCALIBRATED) I, 105°C Q, 105°C LO Q (NULLED AT 1MHz) 90 100 85 fRF = 2150MHz 80 85 90 75 80 Q 80 70 75 IIP2 (dBm)

IIP2 (dBm) 65 IIP2 (dBm) 70 70 60 65 I 60 55 60 50 50 45 55 40 40 50 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 50 100 150 200 250 300 350 400 0 50100 150 200 250 300 350 400 IP2I, IP2Q (V) RF TONE SPACING (MHz) RF TO LO TONE SPACING (MHz)

5585 G52 5585 G53 5585 G54

5585f 11 LTC5585

Noise Figure and Conversion Noise Figure and Conversion Noise Figure vs RF Input Power Gain vs Temperature (TC) Gain vs LO Power 25 24 24 PLO = 0dBm 24 22 I, –40°C Q, –40°C 22 I, 0dBm Q, 0dBm TC = 25°C PLO = 6dBm I, 25°C Q, 25°C I, 6dBm Q, 6dBm 23 PLO = 10dBm 20 I, 85°C Q, 85°C 20 I, 10dBm Q, 10dBm 22 I, 105°C Q, 105°C TC = 25°C 18 18 21 fLO = 2140MHz 16 16 NF NF 20 fRF = 2141MHz 14 14 19 f = 60MHz NOISE 12 12 18 10 10 17 8 8 16 GAIN, NF (dB) 15 GAIN, NF (dB) 6 6 4 GAIN 4 GAIN DSB NOISE FIGURE (dB) 14 13 2 2 12 0 0 11 –2 –2 10 –4 –4 –20 –15 –10 –5 0 5 10 1750 1850 1950 2050 2150 2250 2350 2450 2550 1750 1850 1950 2050 2150 2250 2350 2450 2550 RF INPUT POWER (dBm) LO FREQUENCY (MHz) LO FREQUENCY (MHz)

5585 G55 5585 G56 5585 G57 DC Offset vs DCOI, DCOQ Control Voltage DC Offset vs LO Power 40 15 fLO = 2150MHz I, –40°C Q, –40°C I, 0dBm Q, 0dBm TC = 25°C 35 I, 25°C Q, 25°C 13 I, 6dBm Q, 6dBm 30 I, 85°C Q, 85°C I, 10dBm Q, 10dBm 11 25 I, 105°C Q, 105°C 20 9 15 7 10 5 5 0 3 DC OFFSET (mV) DC OFFSET (mV) –5 1 –10 –1 –15 –3 –20 –25 –5 0 0.10.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1750 18501950 2050 2150 2250 2350 2450 2550 DCOI, DCOQ (V) LO FREQUENCY (MHz)

5585 G58 5585 G59 LO to RF Leakage and RF to LO Image Rejection vs Temperature Isolation (Note 10) –20 100 –25 L-R, –40°C R-L, –40°C TC = –40°C L-R, 25°C R-L, 25°C T = 25°C –30 90 C L-R, 85°C R-L, 85°C T = 85°C –35 L-R, 105°C R-L, 105°C C 80 TC = 105°C –40 –45 70 –50 –55 60 –60 –65 50 –70 IMAGE REJECTION (dB) 40 –75

LEAKAGE (dBm), –ISOLATION (dBc) –80 30 –85 –90 20 1750 1850 1950 2050 2150 2250 2350 2450 2550 1750 1850 1950 2050 2150 2250 2350 2450 2550 LO FREQUENCY (MHz) LO FREQUENCY (MHz)

5585 G60 5585 G61 5585f 12 LTC5585

TYPICAL PERFORMANCE CHARACTERISTICS 2600MHz application. VCC = 5V, EN = 5V, EDC = 0V, EIP2 = 0V, REF = 0.5V, TC = 25°C, PLO = 6dBm, fLO = 2590MHz, fRF1 = 2600MHz, fRF2 = 2601MHz, fBB = 10MHz, PRF1 = PRF2 = –5dBm, DC Blocks and Mini-Circuits PSCJ-2-1 180° combiner at baseband outputs de-embedded from measurement unless otherwise noted. Test circuit with RF and LO ports impedance matched as in Figure 1.

26 26 IIP3 (dBm) 26 IIP3, P1dB (dBm) 22 IIP3, P1dB (dBm) 22 22

18 P1dB 18 P1dB 18 14 14 14 10 10 10 2200 23002400 2500 2600 2700 2800 2900 3000 2200 23002400 2500 2600 2700 2800 2900 3000 2200 23002400 2500 2600 2700 2800 2900 3000 LO FREQUENCY (MHz) LO FREQUENCY (MHz) LO FREQUENCY (MHz)

5585 G62 5585 G63 5585 G64 Uncalibrated IIP2 vs Temperature 2-Tone IIP3 vs RF Power (TC) Uncalibrated IIP2 vs LO Power 50 130 130 48 I, –40°C Q, –40°C I, –40°C Q, –40°C I, 0dBm Q, 0dBm TC = 25°C I, 25°C Q, 25°C 120 I, 25°C Q, 25°C 120 I, 6dBm Q, 6dBm 46 I, 85°C Q, 85°C I, 85°C Q, 85°C I, 10dBm Q, 10dBm 44 I, 105°C Q, 105°C 110 I, 105°C Q, 105°C 110 42 fRF1 = 2600MHz 40 fRF2 = 2601MHz 100 100 38 fLO = 2590MHz 36 90 90 34 80 80 IIP3 (dBm) IIP2 (dBm) 32 IIP2 (dBm) 30 70 70 28 26 60 60 24 50 50 22 20 40 40 –10 –8 –6 –4–2 0 2 4 2200 23002400 2500 2600 2700 2800 2900 3000 2200 23002400 2500 2600 2700 2800 2900 3000 RF POWER (dBm) LO FREQUENCY (MHz) LO FREQUENCY (MHz)

5585 G65 5585 G66 5585 G66 2x2 Half-IF IIP2 vs RF to LO Tone IIP2 vs IP2I, IP2Q Trim Voltage IIP2 vs RF Tone Spacing Spacing 120 100 100 I, –40°C Q, –40°C TC = 25°C I (UNCALIBRATED) TC = 25°C I, 25°C Q, 25°C 95 I (NULLED AT 1MHz) 95 110 fRF1 = 2600MHz fLO = 2590MHz I, 85°C Q, 85°C 90 f = 2590MHz Q (UNCALIBRATED) I, 105°C Q, 105°C LO Q (NULLED AT 1MHz) 90 100 85 fRF = 2600MHz 85 80 90 75 80 80 70 75 IIP2 (dBm) IIP2 (dBm) 65 IIP2 (dBm) 70 70 60 65 60 55 60 50 I 50 45 55 Q 40 40 50 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 50 100 150 200 250 300 350 400 0 50100 150 200 250 300 350 400 IP2I, IP2Q (V) RF TONE SPACING (MHz) RF TO LO TONE SPACING (MHz)

5585 G68 5585 G69 5585 G70

5585f 13 LTC5585

Noise Figure and Conversion Noise Figure and Conversion Noise Figure vs RF Power and Gain vs Temperature (TC) Gain vs LO Power IP2I, IP2Q Trim Voltage 24 24 20 22 I, –40°C Q, –40°C 22 I, 0dBm Q, 0dBm TC = 25°C I, –20dBm Q, –20dBm I, 25°C Q, 25°C I, 6dBm Q, 6dBm 19 I, 0dBm Q, 0dBm 20 I, 85°C Q, 85°C 20 I, 10dBm Q, 10dBm 18 I, 105°C Q, 105°C 18 18 16 16 NF 17 14 14 16 12 NF 12 10 10 15 8 8 14 GAIN, NF (dB) 6 GAIN, NF (dB) 6 4 GAIN 4 GAIN 13 TC = 25°C DSB NOISE FIGURE (dB) 2 2 fRF = 2501MHz 12 f = 2500MHz 0 0 LO 11 fNOISE = 60MHz –2 –2 EIP2 = 5V –4 –4 10 2200 2300 2400 2500 2600 2700 2800 2900 3000 2200 2300 2400 2500 2600 2700 2800 2900 3000 0 0.20.1 0.40.3 0.5 0.6 0.70.8 0.9 1.0 LO FREQUENCY (MHz) LO FREQUENCY (MHz) IP2I, IP2Q TRIM VOLTAGE (V)

5585 G71 5585 G72 5585 G73 DC Offset vs DCOI, DCOQ Control Noise Figure vs RF Input Power Voltage DC Offset vs LO Power 25 40 15 24 PLO = 0dBm fLO = 2600MHz I, –40°C Q, –40°C I, 0dBm Q, 0dBm TC = 25°C PLO = 6dBm 35 I, 25°C Q, 25°C 13 I, 6dBm Q, 6dBm 23 PLO = 10dBm 30 I, 85°C Q, 85°C I, 10dBm Q, 10dBm 22 I, 105°C Q, 105°C 11 TC = 25°C 25 21 fLO = 2500MHz 20 9 20 fRF = 2501MHz 15 19 fNOISE = 60MHz 7 18 10 5 17 5 16 0 3 DC OFFSET (mV) 15 DC OFFSET (mV) –5 1

DSB NOISE FIGURE (dB) 14 –10 13 –1 12 –15 –3 11 –20 10 –25 –5 –20 –15 –10 –5 0 5 10 0 0.10.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 2200 2400 2600 2800 3000 RF INPUT POWER (dBm) DCOI, DCOQ (V) LO FREQUENCY (MHz)

5585 G74 5585 G75 5585 G76 LO to RF Leakage and RF to LO Image Rejection vs Temperature Isolation (Note 10) –10 100 –15 L-R, –40°C R-L, –40°C TC = –40°C L-R, 25°C R-L, 25°C T = 25°C –20 90 C L-R, 85°C R-L, 85°C T = 85°C –25 L-R, 105°C R-L, 105°C C 80 TC = 105°C –30 –35 70 –40 –45 60 –50 –55 50 –60 IMAGE REJECTION (dB) 40 –65

LEAKAGE (dBm), –ISOLATION (dBc) –70 30 –75 –80 20 2200 2300 2400 2500 2600 2700 2800 2900 3000 2200 2300 2400 2500 2600 2700 2800 2900 3000 LO FREQUENCY (MHz) LO FREQUENCY (MHz)

5585 G77 5585 G78 5585f 14 LTC5585 PIN FUNCTIONS IP2Q, IP2I (Pin 1, Pin 4): IIP2 Adjustment Analog Control EDC (Pin 11): DC Offset Adjustment Mode Enable Pin. Voltage Input for Q and I Channel. A decoupling capacitor When the voltage on the EDC pin is a logic high, the DC is recommended on this pin. A low output resistance volt- offset control circuitry is enabled. The circuitry is disabled age source is recommended for driving these pins. These for a logic low. An internal 200k pull-down resistor ensures pins should be left floating if unused. the circuitry remains disabled if there is no connection to DCOQ, DCOI (Pin 2, Pin 3): DC Offset Analog Control the pin (open-circuit condition). Voltage Input for Q and I Channel. A decoupling capaci- EIP2 (Pin 12): IP2 Offset Adjustment Mode Enable Pin. tor is recommended on this pin. A low output resistance When the voltage on the EIP2 pin is a logic high, the IP2 voltage source is recommended for driving these pins. adjustment circuitry is enabled. The circuitry is disabled These pins should be left floating if unused. for a logic low. An internal 200k pull-down resistor ensures RF (Pin 5): RF Input. External matching is used to obtain the circuitry remains disabled if there is no connection to good return loss across the RF input frequency range. the pin (open-circuit condition). The RF pin is internally shorted to ground through internal LO+,LO– (Pin 15, Pin 16): LO Inputs. External matching transformer windings. The RF pin should be DC-blocked is required to obtain good return loss across the LO input with a 1000pF coupling capacitor. frequency range. Can be driven single ended or differentially with an external transformer. The LO pins should be GND (Pins 6, 8, 13, 14, Exposed Pad Pin 25): Ground. DC-blocked with a 1000pF coupling capacitor. These pins must be soldered to the RF ground plane on the circuit board. The backside exposed pad ground con- VCAP, CMQ, CMI (Pin 17, Pin 18, Pin 19): Common Mode nection should have a low inductance connection and Bypass Capacitor Pins. It is recommended that CMI and good thermal contact to the printed circuit board ground CMQ be connected to VCAP through 0.1µF capacitors. plane using many through-hole vias. See Figures 2 and 3. Nothing else should be connected to VCAP since it is connected to V inside the chip. EN (Pin 7): Enable Pin. When the voltage on the EN pin CC is a logic high, the chip is completely turned on; the chip I+, I–, Q+, Q– (Pin 23, Pin 22, Pin 21, Pin 20): Differential is completely turned off for a logic low. An internal 200k Baseband Output Pins for the I Channel and Q Channel. pull-down resistor ensures the chip remains disabled if The DC bias point is VCC – 1.5V for each pin. These pins there is no connection to the pin (open-circuit condition). must have an external 100Ω or an inductor pull-up to VCC.

VBIAS (Pin 9): This pin can be pulled to ground through REF (Pin 24): Voltage Reference Input for Analog Control a resistor to lower the current consumption of the chip. Voltage Pins. A decoupling capacitor is recommended See Applications Information. on this pin. A low output resistance voltage source is recommended for driving this pin. This pin should be left VCC (Pin 10): Positive Supply Pin. This pin should be bypassed with shunt 1000pF and 1µF capacitors. floating if unused.

5585f 15 LTC5585 BLOCK DIAGRAM

10 17 CMI VCC VCAP 19 RF I+ 5 23 I– 22 GND 6

DCOI IP2 AND DC 3 IP2I OFFSET CAL 4 EDC LO+ 11 15 0° EIP2 LO– 12 16 90° REF 24 IP2Q IP2 AND DC 1 DCOQ OFFSET CAL 2

VBIAS 9 Q+ EN 21 7 BIAS Q– 20 CMQ 18 EXPOSED GND GND GND PAD 8 13 14 25 5585 BD

5585f 16 LTC5585 TEST CIRCUIT

RF 0.015" GND 0.062" DC 0.015" GND NELCO N4000-13

C29 C21 C22 C30 R9 R11 R13 R14

I– OUT Q+ OUT

I+ OUT Q– OUT C10 REF C31 24 23 22 21 20 19 + – + – I I C11 Q Q REF 1 CMI 18 IP2Q IP2Q CMQ C36 C12 2 17 L5 DCOQ DCOQ V 3 T1 1 CAP LO 3 – 16 DCOI DCOI LO 2 6 C13 C14 4 LTC5585IUF + 15 C37 IP2I IP2I LO 4 5 5 14 C32 C33 C34 C35 RF GND 6 13 GND GND 25 C18 GND BIAS CC EN GND V L6 V EDC EIP2 RF 7 8 9 10 11 12 C17 C19 EIP2 EDC V EN CC 4.75V TO 5.25V C15 C16

5585 F01

RF MATCH LO MATCH FREQUENCY RANGE C17 L6 C19 C13 L5 C14 700MHz 2.7pF 1.0pF 12nH 5.6pF 1950MHz 4.7nH 0.5pF 5.1nH 0.8pF 2150MHz 0.5pF 4.7nH 5.1nH 0.7pF 2600MHz 0.5pF 2.7nH 1.2nH 1pF

REF DES VALUE SIZE VENDOR REF DES VALUE SIZE VENDOR C10, C11, C31-C35 0.1μF 0402 Murata L5, L6 See Table 0402 Murata C12, C15, C18, C36, C37 1000pF 0402 Murata R9, R11, R13, R14 100Ω 0402 Vishay C13, C14, C17, C19 See Table 0402 Murata T1 4:1 0805 Anaren BD0826J50200A00 C16, C21, C22, C29, C30 1μF 0402 Murata

Figure 1. Test Circuit Schematic

5585f 17 LTC5585 TEST CIRCUIT

Figure 2. Component Side of Evaluation Board Figure 3. Bottom Side of Evaluation Board

APPLICATIONS INFORMATION

The LTC5585 is an IQ demodulator designed for high RF Input Port dynamic range receiver applications. It consists of RF Figure 4 shows the demodulator’s RF input which consists transconductance amplifiers, I/Q mixers, quadrature LO of an integrated transformer and high linearity transcon- amplifiers, IIP2 and DC offset correction circuitry, and ductance amplifiers (V-I converters). The primary side bias circuitry. of the transformer is connected to the RF input pin. The Operation secondary side of the transformer is connected to the

As shown in the Block Diagram for the LTC5585, the RF C18 LTC5585 1000pF BIAS signal is applied to the inputs of the RF transconductor RF L6 RF INPUT V-to-I converters and is then demodulated into I/Q (MATCHED) C17 C19 baseband signals using quadrature LO signals which are internally generated by a precision 90° phase shifter. The demodulated I/Q signals are lowpass filtered on-chip with a –3dB bandwidth of 530MHz. The differential outputs of 5585 F04 the I-channel and Q-channel are well matched in amplitude GND and their phases are 90° apart. Figure 4: Simplified Schematic of the RF Pin Interface

5585f 18 LTC5585 APPLICATIONS INFORMATION differential inputs of the transconductance amplifiers. Table 1. RF Input Impedance External DC voltage should not be applied to the RF input FREQUENCY S11 pin. DC current flowing into the primary side of the trans- (MHz) INPUT IMPEDANCE (Ω) MAG ANGLE (°) former may cause damage to the integrated transformer. 400 6.98 + j25.09 0.800 125.98 A series DC blocking capacitor should be used to couple 600 10.43 + j39.74 0.775 101.55 the RF input pin to the RF signal source. 800 16.76 + j56.73 0.751 80.01 1000 28.55 + j77.15 0.727 61.05 The RF input port can be externally matched over the 1200 51.47 + j101.03 0.706 44.29 operating frequency range with simple L-C matching. An 1400 96.49 + j122.28 0.686 29.33 input return loss better than 10dB can be obtained over a 1600 171.91 + j112.37 0.667 15.81 bandwidth of better than 16% with this method. Figure 5 1800 229.92 + j30.89 0.648 3.45 shows the RF input return loss for various matching com- 2000 202.21 – j58.84 0.630 –8.00 ponent values. Table 1 shows the impedance and input 2200 145.32 – j91.23 0.612 –18.71 reflection coefficient for the RF input without using any 2400 104.82 – j91.69 0.594 –28.49 external matching components. The input transmission 2600 78.33 – j83.38 0.575 –38.22 line length is de-embedded from the measurement. 2800 61.86 – j73.64 0.557 –47.49 3000 51.27 – j64.65 0.538 –56.32 5 3200 43.83 – j56.56 0.519 –65.15 TC = 25°C 0 3400 38.86 – j49.72 0.500 –73.40 3600 35.17 – j43.6 0.481 –81.68 –5 3800 32.46 – j38.21 0.463 –89.79 –10 4000 30.48 – j33.41 0.444 –97.76

–15 C18 LTC5585

RETURN LOSS (dB) L7 L6 –20 1000pF 3.9nH 8.2nH BIAS RF INPUT RF 1500MHz TO –25 2200MHz C17 C19 1.2pF 0.5pF –30 0 0.5 1 1.5 2 2.5 33.5 4 4.5 5

FREQUENCY (GHz) 5585 F05 L6 = 2.7pF, C19 = 1pF

L6 = 4.7nH, C19 = 0.5pF 5585 F06 C17 = 1.5pF, L6 = 4.7nH, C19 = 0.5pF GND C17 = 0.5pF, L6 = 2.7nH Figure 6. Wide Bandwidth RF Input Match Figure 5. RF Input Return Loss 0 Larger bandwidths can be obtained by using multiple L-C sections. For example Figure 6 shows a 2-section L-C –5 match having a bandwidth of about 38% where return loss is >10dB. Figure 7 shows the RF input return loss –10 for the wide bandwidth match. RETURN LOSS (dB) Broadband Performance –15 TC = 25°C L7 = 3.9nH, C17 = 1.2pF To get an idea of the broadband performance of the L6 = 8.2nH, C19 = 0.5pF –20 LTC5585, a 6dB pad can be put on the RF and LO ports, 0 0.5 1 1.5 2 2.5 3 3.5 4 and the ports can be left unmatched. The measured RF FREQUENCY (GHz) performance for this configuration is shown in Figures 8, 5585 F07 9, 10 and 11 with the 6dB pad de-embedded. The RF Figure 7. RF Input Return Loss for Wideband Match 5585f 19 LTC5585 APPLICATIONS INFORMATION

50 30 I, –40°C Q, –40°C 28 I, –40°C Q, –40°C 46 I, 25°C Q, 25°C 26 I, 25°C Q, 25°C I, 85°C Q, 85°C 24 I, 85°C Q, 85°C 42 I, 105°C Q, 105°C I, 105°C Q, 105°C 22 38 20 18 34 IIP3 16 NF 14 30 12 26 10 GAIN, NF (dB) 8 IIP3, P1dB (dBm) 22 6 P1dB 4 GAIN 18 2 14 0 –2 10 –4 400 900 1400 1900 2400 2900 3400 3900 900 1400 1900 2400 2900 3400 3900 LO FREQUENCY (MHz) LO FREQUENCY (MHz)

5585 F08 5585 F10

Figure 8. Broadband IIP3 and IP1dB Figure 10. Broadband NF and Gain

130 100 I, –40°C Q, –40°C TC = –40°C 120 I, 25°C Q, 25°C 90 TC = 25°C I, 85°C Q, 85°C T = 85°C 110 I, 105°C Q, 105°C C 80 TC = 105°C 100 90 70 80 60

IIP2 (dBm) 70 50 60 IMAGE REJECTION (dB) 40 50 40 30 30 20 400 900 1400 1900 2400 2900 3400 3900 500 1000 1500 2000 2500 3000 3500 4000 LO FREQUENCY (MHz) LO FREQUENCY (MHz)

5585 F09 5585 F11 Figure 9. Broadband IIP2 Figure 11. Broadband Image Rejection tone spacing is 1MHz, and fLO is 10MHz lower than fRF. The differential LO input impedance and S parameters with The conversion gain is lower than under the impedance the input transmission lines and balun de-embedded are matched condition, and correspondingly the P1dB, IIP3, listed in Table 2. and NF are higher. As shown, the part can be used at Figure 13 shows LO input return loss using the ANAREN frequencies outside its specified operating range with BD0826J50200A00 4:1 balun with various matching reduced conversion gain and higher NF. component values. LO Input Port For optimum IIP2 and large-signal NF performance the LO The demodulator’s LO input interface is shown in Fig- inputs should be driven differentially with a 4:1 balun such ure 12. The input consists of a high precision quadrature as the ANAREN BD0826J50200A00 or BD2425J50200AHF. phase shifter which generates 0° and 90° phase shifted As shown in Figure 14, the LO input can also be driven + or LO– input. The unused LO signals for the LO buffer amplifiers to drive the I/Q single-ended from either the LO port should be DC-blocked and terminated with a 50Ω load. mixers. DC blocking capacitors are required on the LO+ and LO– inputs. Figure 15 compares the uncalibrated IIP2 performance of single ended versus differential LO drive. 5585f 20 LTC5585 APPLICATIONS INFORMATION

VCC

LTC5585 TO IDENTICAL Q-CHANNEL C37 ANAREN 1000pF LO L5 BD0826J50200A00 LO+ INPUT (MATCHED) C14 C13 LO–

C36 PHASE SHIFTER 1000pF

5585 F12 GND

Figure 12. Simplified Schematic of LO Input Interface with External Matching Components

Table 2. LO Input Impedance (Differential) 5 FREQUENCY S11 0 (MHz) INPUT IMPEDANCE (Ω) MAG ANGLE (°) 400 118.18 – j120.02 0.668 –24.89 –5 600 94.18 – j99.93 0.623 –31.42 –10 800 78.00 – j85.06 0.583 –38.17 –15 1000 67.21 – j73.16 0.544 –44.79

1200 59.71 – j63.49 0.507 –51.25 RETURN LOSS (dB) –20 L5 = 12nH, C14 = 5.6pF 1400 54.22 – j55.46 0.471 –57.63 –25 L5 = 0.8pF, C13 = 5.1nH L5 = 5.1nH, C14 = 0.7pF 1600 50.06 – j48.59 0.437 –64.02 L5 = 1.2nH, C14 = 1pF –30 1800 46.80 – j42.69 0.405 –70.49 0 0.5 1 1.5 2 2.5 33.5 4 4.5 5 FREQUENCY (GHz) 5585 F13 2000 44.10 – j37.42 0.374 –77.28 2200 41.86 – j32.61 0.345 –84.47 Figure 13. LO Input Return Loss 2400 39.98 – j28.16 0.317 –92.21 2600 38.39 – j23.98 0.291 –100.65 2800 37.05 – j20.01 0.267 –109.95 3000 35.92 – j16.21 0.246 –120.29 3200 34.99 – j12.53 0.228 –131.76 3400 34.22 – j8.95 0.214 –144.37 3600 33.61 – j5.45 0.206 –157.88 3800 33.15 – j2.0 0.204 –171.85 4000 32.82 + j1.4 0.208 174.35

5585f 21 LTC5585 APPLICATIONS INFORMATION

VCC

LTC5585 TO IDENTICAL Q-CHANNEL C37 1000pF LO L5 LO+ INPUT (MATCHED) C14 C13 50Ω LO–

C36 PHASE SHIFTER 1000pF

5585 F14 GND

Figure 14. Recommended Single-Ended LO Input Configuration

100 TC = 25°C are required. Each single-ended output has an impedance 90 of 100Ω in parallel with a 6pF internal capacitor. With an

80 external 100Ω pull-up resistor this forms a lowpass filter with a –3dB corner frequency at 530MHz. The outputs 70 can be DC coupled or AC coupled to external loads. The 60 voltage conversion gain is reduced by the external load by: IIP2 (dBm)

50  1 50Ω  20Log + dB 40 10  2 R ||R   PULL-UP LOAD(SE)  30 400 900 1400 1900 2400 2900 3400 3900 LO FREQUENCY (MHz) 5585 F15 when the output port is terminated by RLOAD(SE). For in- SINGLE-ENDED LO, I SIDE stance, the gain is reduced by 6dB when each output pin is DIFFERENTIAL LO, I SIDE SINGLE-ENDED LO, Q SIDE connected to a 50Ω load (or 100Ω differentially). The output DIFFERENTIAL LO, Q SIDE should be taken differentially (or by using differential-to- Figure 15. Broadband IIP2 with Differential single-ended conversion) for best RF performance, includ- and Single-Ended LO Drive ing NF and IIP2. When no external filtering or matching components are used, the output response is determined I-Channel and Q-Channel Outputs by the loading capacitance and the total resistance loading the outputs. The –3dB corner frequency, fC, is given by The phase relationship between the I-channel output the following equation: signal and the Q-channel output signal is fixed. When the –1 LO input frequency is higher (or lower) than the RF input fC = [2π(RLOAD(SE)||100Ω||RPULL-UP) (6pF)] frequency, the Q-channel outputs (Q+, Q–) lead (or lag) Figure 16 shows the actual measured output response the I-channel outputs (I+, I–) by 90°. with various load resistances. Each of the I-channel and Q-channel outputs is internally Figure 17 shows a simplified model of the I, Q outputs connected to VCC through a 100Ω resistor. In order to main- with a 100Ω differential load and 100Ω pull-ups. The –1dB tain an output DC bias voltage of VCC – 1.5V, external 100Ω bandwidth in this configuration is about 520MHz, or about pull-up resistors or equivalent 15mA DC current sources twice the –1dB bandwidth with no load.

5585f 22 LTC5585 APPLICATIONS INFORMATION

5 Figure 18 shows a simplified model of the I, Q outputs 4 TC = 25°C 3 with a L-C matching network for bandwidth extension. 2 Capacitor CS serves to filter common mode LO switching 1 0 noise immediately at the demodulator outputs. Capacitor –1 C in combination with inductor L is used to peak the –2 C S –3 output response to give greater bandwidth of 650MHz. In –4 this case, capacitor C was chosen as a common mode –5 C

CONVERSION GAIN (dB) –6 capacitor instead of a differential mode capacitor to increase RLOAD(DIFF) = 100Ω, BW = 850MHz –7 RLOAD(DIFF) = 200Ω, BW = 630MHz –8 rejection of common mode LO switching noise. RLOAD(DIFF) = 400Ω, BW = 530MHz –9 RLOAD(DIFF) = 1k, BW = 460MHz –10 When AC output coupling is used, the resulting highpass 0 0.10.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

BASEBAND FREQUENCY (GHz) 5585 G16 filter’s –3dB roll-off frequency, fC, is defined by the R-C constant of the external AC coupling capacitance, CAC, and Figure 16. Conversion Gain Baseband Output Response with the differential load resistance, RLOAD(DIFF): RLOAD(DIFF) = 100Ω, 200Ω, 400Ω and 1k and RPULL-UP = 100Ω –1 fC = [2π • RLOAD(DIFF) • CAC]

VCC

LTC5585 VCC

PACKAGE 6pF 100Ω 100Ω 6pF PARASITICS RPULL-UP RPULL-UP 1.5nH I+ 100Ω 100Ω

1k 1.5nH I– RLOAD(DIFF) 100Ω 0.2pF 0.2pF –1dB BW = 520MHz 30mA AC CURRENT 30mA SOURCE

5585 F17 GND Figure 17. Simplified Model of the Baseband Output

VCC

LTC5585 VCC CS PACKAGE 2pF 6pF 100Ω 100Ω 6pF CC PARASITICS LS RPULL-UP RPULL-UP 10nH 4pF 1.5nF I+ 100Ω 100Ω 1k 1.5nF – L R I S 6mA MAX DC LOAD(DIFF) 10nH 100Ω 0.2pF 0.2pF C C S C LOWPASS 2pF 4pF 30mA DC AC CURRENT 30mA DC –1dB BW = 650MHz SOURCE

5585 F18 GND

Figure 18. Simplified Model of the Baseband Output Showing Bandwidth Extension with External L, C Matching

5585f 23 LTC5585 APPLICATIONS INFORMATION Care should be taken when the demodulator’s outputs As shown in Figure 21, the REF pin is similar to the DCOI are DC coupled to the external load to make sure that the pin, but the bias current source is 250µA, and the inter- I/Q mixers are biased properly. If the current drain from nal resistance is 2k. If this pin is left disconnected, it will the outputs exceeds about 6mA, there can be significant self-bias to 500mV. A low impedance voltage source with degradation of the linearity performance. Keeping the com- a source resistance of less than 200Ω is recommended mon mode output voltage of the demodulator above 3.15V, to drive this pin. The control voltage range of the DCOI, with a 5V supply, will ensure optimum performance. Each DCOQ, IP2I and IP2Q pins is set by the REF pin. This range output can sink no more than 30mA when the outputs are is equal to 0V to twice the voltage on the REF pin, whether connected to an external load with a DC voltage higher internally or externally applied. – 1.5V. than VCC It is recommended to decouple any AC noise present on In order to achieve the best IIP2 performance, it is im- the signal lines that connect to the analog control-voltage portant to minimize high frequency coupling among the inputs. A shunt capacitor to ground placed close to these baseband outputs, RF port, and LO port. Although it may pins can provide adequate filtering. For instance, a value increase layout complexity, routing the baseband output of 1000pF on the DCOI, DCOQ, IP2I and IP2Q pins will traces on the backside of the PCB can improve uncalibrated provide a corner frequency of around 6 to 7MHz. A similar IIP2 performance. Figure 19 shows the alternate layout corner frequency can be obtained on the REF pin with a having the baseband outputs on the backside of the PCB. value of 3900pF. Using larger capacitance values such as 0.1µF is recommended on these pins unless a faster control

VCC

LTC5585

62.5µA DCOI, DCOQ, IP2I, IP2Q 8k

5585 F20 GND

Figure 20. Simplified Schematic of the Interface for the DCOI, DCOQ, IP2I and IP2Q Pins

VCC

Figure 19. Alternate Layout of PCB with LTC5585 Baseband Outputs on the Backside

Analog Control Voltage Pins 250µA

Figure 20 shows the equivalent circuit for the DCOI, DCOQ, REF IP2I, and IP2Q pins. Internal temperature compensated 2k 62.5μA current sources keep these pins biased at a nominal

500mV through 8k resistors. A low impedance voltage 5585 F21 source with a source resistance of less than 200Ω is GND recommended to drive these pins. Figure 21. Simplified Schematic of the REF Pin Interface 5585f 24 LTC5585 APPLICATIONS INFORMATION response is needed. Figure 22 shows the input response DC Offset Adjustment Example –3dB bandwidth for the pins versus shunt capacitance Figure 23 shows a typical direct conversion receive path when driven from a 50Ω source. having a DSP feedback path for DC offset adjustment.

0 Any sources of LO leakage to the RF input of the LTC5585 TC = 25°C –1 demodulator will contribute to the DC offset of the receiver. –2 This includes both static and dynamic DC offsets. If the –3 coupling is static in nature due to fixed board-level leakage –4 paths, the resulting DC offset does not typically need to –5 be adjusted at a high repetition rate. Dynamic DC offsets –6

RESPONSE (dB) due to transmitter transient leakage or antenna reflection –7 can be much harder to correct for and will require a faster –8 DCOI, DCOQ; C = 470pF update rate from the DSP. –9 DCOI, DCOQ; C = 1000pF IP2I, IP2Q; C = 100pF –10 LO leakage into the RF port of the demodulator causes a 0 42 86 10 12 1416 18 20 DC offset at the baseband outputs which is then multiplied FREQUENCY (MHz) 5585 F22 by the gain in the baseband path. The usable ADC voltage Figure 22. Input Response Bandwidth for the window will be reduced by the amplified DC offset, resulting DCOI, DCOQ, IP2I and IP2Q Pins in lower dynamic range. Using DSP, this DC offset value can be averaged and sampled at a given update rate and then a 1D minimization algorithm can be applied before DC Offset Adjustment Circuitry a new DCOI or DCOQ control signal is generated to mini- Any sources of LO leakage to the RF input of a direct mize the offset. The 1-D minimization algorithm can be conversion receiver will contribute to the DC offsets of implemented in many ways such as golden-section search, its baseband outputs. The LTC5585 features DC offset backtracking, or Newton’s method. adjustment circuitry to reduce such effects. When the EDC pin is a logic high the circuitry is enabled and the IM2 Adjustment Circuitry resulting DC offset adjustment range is typically ±20mV. The LTC5585 also contains circuitry for the independent In a typical direct conversion receiver application, DC adjustment of IM2 levels on the I and Q channels. When offset calibration will be done periodically at a time when the EIP2 pin is a logic high, this circuitry is enabled and no receive data is present and when the receiver DC levels the IP2I and IP2Q analog control voltage inputs are able have sufficiently settled.

DSP 1-D DAC MINIMIZATION DC ALGORITHM AVERAGING LOWPASS BPF DCOI FILTER SAMPLE AND LNA ADC HOLD LTC5585 fLO = 1950MHz 5585 F23

Figure 23. Block Diagram of a Receiver with a DSP Feedback Loop for DC Offset Adjustment

5585f 25 LTC5585 APPLICATIONS INFORMATION to adjust the IM2 level. The IM2 level can be effectively output voltage will be equal to VCC (if no DC common mode minimized over a large range of the baseband bandwidth. current is being drawn by external baseband circuitry such The circuitry has an effective baseband frequency upper as a baseband amplifier). When the chip is enabled, the limit of about 200MHz. Any IM2 component that falls in this off-chip common mode decouping capacitor must charge frequency range can be minimized. Beyond this frequency, up through a 500Ω resistor. The time constant for this is the gain of the IM2 correction amplifier falls off appreciably essentially 500Ω times the common mode decoupling and the circuit no longer improves IP2 performance. The capacitance value. For example, with a 0.01µF capacitor lower baseband frequency limit of the IM2 adjustment this wait time is approximately 30μs. Figure 26 shows circuitry is set by the common mode reference decoupling the pulsed enable response of the common-mode output capacitor at the CMI and CMQ pins. Below this frequency voltage with 0.01µF on the CMI and CMQ pins. the circuit can not minimize the IM2 component. 130 Figure 24 shows the CMI (and identical CMQ) pin interface. 0.1µF (UNCALIBRATED) 120 0.1µF (NULLED IP2I = 0.1V) These pins have an internal 40pF decoupling capacitance 1500pF (UNCALIBRATED) 110 1500pF (NULLED IP2I = 0.15V) to VCC, to provide a reference for the IP2 adjustment cir- 100 TC = 25°C cuitry. The lower 3dB frequency limit, f , of the circuitry f = 2150MHz C 90 RF1 fLO = 2100MHz is set by the following equation: 80

–1 IIP2 (dBm) fC = [2π • 500(40pF + CCM(EXT))] 70 60 Without any external capacitor on the CMI or CMQ pin the 50 lower limit is 8MHz. By adding a 0.1μF capacitor, CCM(EXT), 40 between the CMI and CMQ pins to VCAP, the lower –3dB 30 0.01 0.1 1 10 frequency corner can be reduced to 3kHz. Figure 25 shows RF FREQUENCY SPACING (MHz)

IIP2 as a function of RF frequency spacing versus common 5585 F25 mode decoupling capacitance values of 0.1µF and 1500pF. Figure 25. IIP2 vs Common Mode Decoupling Capacitance There is effectively no limit on the size of this capacitor, other than the impact it has on enable time for the IM2 8 10 circuitry to be operational. When the chip is disabled, there TC = 25°C CCMI,Q = 0.01µF is no current in the I or Q mixers, so the common mode 7 5

EN ENABLE VOLTAGE (V) PULSE EN PULSE ON V OFF CC 6 0

LTC5585 (V) CM

V V CAP 5 –5 40pF CMI, CMQ CMI OR CMQ 4 –10

BASEBAND OUTPUTS 3 –15 0 10 20 30 40 50 60 7080 90 100

5585 F24 TIME (µs)

GND 5585 F26

Figure 24. Equivalent Circuit of the CMI and CMQ Pin Interfaces Figure 26. Common Mode Output Voltage with a Pulsed Enable

5585f 26 LTC5585 APPLICATIONS INFORMATION IM2 Suppression Example Figures 29 and 30 show the simplified schematics for the IM2 adjustment circuitry can be used in a typical trans- EDC and EIP2 pins ceiver loop-back application as shown in Figure 27. In VCC this example a 2-tone SSB training source of f1 = 20MHz and f2 = 21MHz is generated in DSP and upconverted LTC5585 by the LTC5588-1 quadrature modulator to RF tones at EN 1970MHz and 1971MHz using an LO source at 1950MHz. 100k A narrowband RF filter is required to remove the IM2 component generated by the LTC5588-1. During the 100k loopback test these RF tones are routed through high isolation switches and an attenuation pad to the LTC5585 5585 F28 demodulator input. The tones are then downconverted by GND the same LO source at 1950MHz to produce two tones Figure 28. Simplified Schematic of the EN Pin Interface at the baseband outputs of 20MHz and 21MHz plus an IM2 impairment signal at 1MHz. After baseband chan- VCC nel filtering and amplification the output of the ADC is filtered by a 1MHz bandpass filter in DSP to isolate the LTC5585

IM2 tone. The power in this tone is calculated in DSP and EDC then a 1-D minimization algorithm is applied to calculate 100k the correction signal for the IP2I control voltage pin. The 1-D minimization algorithm can be implemented in many 100k ways such as golden-section search, backtracking or EN Newton’s method.

5585 F29 Enable Interface GND A simplified schematic of the EN pin is shown in Figure 28. Figure 29. Simplified Schematic of the EDC Pin Interface The enable voltage necessary to turn on the LTC5585 is 2V. To disable or turn off the chip, this voltage should be below 0.3V. If the EN pin is not connected, the chip is disabled.

DSP 1-D DAC MINIMIZATION ALGORITHM

IP2I 1MHz BPF LNA RMS ADC DETECTION LTC5585

LOOPBACK fLO = 1950MHz

f1 = 20MHz

DAC + PA f2 = 21MHz LTC5588-1

5585 F27

Figure 27. Block Diagram for a Direct Conversion Transceiver with IM2 Adjustment. Only the I-Channel Is Shown

5585f 27 LTC5585 APPLICATIONS INFORMATION

VCC VCC

LTC5585 LTC5585 100Ω EIP2 VBIAS 100k OPTIONAL R 10k TO REDUCE COPT EN CURRENT 100k

5585 F30 GND

5585 F31 Figure 30. Simplified Schematic of the EIP2 Pin Interface GND

It is important that the voltage applied to the EN, EDC and Figure 31. Simplified Schematic of the VBIAS Pin Interface EIP2 pins should never exceed VCC by more than 0.3V. Otherwise, the supply current may be sourced through the 50 upper ESD protection diode connected at the pin. Under I, 190mA Q, 190mA 45 I, 170mA, 487Ω Q, 170mA, 487Ω no circumstances should voltage be applied to the enable I, 150mA, 294Ω Q, 150mA, 294Ω pins before the supply voltage is applied to the VCC pin. If 40 TC = 25°C fRF = 1950MHz this occurs, damage to the IC may result. 35 30 Figure 31 shows the simplified schematic of the VBIAS IIP3 25 interface. The VBIAS pin can be used to lower the mixer

IIP3, P1dB (dBm) 20 core bias current and total power consumption for the P1dB 15 chip. For example, adding 1kΩ from the VBIAS pin to GND will lower the DC current to 150mA, at the expense 10 5 of reduced IIP3 performance. Figure 32 shows IIP3 and 1500 1600 1700 1800 1900 2000 2100 2200 P1dB performance versus DC current and resistor value. LO FREQUENCY (MHz) An optional capacitor, COPT in Figure 31, has minimal effect 5585 G21 on improving PSRR and IIP2. Figure 32. IIP3 and P1dBm vs DC Current and VBIAS Resistor Value 1950MHz Receiver Application slope with frequency is necessary to compensate for the Figure 33 shows a typical receiver application consisting of roll-off contributed by the ADC Driver and Anti-Alias Filter. the chain of LNA, demodulator, lowpass filter, ADC driver, From the chain analysis shown in Figure 34, the IIP3-NF and ADC. Total DC power consumption is about 2.1W. dynamic range figure of merit (FOM) is 4.3dB at the LNA Full-scale power at the RF input is -6dBm. The Chebychev input, 7.5dB at the demodulator input, and 14.85dB at the lowpass filter with unequal terminations is designed us- ADC driver amp input. ing the method shown in the appendix. Filter component values are then adjusted for the best overall response The measured 6th order lowpass baseband response is and available component values. A positive voltage gain shown in Figure 35.

5585f 28 LTC5585 APPLICATIONS INFORMATION • • • D0 D13 CONTROL DD ADC V 1.8V 206mA LTC2185 – + IN IN A A CM V C23 1µF R20 105Ω R19 105Ω 5585 F33 R17 R18 83Ω 83Ω C21 62pF C22 62pF L11 180nH L12 180nH R16 35Ω R15 35Ω 40MHz ANTI-ALIAS FILTER R14 R13 138Ω 138Ω R10 100Ω L9 180nH L10 180nH R12 R11 10Ω 10Ω R8 R9 440Ω 440Ω LTC6409 – + 5V 52mA C19 C20 OCN 0.4pF 0.4pF + – V R6 R7 30Ω 30Ω R5 110Ω C18 0.1µF R4 C16 150pF C15 150pF 110Ω C14 150pF C13 150pF L7 180nH L8 180nH C17 1µF 40MHz LOWPASS FILTER 40MHz LOWPASS C9 47pF C12 47pF L5 470nH L6 470nH C10 100pF T1 ANAREN BD2425J50200AHF – + – I I LO CC 5V V 200mA + LTC5585 C8 0.5pF LO RF Figure 33. Simplified Schematic of 1950MHz Receiver, (Only I-Channel is Shown) Figure 33. Simplified Schematic of 1950MHz Receiver, C11 C7 0.5pF 100pF L4 4.7nH C6 4.7µF C4 100pF L3 4.7nH 6dBm L2 8.2nH R3 0Ω C2 1950MHz LO INPUT 100pF 5V 48mA AVAGO R2 MGA-634P8 5.6k LNA BIAS R1 49.9Ω L2 C1 100pF 8.2nH TO C3 4.7µF C5 100pF 1910MHz 1990MHz RF INPUT

5585f 29 LTC5585 APPLICATIONS INFORMATION

1950MHz Receiver Chain Analysis G = 32.6dB G = 15.2dB G = 21.5dB G = 21.8dB G = –1.2dB G = 0dB NF = 3.7dB NF = 18.3dB NF = 10.85dB NF = 10.55dB NF = 24.3dB NF = 23.1dB IIP3 = 8dBm IIP3 = 25.8dBm IIP3 = 25.7dBm IIP3 = 25.4dBm IIP3 = 48.7dBm IIP3 = 47.5dBm FOM = 4.3dB FOM = 7.5dB FOM = 14.85dB FOM = 14.85dB FOM = 24.4dB FOM = 24.4dB

MGA-634P8 LTC5585 40MHz LPF LTC6409 40MHz AAF LTC2185

G = 17.4dB G = –6.3dB G = –0.3dB G = 23dB G = –1.2dB G = 0dB NF = 0.44dB NF = 13dB NF = 0.3dB NF = 10dB NF = 1.2dB NF = 23.1dB OIP3 = 36dBm IIP3 = 27dBm OIP3 = 50dBm IP3 = 47.5dBm 5585 F34

Figure 34. 1950MHz Receiver Chain Analysis

20 TC = 25°C For this example, receiver noise floor is approximated 10 by a measurement at 845MHz, where adequate filtering 0 for RF and LO signals was possible. Using the test data –10 from Figure 37, the receiver noise figure for the I-channel –20 –30 (Ch 1) is calculated using the –6dBm input power, 15kHz

GAIN (dB) –40 bin width, 40MHz bandwidth, and –116.3dBFS measured –50 in-band noise floor: –60 SNRIN = PIN – P0 –70 –80 SNRIN = – 6 – (–174 + 76) = 92dB 0 2040 60 80 100 120 140 160 FREQUENCY (MHz) SNROUT = –10 Log10(BinW/BW) – Floor 5585 F35 SNROUT = –43.3 + 116.3 = 73dB Figure 35. Baseband Gain Response without LNA NF = SNRIN – SNROUT The receiver spurious free dynamic range (SFDR) in terms NF = 92 – 73 = 19dB of FOM can be calculated using the following equations: Finally, an approximate receiver spurious free dynamic FOM = IIP3 – NF range can be calculated using the measured data at 845MHz and 1910MHz: SFDR = 2/3(FOM – P0) SFDR = 2(IIP3 – NF – P0)/3 P0 = –174dBm + 10Log10(BW|Hz) SFDR = 2(21.78 – 19 – (–174 + 76))/3 where P0 is the input noise power and –174dBm is the input thermal noise power in a 1Hz bandwidth. A measured SFDR = 67.2dB (I-channel) 2-tone output spectrum at 1910MHz is shown in Figure 36. Measured IIP3 is 2.3dB higher for the Q-channel, so the IIP3 is calculated from the 2-tone IM3 levels: resulting SFDR is: IIP3 = (–7.067 – (–76.63))/2 – 13 SFDR = 68.7dB (Q-channel) IIP3 = 21.78dBm

5585f 30 LTC5585 APPLICATIONS INFORMATION

Figure 36. fRF = 1909MHz and 1910MHz 2-Tone Receiver Test, fLO = 1930MHz. Ch.1 is the I-Channel and Ch.2 is the Q-Channel. Tested without LNA

5585f 31 LTC5585 APPLICATIONS INFORMATION

Figure 37. fRF = 845MHz Receiver Noise Floor Test, fLO = 846MHz. Ch.1 is the I-Channel and Ch.2 is the Q-Channel. Tested without LNA

5585f 32 LTC5585 APPENDIX

Chebychev Filter Synthesis with Unequal where RIN is the input impedance and the terminating Terminations impedance ROUT is equal to RIN for the n odd case but is scaled by the g prototype value for the n even case. To synthesize Chebychev filters with unequal terminations, n+1 two equally terminated filters are synthesized at the two The Impedance Bisection Theorem can be applied to sym- different impedance levels and the resulting networks are metrical networks by dividing the element values along joined using the Impedance Bisection Theorem[1]. This the networks’ plane of symmetry, and then adding the method only works with symmetrical odd-order filters. The two networks together. The filter response is preserved. general lowpass prototype element values are generated For example, if L | = 0.2dB, f = 40MHz, R = 100Ω, by the method shown [2]: Ar dB C IN ROUT = 20Ω and n = 5, the prototype element values and  LAr |dB  resulting scaled filter values are listed: β =In coth   17.37  Filter 1: RIN = ROUT = 100Ω  β  g1 = 1.339 → C1 = 53.3pF γ = sinh   2n g2 = 1.337 → L1 = 531.98nH g = 2.166 → C2 = 86.19pF π()2k –1 3 ak = sin , k = 1,2,...,n g = 1.337 → L2 = 531.98nH 2n 4 g5 = 1.339 → C3 = 53.3pF 2 2 πk bk = γ +sin , k = 1,2,...,n Filter 2: RIN = ROUT = 20Ω n g = 1.339 → C1 = 266.48pF where LAr|dB is the passband ripple in dB, and n is the 1 filter order. g2 = 1.337 → L1 = 106.4nH The prototype element values will be: g3 = 2.166 → C2 = 430.93pF g4 = 1.337 → L2 = 106.4nH 2a1 g1 = γ g5 = 1.339 → C3 = 266.48pF The Impedance Bisection Theorem can be applied at the 4akak–1 gk = , k = 1,2,...,n plane of symmetry about C2 such that a new value of C2 bk−1gk−1 can be computed with half the values of the two filters. g = 1 for n odd 86.19pF 430.93pF n+1 C2→ + = 258.56pF 2 2 2  β  gn+1 = coth   for n even  4  The final unequally-terminated filter design values are shown in Figure 38. Assuming the first element is a capacitor, we can scale the RIN L1 L2 filter capacitor prototype values up to our desired cutoff 100Ω 531.98nH 106.4nH frequency fC: + C1 C2 C3 ROUT 53.3pF 258.56pF 266.48pF 20Ω gk – Ck = , k = 1,3,...,n 5585 F38 2π • fC •RIN Figure 38. Final Design Schematic The filter inductor values can be scaled with: [1] A.C. Bartlett, “An Extension of a Property of Artificial Lines,” Phil. Mag., vol.4, p.902, gk •RIN November 1927. LK = , k = 2,4,...,n [2] G. Matthaei, L. Young, and E.M.T. Jones, Microwave Filters, Impedance-Matching Networks, 2π • f and Coupling Structures, p.99, 1964. C 5585f 33 LTC5585 APPENDIX

Image Rejection Calculation We combine I(t) + Q–90(t) and choose terms containing as the desired signal: Image rejection can be calculated from the measured gain ωBB and phase error responses of the demodulator. Consider 1 AERR desired= sin()ωBBt + sin()ωBBt –φERR the signal diagram of Figure 39: 2 2

Similarly, we choose terms containing ωIM as the image AERR I(t) signal: 1 A LO (t) ERR I image = sin()ωIMt – sin()ωIMt+φERR RF(t) 2 2 LOQ(t) The image rejection ratio (IRR) can then be written as: Q(t) 5585 F39 |desired|2 IRR|dB = 10log 2 Figure 39. Signal Diagram for a Demodulator |image| where: Written in terms of AERR and φERR as: RF(t) = sin(ωLO + ωBB)t + sin(ωLO – ωIM)t 2 |1+ AERR +2AERR cos()φERR | IRR|dB = 10log LOI(t) = cos(ωLOt + φERR) |1 A 2 + ERR −2AERR cos()φERR | LO (t) = sin(ω t) Q LO Figure 40 shows image rejection as a function of amplitude ωLO + ωBB is the desired sideband frequency and and phase errors for a demodulator. ωLO – ωIM is the image frequency. The total phase error 70 of the I and Q channels is lumped into the I-channel LO AERR = 0dB AERR = 0.05dB source as φERR. The total gain error is represented by 60 AERR = 0.1dB AERR = 0.2dB AERR, and is lumped into a gain multiplier in the I-channel. AERR = 0.3dB 50 AERR = 0.5dB After lowpass filtering the I and Q signals can be written as: AERR = 1dB 40 AERR I(t)= sin()ωBBt –φERR –sin()ωIMt+φERR  2   30 IMAGE REJECTION (dB) 1 20 Q(t)= cos()ωBBt +cos()ωIMt  2 10 10 23 4 5 6 7 8 9 10 Shifting the Q channel by –90° can be accomplished by PHASE ERROR (DEG) replacing sine with cosine such that the shifted Q-channel 5585 F40 signal is: Figure 40. Image Rejection as a Function of Gain and Phase Errors 1 Q–90(t)= sin()ωBBt +sin()ωIMt  2

5585f 34 LTC5585 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

UF Package 24-Lead Plastic QFN (4mm × 4mm) (Reference LTC DWG # 05-08-1697)

0.70 ±0.05

4.50 ±0.05 2.45 ±0.05 3.10 ±0.05 (4 SIDES)

PACKAGE OUTLINE

0.25 ±0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS BOTTOM VIEW—EXPOSED PAD PIN 1 NOTCH R = 0.20 TYP OR 4.00 ±0.10 0.75 ±0.05 R = 0.115 0.35 × 45 CHAMFER TYP (4 SIDES) 2423

PIN 1 0.40 ±0.10 TOP MARK (NOTE 6) 1 2

2.45 ±0.10 (4-SIDES)

(UF24) QFN 0105 0.200 REF 0.25 ±0.05 0.00 – 0.05 0.50 BSC NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

5585f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. 35 LTC5585 TYPICAL APPLICATION Simplified Schematic of 1950MHz Receiver, (Only I-Channel Is Shown)

C19 0.4pF 40MHz LOWPASS FILTER 40MHz ANTI-ALIAS FILTER (AAF) C17 R8 5V R4 R5 1µF 110Ω 110Ω 440Ω R14 R17 200mA 138Ω 83Ω 1.8V 5V 206mA C9 C14 C16 R6 52mA R12 R15 C21 47pF 150pF 150pF VCC 30Ω 10Ω 35Ω 62pF VDD + + RF INPUT LTC5585 I – + AIN D13 L3 4.7nH L5 470nH L7 180nH L9 180nH L11 180nH • 1910MHz R7 R11 LTC2185 RF VOCMLTC6409 VCM • TO C7 L6 470nH L8 180nH 30Ω 10Ω L10 180nH L12 180nH ADC • – – D0 1990MHz C2 0.5pF I + – AIN + – C12 C13 C15 C22 100pF LO LO C18 R16 R19 R20 47pF 150pF 150pF R13 62pF R18 0.1µF R9 138Ω 35Ω 83Ω 105Ω 105Ω C11 C10 440Ω C23 100pF 100pF C20 1µF CONTROL 0.4pF T1 LO INPUT L4 4.7nH R10 ANAREN BD2425J50200AHF 1950MHz 100Ω 6dBm C8 5585 TA02 0.5pF

RELATED PARTS PART NUMBER DESCRIPTION COMMENTS Infrastructure LTC5569 300MHz to 4GHz Dual Active Downconverting Mixer 2dB Gain, 26.7dBm IIP3 and 11.7dB NF at 1950MHz, 3.3V/180mA Supply LT5527 400MHz to 3.7GHz, 5V Downconverting Mixer 2.3dB Gain, 23.5dBm IIP3 and 12.5dB NF at 1900MHz, 5V/78mA Supply LT5557 400MHz to 3.8GHz, 3.3V Downconverting Mixer 2.9dB Gain, 24.7dBm IIP3 and 11.7dB NF at 1950MHz, 3.3V/82mA Supply LTC6409 10GHz GBW Differential Amplifier DC-Coupled, 48dBm OIP3 at 140MHz, 1.1nV/√Hz Input Noise Density LTC6412 31dB Linear Analog VGA 35dBm OIP3 at 240MHz, Continuous Gain Range –14dB to 17dB LTC554X 600MHz to 4GHz Downconverting Mixer Family 8dB Gain, >25dBm IIP3, 10dB NF, 3.3V/200mA Supply LT5554 Ultralow Distortion IF Digital VGA 48dBm OIP3 at 200MHz, 2dB to 18dB Gain Range, 0.125dB Gain Steps LT5578 400MHz to 2.7GHz Upconverting Mixer 27dBm OIP3 at 900MHz, 24.2dBm at 1.95GHz, Integrated RF Transformer LT5579 1.5GHz to 3.8GHz Upconverting Mixer 27.3dBm OIP3 at 2.14GHz, NF = 9.9dB, 3.3V Supply, Single-Ended LO and RF Ports LTC5590 Dual 600MHz to 1.7GHz Downconverting Mixer 8.7dB Gain, 26dBm IIP3, 9.7dB Noise Figure LTC5591 Dual 1.3GHz to 2.3GHz Downconverting Mixer 8.5dB Gain, 26.2dBm IIP3, 9.9dB Noise Figure LTC5592 Dual 1.6GHz to 2.7GHz Downconverting Mixer 8.3dB Gain, 27.3dBm IIP3, 9.8dB Noise Figure RF PLL/Synthesizer with VCO LTC6946-1 Low Noise, Low Spurious Integer-N PLL with 373MHz to 3.74GHz, –157dBc/Hz WB Phase Noise Floor, –100dBc/Hz Closed-Loop Integrated VCO Phase Noise LTC6946-2 Low Noise, Low Spurious Integer-N PLL with 513MHz to 4.9GHz, –157dBc/Hz WB Phase Noise Floor, –100dBc/Hz Closed-Loop Integrated VCO Phase Noise LTC6946-3 Low Noise, Low Spurious Integer-N PLL with 640MHz to 5.79GHz, –157dBc/Hz WB Phase Noise Floor, –100dBc/Hz Closed-Loop Integrated VCO Phase Noise ADCs LTC2145-14 14-Bit, 125Msps 1.8V Dual ADC 73.1dB SNR, 90dB SFDR, 95mW/Ch Power Consumption LTC2185 16-Bit, 125Msps 1.8V Dual ADC 76.8dB SNR, 90dB SFDR, 185mW/Channel Power Consumption

LTC2158-14 14-Bit, 310Msps 1.8V Dual ADC, 1.25GHz Full-Power 68.8dB SNR, 88dB SFDR, 362mW/Ch Power Consumption, 1.32VP-P Input Range Bandwidth

5585f Linear Technology Corporation LT 0112 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 36 ● ● (408) 432-1900 FAX: (408) 434-0507 www.linear.com  LINEAR TECHNOLOGY CORPORATION 2012