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Design of Analog Baseband Circuits for Wireless Communication Receivers Design of Analog Baseband Circuits for Wireless Communication Receivers DISSERTATION Presented in Partial Fulfillment of the Requirements for the Degree Doctor of Philosophy in the Graduate School of The Ohio State University By Seoung Jae Yoo, B.S., M.S. ***** The Ohio State University 2004 Dissertation Committee: Approved by Mohammed Ismail ElNaggar, Adviser Joanne E. DeGroat Adviser Furrukh Khan Department of Electrical Engineering c Copyright by Seoung Jae Yoo 2004 ABSTRACT This dissertation describes the design and implementation of analog baseband filter and variable gain amplifiers (VGA) for wireless communication receivers. Since discrete high-Q image rejection and IF filters are eliminated, fully integrated receiver architecture demands baseband filters and VGAs which exhibit high linearity and wide dynamic range. In this dissertation, baseband chains for WLAN receivers and base station application, and low voltage transresistance based filter and VGA are presented. For WLAN receiver, three different baseband chains are introduced in chapter 3. First baseband chain is designed based on the feed forward compensated amplifier. Since the amplifier demonstrates high gain bandwidth and phase margin, the opera- tion of filter is not affected by phase error and finite gain bandwidth of the amplifier. The feedforward compensated amplifier based filter and VGA are fabricated in 0.5µ CMOS technology and measured. Second baseband chain is designed based on fully differential buffer. The fully differential buffer shows the characteristics such as wide bandwidth, low output impedance, and high linearity, which are required in the design of wideband filter. Since identical buffer circuits are applied for the design of filter and VGA, design and optimization time are saved. This baseband chain is fabricated in 0.18 µ CMOS technology and test results are presented. Third baseband chain is designed based on the differential difference amplifier(DDA) and folded cascode ii amplifier. The DDA is used to implement wide band width buffer and folded cascode amplifier is used to design variable gain amplifier. The VGA of this baseband chain is fabricated in 0.5 µ CMOS technology and tested. In chapter 4, the band pass filter and VGA for basestation are presented. Since base station requires strong linearity and power compression behavior, the baseband chain must demonstrate high linearity and wide dynamic range. To achieve required linearity, power consumption is increased and the use of nonlinear components is minimized. Seven filter blocks and five attenuators are cascaded for the realization of the baseband chain. The baseband chain is fabricated in 0.5 µ CMOS technology. Finally, in chapter 5, the design of low voltage transresistance amplifier is pre- sented. The amplifier is operated with 1.8 V supply in 5 V CMOS technology. The amplifier is implemented to design Tow-Thomas filter and R2R ladder based VGA. The amplifier and VGA are fabricated in 0.5 µ CMOS technology and tested. iii This is dedicated to my wife and my parents iv ACKNOWLEDGMENTS I would like to express my utmost thanks and gratitude to Dr. Mohammed Ismail for providing an opportunity to perform research at Analog VLSI lab., The Ohio State University. Without his guidance, this dissertation would not have been possible. He has helped me earn a lot of knowledge, and has given me confidence in my field of study. I would alos like to thank Prof. Joanne E. DeGroat and Prof. Furrukh Khan for being part of my candidacy examination and Ph. D. dissertation committee. I especially appreciate my wife and parents, who always support me and have made great sacrifice during my study. Without their support and sacrifice, I would not be able to finish my study. I would like to thank my colleagues at Analog VLSI Lab. I appreciate their support and suggestions on my work. v VITA March 6, 1971 ..............................Born - Seoul, Korea March, 1994 - June, 1998 ...................B.S. Electrical Engineering, The Ohio State University, Columbus, Ohio June, 1998 - June, 2000 .....................M.S. Electrical Engineering, The Ohio State University, Columbus, Ohio July, 2000 - Present ........................ Ph. D. Electrical Engineering, The Ohio State University, Columbus, Ohio January, 2000 - June, 2001 ..................Industrial Fellowship, by Nokia, Inc., Helsinki, Finland July, 2001 - Present ........................ Graudate Research Assistant, The Ohio State University, Columbus, Ohio FIELDS OF STUDY Major Field: Electrical Engineering Studies in Analog Microelectronics and IC Design: vi TABLE OF CONTENTS Page Abstract....................................... ii Dedication...................................... iv Acknowledgments.................................. v Vita ......................................... vi ListofTables.................................... x ListofFigures ................................... xi Chapters: 1. Introduction.................................. 1 1.1 Motivation ............................... 1 1.2 Analog Baseband Filter and VGA in Wireless Communication... 3 1.3 Channel Select Filtering and Tradeoffs . 5 1.4 OrganizationoftheDissertation . 7 2. Background.................................. 9 2.1 ReceiverArchitecture . 11 2.1.1 Superheterodyne receiver . 11 2.1.2 Direct Conversion Receiver . 14 2.1.3 Wide-BandIFreceiver. 18 2.1.4 DigitalIFreceivers. 20 2.2 ChannelSelectionFilters . 21 2.2.1 Channel Selection Filtering and ADC requirements . .. 22 2.3 CMOSContinuousTimeFilters. 27 vii 2.3.1 ActiveRCFilter ........................ 30 2.3.2 MOSFET-CFilter ....................... 33 2.3.3 OTA-Cfilter .......................... 37 2.3.4 Tuningoffilter ......................... 40 3. DesignofFilterandVGAforWLAN . 45 3.1 Feed forward compensated amplifier based filter and VGA for WLAN application ............................... 46 3.1.1 Feed forward compensation technique . 47 3.1.2 Feed-forward compensated differential difference amplifier (DDA) 50 3.1.3 DesignofactiveRCfilterandVGA. 54 3.1.4 TestResults........................... 59 3.2 Fully differential buffer based filter and VGA for WLAN application 66 3.2.1 Fullydifferentialbuffer. 67 3.2.2 DesignoftheWLANfilterandVGA . 70 3.2.3 Testresults ........................... 76 3.3 Folded cascode amplifier and DDA based WLAN VGA and filter . 84 3.3.1 Folded cascode amplifier and Fully differential buffer based onDDA............................. 84 3.3.2 DDA based filter and folded cascode amplifier based VGA . 89 3.3.3 Testresults ........................... 93 4. DesignofFilterandVGAforbasestation . 101 4.1 Thebasestationarchitectures. 103 4.2 DesignConsideration. 106 4.2.1 FilterandVGAStructure . 107 4.2.2 Trade off between Power consumption and dynamic range . 111 4.3 DesignofFilterandVGA . 116 4.3.1 Fully differential buffer without common mode feedback . 118 4.3.2 Designofthebandpassfilter . 120 4.3.3 Digitallyprogrammableattenuators . 123 4.4 TestResults............................... 125 5. Filter and VGA based on a Low Voltage Transresistance Amplifier. 136 5.1 Low Voltage Transresistance Amplifier . 137 5.2 Filter and Variable Gain Amplifier . 146 5.3 TestResults............................... 150 viii 6. Conclusions .................................. 158 Bibliography .................................... 163 ix LIST OF TABLES Table Page 2.1 Requirements to channel selection filtering . ..... 25 2.2 Attenuation of a W-CDMA signal at different offsets for low pass filters. 26 3.1 Test results of feed forward compensated amplifier based filter and VGA 66 3.2 The specification of the filter and VGA for Wireless LAN application 71 3.3 Test results of Fully differential buffer based filter and VGA ..... 84 3.4 TestresultsofthefilterandVGA . 100 4.1 Test results of the filter and VGA for base station receiver ...... 135 5.1 MeasuredPerformance . 157 x LIST OF FIGURES Figure Page 1.1 Definition of the linearity parameters . ... 7 2.1 Power levels of the neighboring channels of GSM . .... 10 2.2 SuperheterodyneReceiver . 12 2.3 Directconversionreceiver . 15 2.4 Two different cases of self mixing . 17 2.5 WideBandIFReceiver. ......................... 19 2.6 Digital-IFReceiver............................. 21 2.7 RC-OPampintegrator .......................... 31 2.8 (a):Tow-Thomas Filter (b): Ackerberg-Mossberg Filter ........ 34 2.9 Sallen-KeyFilter ............................. 34 2.10 Fully differential MOS-resistor . ... 35 2.11 The filter structure suitable for MOSFET-C filter . ..... 36 2.12Gm-Cintegrator ............................. 38 2.13 1storderOTA-Cfilters. .. .. 39 2.14OTA-Cbiquadfilter ........................... 40 xi 2.15 Block diagram of Master-Slave tuning system . .... 42 2.16 Block diagram of Frequency tuning controller . ..... 43 3.1 Schematic of the feed-forward compensation . .... 49 3.2 The schematic of feed-forward compensated DDA . ... 51 3.3 TheMergedFilterandVGA. 55 3.4 The Merged Filter and VGA for WLAN application . 58 3.5 Testchipmicrophotograph . 60 3.6 Frequency and phase response of the feedforward compensatedDDA. 61 3.7 Simulation result of corner simulations . .... 62 3.8 Measured square wave input response of the DDA . .. 62 3.9 Measurement result of AC magnitude of the Filter . .... 63 3.10 Measurement result of AC magnitude of the Filter when tuning signal wasapplied ................................ 63 3.11 Measurement result of Q factor variations . .... 64 3.12 Measurement result of gain variations of Filter and VGA ....... 65 3.13 Measurement result of two tone test of the filter and VGA . ..... 65 3.14 FullyDifferentialBuffer . 68 3.15 WLANreceiverarchitecture
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