Design of Analog Baseband Circuits for Wireless Communication Receivers
DISSERTATION
Presented in Partial Fulfillment of the Requirements for the Degree Doctor of Philosophy in the
Graduate School of The Ohio State University
By
Seoung Jae Yoo, B.S., M.S.
*****
The Ohio State University
2004
Dissertation Committee: Approved by
Mohammed Ismail ElNaggar, Adviser Joanne E. DeGroat Adviser Furrukh Khan Department of Electrical Engineering c Copyright by
Seoung Jae Yoo
2004 ABSTRACT
This dissertation describes the design and implementation of analog baseband
filter and variable gain amplifiers (VGA) for wireless communication receivers. Since discrete high-Q image rejection and IF filters are eliminated, fully integrated receiver architecture demands baseband filters and VGAs which exhibit high linearity and wide dynamic range. In this dissertation, baseband chains for WLAN receivers and base station application, and low voltage transresistance based filter and VGA are presented.
For WLAN receiver, three different baseband chains are introduced in chapter 3.
First baseband chain is designed based on the feed forward compensated amplifier.
Since the amplifier demonstrates high gain bandwidth and phase margin, the opera- tion of filter is not affected by phase error and finite gain bandwidth of the amplifier.
The feedforward compensated amplifier based filter and VGA are fabricated in 0.5µ
CMOS technology and measured. Second baseband chain is designed based on fully differential buffer. The fully differential buffer shows the characteristics such as wide bandwidth, low output impedance, and high linearity, which are required in the design of wideband filter. Since identical buffer circuits are applied for the design of filter and VGA, design and optimization time are saved. This baseband chain is fabricated in 0.18 µ CMOS technology and test results are presented. Third baseband chain is designed based on the differential difference amplifier(DDA) and folded cascode
ii amplifier. The DDA is used to implement wide band width buffer and folded cascode amplifier is used to design variable gain amplifier. The VGA of this baseband chain is fabricated in 0.5 µ CMOS technology and tested.
In chapter 4, the band pass filter and VGA for basestation are presented. Since base station requires strong linearity and power compression behavior, the baseband chain must demonstrate high linearity and wide dynamic range. To achieve required linearity, power consumption is increased and the use of nonlinear components is minimized. Seven filter blocks and five attenuators are cascaded for the realization of the baseband chain. The baseband chain is fabricated in 0.5 µ CMOS technology.
Finally, in chapter 5, the design of low voltage transresistance amplifier is pre- sented. The amplifier is operated with 1.8 V supply in 5 V CMOS technology. The amplifier is implemented to design Tow-Thomas filter and R2R ladder based VGA.
The amplifier and VGA are fabricated in 0.5 µ CMOS technology and tested.
iii This is dedicated to my wife and my parents
iv ACKNOWLEDGMENTS
I would like to express my utmost thanks and gratitude to Dr. Mohammed Ismail for providing an opportunity to perform research at Analog VLSI lab., The Ohio State
University. Without his guidance, this dissertation would not have been possible. He has helped me earn a lot of knowledge, and has given me confidence in my field of study.
I would alos like to thank Prof. Joanne E. DeGroat and Prof. Furrukh Khan for being part of my candidacy examination and Ph. D. dissertation committee.
I especially appreciate my wife and parents, who always support me and have made great sacrifice during my study. Without their support and sacrifice, I would not be able to finish my study.
I would like to thank my colleagues at Analog VLSI Lab. I appreciate their support and suggestions on my work.
v VITA
March 6, 1971 ...... Born - Seoul, Korea
March, 1994 - June, 1998 ...... B.S. Electrical Engineering, The Ohio State University, Columbus, Ohio June, 1998 - June, 2000 ...... M.S. Electrical Engineering, The Ohio State University, Columbus, Ohio July, 2000 - Present ...... Ph. D. Electrical Engineering, The Ohio State University, Columbus, Ohio January, 2000 - June, 2001 ...... Industrial Fellowship, by Nokia, Inc., Helsinki, Finland July, 2001 - Present ...... Graudate Research Assistant, The Ohio State University, Columbus, Ohio
FIELDS OF STUDY
Major Field: Electrical Engineering
Studies in Analog Microelectronics and IC Design:
vi TABLE OF CONTENTS
Page
Abstract...... ii
Dedication...... iv
Acknowledgments...... v
Vita ...... vi
ListofTables...... x
ListofFigures ...... xi
Chapters:
1. Introduction...... 1
1.1 Motivation ...... 1 1.2 Analog Baseband Filter and VGA in Wireless Communication... 3 1.3 Channel Select Filtering and Tradeoffs ...... 5 1.4 OrganizationoftheDissertation ...... 7
2. Background...... 9
2.1 ReceiverArchitecture ...... 11 2.1.1 Superheterodyne receiver ...... 11 2.1.2 Direct Conversion Receiver ...... 14 2.1.3 Wide-BandIFreceiver...... 18 2.1.4 DigitalIFreceivers...... 20 2.2 ChannelSelectionFilters ...... 21 2.2.1 Channel Selection Filtering and ADC requirements . . . .. 22 2.3 CMOSContinuousTimeFilters...... 27
vii 2.3.1 ActiveRCFilter ...... 30 2.3.2 MOSFET-CFilter ...... 33 2.3.3 OTA-Cfilter ...... 37 2.3.4 Tuningoffilter ...... 40
3. DesignofFilterandVGAforWLAN ...... 45
3.1 Feed forward compensated amplifier based filter and VGA for WLAN application ...... 46 3.1.1 Feed forward compensation technique ...... 47 3.1.2 Feed-forward compensated differential difference amplifier (DDA) 50 3.1.3 DesignofactiveRCfilterandVGA...... 54 3.1.4 TestResults...... 59 3.2 Fully differential buffer based filter and VGA for WLAN application 66 3.2.1 Fullydifferentialbuffer...... 67 3.2.2 DesignoftheWLANfilterandVGA ...... 70 3.2.3 Testresults ...... 76 3.3 Folded cascode amplifier and DDA based WLAN VGA and filter . 84 3.3.1 Folded cascode amplifier and Fully differential buffer based onDDA...... 84 3.3.2 DDA based filter and folded cascode amplifier based VGA . 89 3.3.3 Testresults ...... 93
4. DesignofFilterandVGAforbasestation ...... 101
4.1 Thebasestationarchitectures...... 103 4.2 DesignConsideration...... 106 4.2.1 FilterandVGAStructure ...... 107 4.2.2 Trade off between Power consumption and dynamic range . 111 4.3 DesignofFilterandVGA ...... 116 4.3.1 Fully differential buffer without common mode feedback . . 118 4.3.2 Designofthebandpassfilter ...... 120 4.3.3 Digitallyprogrammableattenuators ...... 123 4.4 TestResults...... 125
5. Filter and VGA based on a Low Voltage Transresistance Amplifier. . . . 136
5.1 Low Voltage Transresistance Amplifier ...... 137 5.2 Filter and Variable Gain Amplifier ...... 146 5.3 TestResults...... 150
viii 6. Conclusions ...... 158
Bibliography ...... 163
ix LIST OF TABLES
Table Page
2.1 Requirements to channel selection filtering ...... 25
2.2 Attenuation of a W-CDMA signal at different offsets for low pass filters. 26
3.1 Test results of feed forward compensated amplifier based filter and VGA 66
3.2 The specification of the filter and VGA for Wireless LAN application 71
3.3 Test results of Fully differential buffer based filter and VGA ..... 84
3.4 TestresultsofthefilterandVGA ...... 100
4.1 Test results of the filter and VGA for base station receiver ...... 135
5.1 MeasuredPerformance ...... 157
x LIST OF FIGURES
Figure Page
1.1 Definition of the linearity parameters ...... 7
2.1 Power levels of the neighboring channels of GSM ...... 10
2.2 SuperheterodyneReceiver ...... 12
2.3 Directconversionreceiver ...... 15
2.4 Two different cases of self mixing ...... 17
2.5 WideBandIFReceiver...... 19
2.6 Digital-IFReceiver...... 21
2.7 RC-OPampintegrator ...... 31
2.8 (a):Tow-Thomas Filter (b): Ackerberg-Mossberg Filter ...... 34
2.9 Sallen-KeyFilter ...... 34
2.10 Fully differential MOS-resistor ...... 35
2.11 The filter structure suitable for MOSFET-C filter ...... 36
2.12Gm-Cintegrator ...... 38
2.13 1storderOTA-Cfilters...... 39
2.14OTA-Cbiquadfilter ...... 40
xi 2.15 Block diagram of Master-Slave tuning system ...... 42
2.16 Block diagram of Frequency tuning controller ...... 43
3.1 Schematic of the feed-forward compensation ...... 49
3.2 The schematic of feed-forward compensated DDA ...... 51
3.3 TheMergedFilterandVGA...... 55
3.4 The Merged Filter and VGA for WLAN application ...... 58
3.5 Testchipmicrophotograph ...... 60
3.6 Frequency and phase response of the feedforward compensatedDDA. 61
3.7 Simulation result of corner simulations ...... 62
3.8 Measured square wave input response of the DDA ...... 62
3.9 Measurement result of AC magnitude of the Filter ...... 63
3.10 Measurement result of AC magnitude of the Filter when tuning signal wasapplied ...... 63
3.11 Measurement result of Q factor variations ...... 64
3.12 Measurement result of gain variations of Filter and VGA ...... 65
3.13 Measurement result of two tone test of the filter and VGA ...... 65
3.14 FullyDifferentialBuffer ...... 68
3.15 WLANreceiverarchitecture ...... 71
3.16 Fully differential buffer based multi standard filter and VGA ..... 72
3.17 6dBstepattenuator ...... 76
3.18 The simulation result of frequency response of the high pass filter . . 77
xii 3.19 The simulated frequency response of the cascaded Filter and VGA blocks 78
3.20 ThelayoutoftheWLANfilterandVGA ...... 78
3.21 The measured results of the filter and VGA gain variation ...... 79
3.22 Gaincomparisonto0dBreference ...... 80
3.23 The frequency response of 10 MHz and 20 MHz filter ...... 81
3.24 The measured result of two tone test ...... 82
3.25 The transient response when the gain is switched from 30 dBto9dB 83
3.26 ThemagnifiedviewoftheFigure3.25 ...... 83
3.27 Foldedcascodeamplifier ...... 85
3.28 TheschematicofDDA ...... 88
3.29 TheTunableMOSFET-CFilter ...... 90
3.30 The VGA based on the folded cascode amplifier ...... 91
3.31 The schematic of the multi-standard filter and VGA ...... 93
3.32 The post layout simulation result of the WLAN filter/VGA blocks . . 94
3.33 The post layout simulation result of the VGA ...... 95
3.34 The simulated result of low pass filter noise figure ...... 95
3.35 The simulated result of VGA noise figure ...... 96
3.36 Thetestchipmicrophotograph ...... 97
3.37 The measured result of the gain variation ...... 97
3.38 The measured result of gain variation in time domain ...... 98
3.39 The output response of the VGA when pulse input signal was applied 99
xiii 3.40 The measured result of two tone test ...... 99
4.1 Traditional Digital Base Station Architecture ...... 103
4.2 Universal Base Station Architecture ...... 104
4.3 InputSpectrumoftheWideBandADC ...... 106
4.4 The relation between IMFDR3 vsSNR...... 108
4.5 Three possible combinations of filter and VGA ...... 109
4.6 IMFDR3 vs.Inputvoltage(rms)...... 111
4.7 The change of IMFDR3 and NF according to different IIP3 . . . . . 115
4.8 FilterandVGAforbasestation ...... 117
4.9 FullyDifferentialBuffer ...... 119
4.10 Sallen-Key filter with capacitor stack ...... 122
4.11 6dBstepand1dBstepattenuators ...... 124
4.12 Frequency response of the Fully differential buffer ...... 125
4.13 Frequency response of the VGA-Filter combination when the gain is maximum ...... 126
4.14 Thepassbandripple ...... 127
4.15 The simulated plot of the frequency shift when the capacitor array is switched ...... 128
4.16 ThegroupdelayoftheVGA-Filter ...... 129
4.17 The group delay of the VGA-Filter when 2nd order all pass filter is cascaded...... 130
4.18 ThegainvariationoftheVGA-Filter ...... 131
xiv 4.19 The simulation result of two tone test of the VGA-Filter combination 132
4.20 The simulated output noise of the VGA-Filter ...... 132
4.21 TheChipMicrophotographoftheFilter ...... 133
4.22 TheChipMicrophotographoftheVGA...... 133
4.23 The measured output response of the filter ...... 134
4.24 The measured output response of the VGA ...... 134
4.25 The measured result of the VGA two tone test ...... 135
5.1 The input stage of an NMOS differential pair amplifier ...... 138
5.2 Theconversionofvoltagetocurrent...... 140
5.3 The closed amplifier configuration ...... 140
5.4 The closed amplifier configuration ...... 141
5.5 Thecurrentbuffer ...... 142
5.6 TheLVTA...... 143
5.7 The simplified view of the receiver ...... 146
5.8 TheTowThomasFilter ...... 147
5.9 TheR-2Rladder ...... 149
5.10 The programmable gain amplifier by using R-2R ladder ...... 150
5.11 ThemicrophotographoftheLVTA ...... 151
5.12 The frequency response of LVTA when Ri ischanged ...... 152
5.13 The frequency response of LVTA when RF ischanged ...... 152
xv 5.14 The frequency response of LVTA when CF ischanged ...... 153
5.15 The frequency response of LVTA based Tow-Thomas filter ...... 154
5.16 Thespectralresponseofatwotonetest ...... 154
5.17 The frequency response of LVTA with 1.5V supply ...... 155
5.18 The microphotograph ofthe R-2Rbased VGA ...... 156
5.19 The Frequency response of R-2R based VGA ...... 156
xvi CHAPTER 1
INTRODUCTION
1.1 Motivation
As various wireless communication systems emerge, size and price have become under heavy pressure because average consumers want smaller and lower price mobile sets. A lot of research effort has been dedicated to make standard CMOS technology applicate to System-on-Chip configuration (Soc). SoC is highly wanted by the wireless industry since it reduces the area of transceiver and the price of product.
The integration of digital circuits is straightforward as all the components are transistors. Even though the level of complexity is so high in terms of managing the design and verification process, the problems with very large digital circuits are not associated with the technology, but with the design methodologies and tools [25].
However, integrating all analog circuitry on a single chip is very difficult in terms of integrated circuit technology. In particular, high frequency filters are still realized with discrete components in wireless communication systems because the required selectivity is infeasible with current integrated circuit technology. These discrete
filters are not only expensive but are increasing the loss in the receiver chain.
1 To increase the integration rate of the analog circuitry, the use of discrete filters must be minimized. To achieve this purpose, the radio architecture that applies the minimum number of high frequency filters should be used. The radio architecture has a major impact on the number of external components and power consumption [11].
Depending on the receiver architecture, the number of discrete filters can be reduced and integration of analog filter is easier, but other problems may occur. For example, in direct conversion receiver, all IF filters are eliminated and channel selection is done in baseband. But this architecture is susceptible to DC offset and flicker noise.
In low frequency, the integration of analog filter is feasible because the required selectivity is low. However there are still many difficulties in the integration because of limited dynamic range and unwanted variation. Most low frequency range filters are based on operational amplifier (OP AMP) or operational transconductance am- plifier(OTA). Since the active components are only linear in certain frequencies and signal range, the use of active components limits the dynamic range and linearity of
filter. The integrated filters are also sensitive to process and temperature variation.
So tuning circuits must be used to compensate the frequency shift. The tuning cir- cuits sometimes affect the dynamic range. Furthermore, as wireless communication systems such as WLAN emerge, 3 dB corner frequency of the baseband filter is highly increased, and this makes the integrated filter design more difficult.
As wireless communication systems are required to process high data rate signals, baseband analog filters must have wide bandwidths, while maintaining high linearity, low noise, and low power consumption. In wide bandwidth system, it is not easy to achieve high linearity and low noise with low power consumption since linearity
2 and integrated noise are increased with power consumption and bandwidth respec- tively. Therefore, the design of baseband filters is more complicated as the band- width increases. Wide bandwidth filters are only possible when the active component demonstrates wide gain bandwidth, high linearity, and low noise.
The motivation of this dissertation is to investigate and propose simple and robust
CMOS circuits based filter and VGA, and develop low power consumpion and dig- itally programmable baseband chains for wideband receivers. The analog baseband
filter and VGA are essential building blocks in the wireless communication system.
They are used to select desired signals from interferers, to antialias unwanted noise and blockers, and to relax the dynamic range requirement of analog to digital con- verter(ADC). Without them, the ADC must handle all interferers, aliased noise, and gain variations. These unwanted effects will inhibit the proper operation of ADC.
1.2 Analog Baseband Filter and VGA in Wireless Commu- nication
Analog baseband filters can be divided into two different kinds: sampled data
filters and continuous time filters. Even though sampled data filters are accurate and not sensitive to process variation, they are not used in wideband signal processing because of the high clock frequency and settling time requirement of the amplifier. In contrast, continuous time filters are widely used in wideband signal processing, but they are very sensitive to process and temperature variation. The performance of continuous time baseband filters often represents the main bottleneck in improving the performance of digital receiver [49]. The performance of receiver is often limited because of frequency variation, mismatch, and phase error in the baseband filter.
3 Variable gain amplifiers(VGA) are used to increase the dynamic range of the baseband processing in certain cases. The power received at the antenna in the desired channel can vary widely depending on the distance from the base station and channel characteristics. If only the desired channels are present, the dynamic range requirements are set by this power variation. This means that the VGA can be used to vary the gain in the receive path to meet the dynamic range requirement. If the interfering channels are present, the VGA will not improve the dynamic range because both the desired and interferers will be amplified by the same amount. Therefore, interferers must be attenuated before the amplification of desired signal.
Nowadays, wireless communication systems are required to process not only high data rates but also multi-standard information. The reason for this is that second generation and third generation cellular phones or WLAN and Bluetooth will coexist for some time [1]. This implies that the baseband filter in the receiver must have wide- band cut-off frequency and multi-standard capability. To achieve wideband cut-off frequency, the amplifier applied in the filter must have high gain bandwidth (GBW).
High gain bandwidth is usually achieved at the expense of high current consumption, which is the main reason for the increase of power consumption in the filter. Multi- standard capability is usually obtained with parallel connection of passive components with switches. Since the bandwidth of different standard is determined by digital sig- nal processor (DSP), programmable switches must be implemented to change the bandwidth.
There are still many difficulties in achieving wideband continuous time filter. Lin- earity is a main concern because intermodulation products of two in-band signals can block desired signals in the wideband filter. Also parasitics near the cut-off frequency
4 not only degrades the linearity but also increases the uncertainty of the time con- stant of the filter. Since the size of passive components used in the filter is getting smaller as the filter bandwidth increases, Mismatch or process variation of the passive components is more critical to the variation of the filter’s time constant. Therefore, integration of wideband filter requires extra time for post design tuning.
1.3 Channel Select Filtering and Tradeoffs
The main purpose of the analog baseband filter in the digital receiver is to select the desired channel and maximize the dynamic range of ADC. To do so, the base band filter must attenuate interferers to certain power level and provide wide dynamic range. Channel selection can be performed in the analog domain, digital domain or in both domains. In analog domain, continuous-time or switched-capacitor filters are used to select the desired channel. In this case, the analog filter must have enough of a dynamic range and linearity to select the desired channel in the presence of strong adjacent channel interferers. The ADC is required to have only a low resolution.
However, the required channel selectivity and linearity of analog filters are very high, and component variations must be well compensated in order to avoid impact of the bandwidth of the filter.
Channel selection can be performed in the digital domain using an digital filter. In this case, phase and gain error due to analog filters do not exist and component vari- ation is not a concern. Also, programmability of the receiver is increased. However, the ADC must have high resolution and a wide dynamic range to handle interferers and blockers. Even in the digital channel selection, antialias analog filter must be
5 used. In case of mixed signal channel selection, channel selection is partitioned be- tween the analog and digital domain. From a power dissipation and area perspective, some combination of analog and digital filtering will be an optimal choice.
To design baseband filter and VGA in a wireless communication system, many specifications must be considered. The specifications include bandwidth, antialias- ing, linearity, and dynamic range. The bandwidth requirements on the baseband processing are determined by the channel spacing and the modulation scheme which determines how much of that bandwidth is occupied by information. RF bandwidth is the number of channels multiplied by the channel spacing. Since the integrated receivers mix the entire RF band to baseband, the total RF bandwidth will impact antialiasing requirements.
Linearity is an important specification because third order intermodulation of the large adjacent channel blockers will fall into the same frequency band as the desired signal. Third order distortion is specified in terms of the input referred third order intercept point IIP3. IIP3 is the input power level in dBm where the third-
order intermodulation distortion (IM3) line crosses the input line. Figure 1.1 shows
definition of the linearity parameters in log log scale.
Dynamic range is the difference in power between the maximum signal level that
must be handled and the noise floor. Since no channel select filtering is performed
prior to the baseband in integrated receivers, the maximum signal level is set primarily
by blocking requirements. Spurios-free dyanamic range (SFDR) is often used for
the measure of dynamic range of filter and VGA. The spurious-free dynamic range
(SFDR) is the difference in decibels between the input referred in-channel noise power
(PN,IN ) and the level of a single test signal in the IIP3 test at which the level of the
6 P out OIP 3
3 SFDR 1
1 1 Nout
Nin IIP 3 P in
Figure 1.1: Definition of the linearity parameters
input-referred third-order intermodulation distortion component becomes equal to the input-referred noise. The SFDR can be written as
2 SFDR = (IIP P ) (1.1) 3 3 − N,IN
1.4 Organization of the Dissertation
Chapter 2 discusses the background of analog continuous time filters. In this chapter, receiver architectures are briefly reviewed and requirements of continuous time channel selection filters are discussed. The most popular continuous time filters are briefly introduced and design requirements are also discussed.
Chapter 3 discusses continuous time filters and VGA for a wireless local area net- work (WLAN). Since WLAN requires wideband signal processing, baseband continu- ous time filter must have wideband 3 dB frequency. To achieve wideband capability without significant phase error, high gain bandwidth amplifier must be implemented.
7 In this chapter, three different WLAN filters and VGAs are introduced. Each filter and VGA apply different amplifiers to achieve the requirement.
Chapter 4 discusses filter and VGA for base station. The presented filter is a bandpass filter that is applicable to Universal base station receiver. Since the filter in the base station must demonstrate high linearity, the number of active elements is minimized, with the exception of the amplifier. To achieve wide bandwidth and high linearity, the VGA is replaced with a passive resistive chain based attenuator.
Chapter 5 discusses the transresistance amplifier based filter and VGA. Since transresistance amplifier uses current as input, it is suitable in the design of low voltage filter and VGA. In this chapter, single input with single output transresistance amplifier is discussed and application of the amplifier is demonstrated.
Chapter 6 concludes this dissertation and discusses future work and possibilities.
8 CHAPTER 2
BACKGROUND
Early radio receivers detected signals directly from radio frequency(RF). There- fore, the early radio receivers did not utilize frequency translation at all. However, this direct signal detection is impossible in modern radio receivers. Because the mod- ulation schemes are used to deliver information effectively, a radio receiver must select a certain frequency band and translate the band to another frequency to detect the transmitted information [25]. Thus, modern communication systems are not designed for easy detection but for the efficient use of radio bandwidth. The received signal may contain other adjacent channels with significantly higher power than the desired channel.
As an example, Figure 2.1 shows the well-known GSM specification for the possible power levels of the neighboring channels as a function of frequency offset. If the adjacent channel which is 600kHz offset from the desired channel must be attenuated by 10 dB below the desired channel to detect the information, the adjacent channel must be attenuated by 65 dB according to the Figure 2.1. Since the desired channel is
-98 dBm, the power of adjacent channel, -43 dBm, should be attenuated to -108 dBm.
In the case of GSM, the desired channel has a bandwidth of only 200KHz located
9 -23 -23 -33 -33 -43 -43 I n t e r f e r e r [ d B m ] I n t e r f e r e r
-98
-3 -1.6 -0.6 +0.6 +1.6 +3 Input frequency [MHz]
Figure 2.1: Power levels of the neighboring channels of GSM
around 900 MHz. For the detection of the transmitted information, the required filter must have a quality factor Q as
900MHz Q = 200KHz = 4500. which is impossible to realize with modern technology [25]. The solution for this prob- lem is to translate the frequency to lower or zero frequency for easier detection with feasible filters. In modern receivers, detection of information is usually done in low IF or zero IF. The analog filters in low IF or zero IF separate the desired channel from undesired ones and interferers, which may be orders of larger than the desired signal.
Accomplishing the same job without analog filters would require analog to digital converters(ADCs) with much larger number of bits to properly digitize and process large interferers [49]. In most cases, power dissipation constraints and difficulty of implementation prohibit the use of such ADCs. Therefore, analog baseband filters are needed for the proper detection of the desired signal in radio receivers. In the design of the high-performance electronic circuits, the use of analog filters is unavoidable
10 [38]. In this chapter, background of analog continuous time filters are overviewed.
Receiver architectures used in the next chapters are briefly introduced and require- ments of channel selection filters are consequently discussed. Finally, representative analog continuous time filters are introduced.
2.1 Receiver Architecture
The purpose of this section is to briefly overview the receiver architectures that will be used in the following chapters. Therefore, this section does not cover all receiver architectures and a detailed analysis will not be considered. As mentioned before, the analog channel selection filter’s specification is highly affected by receiver architecture. Therefore, it is important to understand the requirements of receiver architectures for the effective design of analog baseband filters. In this section, super heterodyne receiver, direct conversion receiver, wide band IF receiver, and digital
IF receiver architecture are presented. Even though super heterodyne receiver was not used in the design of channel selection filters in this thesis, this architecture is introduced for the purpose of comparison with other receiver architectures used in the following chapters.
2.1.1 Superheterodyne receiver
A superheterodyne receiver removes the image component by filtering before each downconversion stage [29]. When the radio frequency(RF) signal is downconverted to a non-zero intermediate frequency(IF), the image component which is at the same frequency offset from the local oscillator(LO) as the desired RF signal, but on the other side of the LO, is mixed to the same IF as the desired signal. The image rejection filter must attenuate the image before the frequency translation. Otherwise,
11 the image frequency component cannot be separated from the desired signal. A block diagram of the superheterodyne receiver is shown in Figure 2.2.
IF LNA
Band Select Image Channel VGA Channel Reject Select Select RF LO IF LO
Figure 2.2: Superheterodyne Receiver
First, a passive off-chip pre-select filter attenuates the signal outside the desired
system band [20]. This filter serves to suppress out-of-band signals and thus lower
the dynamic range requirements of the subsequent stages. It is desirable to suppress
out-of-band signals as much as possible, but there is a tradeoff between stop band
attenuation and pass band insertion loss [17]. The insertion loss of this filter is
critical since it directly adds to the receiver noise figure. Usually, the band select
filter is realized as a ceramic or a surface acoustic wave (SAW) filter. Above 1GHz,
Ceramic filters are often preferred because it demonstrates less insertion loss [17]. A
low noise amplifier follows the preselect filter. The low noise amplifier(LNA) input
must be matched to a specified impedance level, typically 50 Ω, since the matching
impedance is part of the preselect filter [20]. After the LNA, the first mixer converts
the desired channel down to a fixed IF.
12 The first IF frequency must be chosen carefully to allow the image at any possible
LO frequency to lie outside the system band and to be attenuated enough by the pre-selection filter [25]. The first IF in a superheterodyne receiver must be given as
B fIF 1 > 2 where B is the bandwidth of the pre-selection filter. A high intermediate frequency relaxes the requirements on the preceding filter, but places higher demands on the circuitry of the succeeding IF stage. If the received radio frequency is very high when compared to the available filter technologies, it might be impossible to filter the signal. This problem can be overcome by filtering and converting down several times. The number of downconversions depends on the frequency planning and on the selectivity of the filters that can be attained. However, every down converting generates a new image frequency which must be rejected before the mixing, and the successive stages usually introduce a lot of noise which eventually limits the dynamic range of the receiver.
After the down-conversion mixer, a passive off-chip channel-select filter attenuates the out-of-channel signals to a sufficiently low level. Therefore, the linearity require- ments of the following stages are significantly decreased. The first IF is typically between 30MHz and 100MHz [20]. The selection of the IF forms a trade-off. If a high
IF is chosen, a less selective image-reject filter is sufficient at RF, but the required selectivity of the IF channel-select filter is increased. On the other hand, if a low IF is selected, the requirements for the channel-select filters are relaxed at the expense of tighter specifications for the RF filters. In most applications, the channel select
filters cannot be implemented on chip with active components [20]. Therefore, power consumption is increased because input and output of the channel select filter should
13 be matched to low impedance level. The channel-select filtering is usually divided between one or more IF filters and analog or digital baseband filters. A variable-gain amplifier (VGA), which follows the IF filter, decreases the dynamic range require- ments of the following stages. After the first IF, the signal can be downconverted to another IF or to DC using quadrature downconversion. The signal may also be sampled and digitized if the IF is sufficiently low. More than one IF can be used to divide the channel-select filtering and amplification between several stages.
The superheterodyne receiver architecture has dominated the field for decades since it offers a superior performance compared to other radio receiver architectures
[25]. The excellent sensitivity and selectivity comes from the use of passive, highly linear off-chip filters. These filters offer a sufficient image rejection and selectivity at IF. The problems related to DC offsets and flicker noise can be avoided since the signal can be processed at an IF far from DC.
2.1.2 Direct Conversion Receiver
A direct conversion receiver converts the carrier of the desired channel to the zero frequency directly [29]. The direct conversion receiver is an alternative solution to the image rejection problem. The intermediate frequency is moved to DC making the desired channel an image of itself. Consequently, no image rejection filter is needed prior to mixing. The direct conversion receiver has several advantages over the superheterodyne receiver which must implement external IF filters. The IF stages and the passive IF filters are eliminated so that the integrability of the direct conversion receiver is much higher than the superheterodyne. Furthermore, the direct conversion receiver is suitable for the multi-mode receivers since the bandwidth of the integrated
14 low pass filters can be designed programmable. Figure 2.3 shows the schematic of the direct conversion receiver architecture.
Channel Select
I
VGA 0 LNA RF LO 90
Band Select
Q
Channel Select VGA
Figure 2.3: Direct conversion receiver
Two downconversion mixers must be used for demodulation at RF if a signal with quadrature modulation is received [29]. The pre-select filter is used to attenuate out of band signals before the LNA. Since there is no problem with image signal in the direct conversion receiver, the off-chip filter between LNA and mixer is not required.
Therefore, the output of the LNA drives on-chip load so that only input matching in the LNA is required. Also, a low pass filter with a bandwidth of half the symbol rate is suitable for channel selection [29]. This can be implemented with an active on-chip
filter.
The most serious problem of the direct conversion receiver is that of DC and time varying offset voltages after the down conversion stage [29], [17], [20]. Since the down converted band extends to zero frequency, static and time varying offset voltages can
15 corrupt the signal and saturate the following stages [17], [20]. The dc offset must be eliminated or minimized to avoid the signal saturation. Even though automatic gain control can prevent the saturation of the incoming signal, the amplification will be very small so that the detection of a weak signal will be very difficult. In addition the dc offset component can be considered as an in-band interferer if the offset is not removed.
One source of offset voltage involves transistor mismatches in the down converter and following baseband stages [17]. This kind of offset voltage is almost constant. The other dc offsets come from the self-mixing of the local oscillator signal. This is caused by the leakage of local oscillator signal to the input of the mixers, which mixes with itself and generates a constant dc offset [17]. If local oscillator leak directly to the RF port of the mixers or to the input of LNA, the dc offset problem will be more serious
[17], [20]. The leaked local oscillator signal can also propagate to antenna because of the finite reverse isolation of the LNA and pre-selection filter and reflect back from the interfaces having mismatch. If the local oscillator radiates from the antenna and reflects from other objects back to the receiver, the offset due to self-mixing varies in time [17], [20]. Figure 2.4 shows two different cases of self mixing.
In case of Figure 2.4 (a) the local oscillator is mixed with itself, creating an offset voltage at the output of the down converter. This voltage is typically orders of magnitude larger than the desired signal, and if not removed unremoved will cause saturation in subsequent stages [17]. As the antenna surroundings change over time and as leakage local oscillator reflect from nearby moving objects, the local oscillator signal at the RF port of the down converter may vary over time, resulting in a time
16 LNA Channel Select VGA
LO leakage
RF LO
(a)
LNA Channel Select VGA
Interferer leakage
RF LO
(b)
Figure 2.4: Two different cases of self mixing
varying offset voltage [17]. The other source of time varying offset voltage is self- mixing of a strong interfering signal as shown in Figure 2.4 (b). For example, the leakage signal from the transmitter is self mixed and creates a distorting signal at the baseband. This distorting baseband signal will vary with time due to both the amplitude modulation of the transmitted signal and due to the power control in the up-link [17], [20].
The magnitude of the offset voltage can be reduced by better circuit design. Im- plementation of high pass filter or DC servo loop can remove the dc offset. However since the substantial information is contained at low frequency, the cutoff frequency
17 of the high pass filter must be very low. This means that the capacitor in high pass
filter must be very large. Then the settling time of the filter will be slow that the high pass filter will not remove the fast time varying dc offsets.
The absence of passive IF filters places very stringent requirements on the active baseband filters. Both the linearity and the noise must be much lower than in a superheterodyne receiver as there is no significant amount of filtering or amplification in the IF. However flicker noise is high around dc and dc offset is always present.
Also mismatches between I and Q phase signal path cause significant problem. So the design of channel select filter in the direct conversion receiver should be done carefully. The WLAN filters and VGAs presented in 3.1 and 3.3 are designed based on the direct conversion receiver architecture.
2.1.3 Wide-Band IF receiver
This kind of receiver down converts a group of channels simultaneously [17]. Figure
2.5 shows the schematic of the wide-band IF receiver.
In most wide-band IF receiver, simple low pass filters are used at IF to suppress higher frequency components, allowing all channels to pass the second stage of down converters, where the wanted channel is converted to base band or low intermediate frequency [17]. The second mixer and latter stages constitute a direct conversion or low-IF receiver [17]. A benefit of the wide-band architecture is the adaptation of a high IF in which the image is outside the passband of the pre-selection filter. Another advantage of the wide-band IF receiver is that it eases full synthesizer integration [17].
The fixed frequency RF local oscillator is easier to implement, since a crystal con- trolled wide-band PLL with a high phase detector frequency can be used to clean up
18 Wideband IF Channel I
VGA 0 LNA 90 RF LO Band Select Q
Wideband IF Channel VGA
0 90
Figure 2.5: Wide Band IF Receiver.
the phase noise spectrum of the VCO [17]. The requirements for high Q components are thus relaxed. The wide-band IF architecture follows exactly the same frequency selection criteria for the first IF as superheterodyne. If the second mixer stage does not convert the signal directly down to baseband, the secondary image can be a prob- lem. However, most wide-band IF architecture use a zero IF after the mixers. As shown in the Figure 2.5, the lowpass filters between the mixers are only necessary to suppress the upconverted product generated in the first downconversion [29]. The channel selection filters are placed after the second downconversion. Typically, the limited output bandwidth of the RF mixers together with the interconnection to the second mixing stage attenuate the high-frequency products sufficiently without any extra components [29]. In this architecture, the local oscillator to RF leakage is less important because the first local oscillator is outside the passband of the preselection
19 filter like in superheterodyne. The wide band IF topologies transfer the typical down- conversion problems of a direct conversion into the second mixer stage [17], [29]. The distortion generated around dc in the first mixer is not significant because the por- tion, which passes the possible ac-coupling between the stages, is mainly upconverted in the second mixers. The most critical blocks are the second mixers. They handle all radio channels passing the preselection filter. This receiver architecture was used in the WLAN baseband chain of 3.2.
2.1.4 Digital IF receivers
Digital signal processing would provide significant benefits compared to analog cir- cuitry if the conversion to digital will be brought closer to the antenna [29]. When the downconversion to baseband is performed digitally, dc offset, flicker noise or match- ing problems can be eliminated. However, due to the resolution or increased power consumption and sampling rate of ADC, direct RF to digital conversion is impossible with current technology. But low frequency operations, such as the second set of mixing and filtering in the dual IF heterodyne conversion, can be performed more efficiently in the digital domain. Figure 2.6 shows the digital IF receiver. In this
figure, the first IF signal is digitized, mixed with the quadrature phases of a digital sinusoid, and low pass filtered to yield the quadrature baseband signals [33]. The digital processing avoids the problem of I and Q mismatch [33]. The issue in this architecture is the requirement of ADC. ADC dynamic range must be wide enough to handle the signal variations caused by path loss. Also band pass filter should have wide signal handling capability, dynamic range and need to suppress adjacent interferers effectively. Because the power consumption and requirement of ADC is
20 LPF I BPF BPF
Wide Digital LNA VGA Band sinewave ADC generator
Q LPF
oscillator
Figure 2.6: Digital-IF Receiver.
too high for the mobile set receivers, this architecture is mainly used in the base station [33]. The baseband chain presented in chapter 4 was designed based on this architecture.
2.2 Channel Selection Filters
The receiver’s ability to suppress adjacent channel interference and in-band block- ing signals is directly dependent on the channel selection filtering. As pointed out in the previous section, the received signal contains not only the desired channel but a multitude of neighboring channels or other interferers which must be attenuated before the detection can be done [25].
The channel filtering can be done at an intermediate frequency, at baseband or even over the A/D interface. In superheterodyne receivers, the channel filtering is performed at the intermediate frequency with a passive filter [25]. The passive filter is very linear and reduce the interferers without corrupting the desired signal. However, the passive filter must be used externally so it is not suitable for system on chip
21 configuration. In direct conversion or wide-band IF receivers, the channel selection
filtering is performed at the baseband. The required quality factor of the filter is not high so that the channel selection filters can be integrated with other receiver blocks. However, the linearity requirement of the filter is high because adjacent channel interferers are unattenuated so that the filter must suppress the interferers without the production of significant intermodulation products [30].
One of the main issues to address when designing the channel selection filtering is how to partition the filtering between the analog and the digital domain. Generally it is preferable to realize as much filtering as possible in the digital domain because this reduces the analog complexity. However, the penalty of pushing more filtering into the digital domain is that the ADC requirements and digital complexity increase.
In this section, channel selection filtering, ADC requirements and filter prototype for channel selection filters are discussed.
2.2.1 Channel Selection Filtering and ADC requirements
In modern communication systems, the signal is eventually converted to a digi- tal representation. Therefore, analog to digital converter (ADC) should be used to convert analog data to digital form [17], [20]. If the ADC is able to handle every interferers and noise generated by preceding blocks, channel selection can be done in digital domain [11], [17], [20]. This is desirable case since digital filters are very accurate and do not require tuning circuitry. Also digital filters are readily integrated together with the front-end of the receiver [25]. However, as mentioned before, it is very difficult to design the ADC that has extremely high dynamic range and linearity with low power consumption. Even if the ADC can handle all the interferers, the
22 power consumption would be very high due to the increased resolution requirements since the power of Nyquist rate ADC is proportional 2N where N is number of bits
[20]. Thus, this is not a recommended way for low powered mobile hand set receiver.
In the other case, channel selection filtering can be done partially or fully in analog domain. Since the channel selection filter in the analog domain reduces the power of interferers, the dynamic range requirement of the ADC is relaxed. As the order of analog channel selection filter increases, the requirement of ADC is more relaxed, but the increased order of analog domain filter increases signal delay and phase dis- tortion [17]. Usually group delay and phase near the cut-off frequency are highly distorted than other region [17], [20], so the distortion should be compensated with additional circuitry such as all pass filter. Moreover, higher order filter increases the complexity of tuning circuit since the quality factor and attenuation rate of the filter are increased.
In selecting analog low pass filters for the channel-selection filtering, three im- portant parameters have to be determined: filter prototype function, 3 dB corner frequency, and filter order [17]. There are four main filter prototypes: Butterworth,
Chebychev, Inverse Chebychev and Cauer or elliptic filter. Each prototype has its advantages and disadvantages. In terms of attenuation, the Cauer filter performs the best [28]. To achieve the same attenuation rate as the Cauer filter, the Butterworth
filter requires a much higher order such as 1.5 times or even 2 times the order of the elliptic filter [28]. In terms of group delay, the Butterworth filter demonstrates minimum error while the Cauer filter exhibits worst group delay errors [28], [38].
Since the Butterworth filter requires higher orders than the Cauer filter to achieve the same attenuation rate, eventually the group delay of the Butterworth filter will be
23 increased. Therefore, the Cauer or the elliptic filters are popular in realization of the channel selection filter. However, the elliptic filter requires higher order delay equal- izers than the Butterworth filter to compensate for group delay. Since elliptic lowpass
filters contain right half plane zeros (transmission zeros) at the stopband, in addition to left half plane poles, a sharp transition region due to high Q elliptic prototype causes severe group delay peaking close to the passband edge. If channel selection is partially done in analog domain, the required filter order will not be high. Then
Butterworth filters will be the proper choice for channel selection filter, providing a good compromise between attenuation and distortion of the desired signal.
3 dB corner frequency and filter order are chiefly determined by channel spacing, blocking profiles and intermodulation test. Detailed analysis of choosing 3 dB corner frequency is introduced in [17]. Even though 3 dB corner frequency is mainly de- termined by channel spacing and signal bandwidth, actual 3 dB corner frequency of the channel selection filter should be decided after considering the amplitude and the phase distortion of the desired signal. Since phase and amplitude error is increased near the 3 dB corner frequency, the 3 dB bandwidth of the filter can be selected as a higher frequency than that of the signal bandwidth. In this case, the order of the
filter must be increased since the 3 dB corner frequency of the filter is increased. To demonstrate how to choose order of channel selection filters, the W-CDMA adjacent channel selectivity requirements and blocking test requirements from [17] are used.
The test requirements are summarized in Table 2.1. To investigate the channel se- lection filtering requirements, a Butterworth filter is used for simplicity. As shown in the Table 2.1, the band selection filter does not attenuate in band blockers. In the
24 case of the Butterworth filter, the attenuation of filter can be decided by the equation
2.1 [28]
Frequency Offset Required Total Contribution from Requirements to Attenuation Band Selection Channel Selection Filter Filtering f f =5MHz 33 dB 0 dB 33 dB | − o| f fo =10MHz 43 dB 0 dB 43 dB |f − f |=15MHz 55 dB 0 dB 55 dB | − o| f f =60MHz 69 dB 9 dB 60 dB | − o|
Table 2.1: Requirements to channel selection filtering
[2nlog( ωs )+log(100.1Amax −1)] Attenuation = 10log 1+10 ωp (2.1) h i where n is the order of filter, ωs is the stop band of the filter, ωp is the pass band of
the filter, and Amax is the maximum attenuation at the pass band. If 3 dB corner
frequency is selected as the edge of the pass band, Amax is equal to 3 dB. In the case
of the W-CDMA receiver specification introduced in the [17], 3 dB corner frequency
is selected to be 2.25 MHz. However, the equation 2.1 does not approximate closely
at frequencies near cut-off frequency. The attenuation of the adjacent channel cannot
be accurately predicted using the equation 2.1. Therefore, to include margin, 3 dB
corner frequency is assumed as 2.5 MHz for only calculation purposes. Table 2.2
shows the calculated attenuation of the Butterworth filter. According to Table 2.2,
the 2nd order filter cannot be used in fulfilling the attenuation requirements. In the
case of the 3rd order filter, the required attenuation is fulfilled for offsets higher than
approximately 25 MHz. In the case of the 4th order filter, the attenuation requirement
25 Frequency Offset 2nd order 3rd order 4th order 5th order Requirement filter filter filter filter f f =5MHz 12 dB 18 dB 24 dB 30 dB 33 dB | − o| f fo =10MHz 24 dB 36 dB 48 dB 60 dB 43 dB |f − f |=15MHz 31 dB 47 dB 62 dB 78 dB 55 dB | − o| f f =60MHz 55 dB 83 dB 110 dB 138 dB 60 dB | − o|
Table 2.2: Attenuation of a W-CDMA signal at different offsets for low pass filters.
is fulfilled for offsets above 10 MHz. The 5th order filter also fulfills the attenuation requirement for offsets above 10 MHz. However, the 5th order and 4th order filters fail to meet attenuation requirement at the 5 MHz offset. Actually, the attenuation of the 1st adjacent channel is the hardest to fulfill. If the channel selection must be done in analog domain, the order of filter should be increased. However, the increase of filter order also increases phase and amplitude distortion and power consumption.
A possible choice is that channel selection is partially done in analog domain and digital domain.
To do the channel selection partially in digital domain, the sampling frequency and resolution of the ADC must be considered. From a power consumption point of view, it is encouraged to have as low a sample frequency as possible. When the chip rate of W-CDMA receiver is 3.84 MHz, the sampling frequency must be at least higher than 25 MHz in case of 3rd order filter. If the sampling frequency is lower than 25 MHz such as 15.36 MHz which is four times the chip rate, aliasing of blocker will prevent effective digital filtering. However if the sampling frequency is 30.72
MHz, eight times the chip rate, blockers higher than sampling frequency are already attenuated below the requirements. However, the 3rd order filter only provides 18
26 dB and 36 dB attenuation at 5 MHz and 10 MHz offsets respectively. Therefore, the
ADC dynamic range should be extended by about 16 dB [17]. In the case of the
4th order filter, it is possible to use a sampling frequency of four times the chip rate, namely 15.36 MHz. In this case, the dynamic range of ADC must be extended by about 9 dB to provide remaining filtering in the digital domain. In the case of 5th order, the dynamic range of ADC needs to be extended by only 3 dB. As the filter order increases, dynamic range and sampling frequency of ADC is relaxed. However, power consumption, phase error, and gain error in analog domain increase. Therefore, the order of analog filter must be decided carefully.
2.3 CMOS Continuous Time Filters
In CMOS technologies, the analog channel selection filter design techniques can be divided into continuous filters and sampled data filters [43], [26]. The sampled data filters use several non-overlapping clock phases. Among the sampled data fil- ters, switched capacitor filters are the most popular. The main characteristics of the switched capacitor filters are determined by a clock frequency and by capacitor ratios
[26], [28], [43]. The switched capacitor filter is only used in low frequency such as audio frequency due to requirements for high speed clocks for switching and settling time of amplifier. In contrast to the sampled data filters, analog continuous time
filters directly process analog signals. Owing to the continuous time nature, analog continuous time filters are most suitable for high-dynamic range or high frequency
filtering [30]. A major disadvantage of continuous time filters is that the filter co- efficients are sensitive to process and temperature variations along with aging. For this reason, tuning of the frequency is necessary. Regardless of the high sensitivity
27 to the process and temperature variations, continuous time filters are receiving more attention due to fast data processing capability.
For the realization of fully integrated analog filters, there are many things which must be considered. First, the size of capacitor and resistor should be limited. Since integrated capacitors such as poly insulator poly capacitors or metal insulator metal capacitors occupy a large area, the size of capacitor must be limited. For example, the capacitance can be expressed by
ε ε A C = r 0 (2.2) t where A = area of the capacitor, t = thickness, ε = permittivity = 8.854 10−12F/m. 0 ×
εr = relative permittivity which is usually equal to 3.78 in CMOS. In CMOS, t
is usually equal to 6 10−8m. To get the capacitance of 50 pF, an area of about × (300µm)2 is necessary [28], [38]. This area is relatively large compared to the area
of other active components. The capacitor also should not be too small because of
the effect of parasitic capacitance. Normally, the capacitor must be higher than 0.5
pF [28]. Also large size of passive resistors often contain huge parasitic capacitances,
which highly degrade the linearity of the filter. Therefore, optimum size of capacitors
and resistors must be carefully decided.
Second, frequency response of the filter should be stable. This means that every
element in the filter should have accurate and stable values in the presence of fab-
rication tolerances and temperature variations, but this is almost impossible in an
integrated circuit. In the integrated circuit, the ratio between same resistors or ca-
pacitors can be controlled in relatively accurate, but the absolute values are usually
varied by 20 % [28]. This indicates that the time constant RC can be varied by ± ± 40 %. Furthermore, the quality factor of the filter is highly affected by small errors of
28 the phase and component variation. These process variations require tuning circuits for frequency and quality factor. This extra circuit often becomes a bottleneck in the realization of low power consumption and high dynamic range filter.
Third, analog continuous time filters should be able to handle large signal. For a wide dynamic range required in radio receiver, large signal swings are essential. How- ever, these are increasingly difficult to achieve as power supply voltages are reduced and bandwidth is increased.
Fourth, analog IC filters are often located with data converters and digital circuits on the same chip. In this case, noise due to clock or switching is transferred to the analog filters through substrate or power supply line. This noise highly degrades dynamic range and signal to noise ratio of the analog filter. Therefore, special design and layout techniques are required to minimize the effect of the noise [28].
In CMOS technologies, Active RC, MOSFET-C and Gm-C filters are the most popular baseband filters for wireless communication. Active RC filters usually apply lossy and lossless integrators to attenuate interferers. MOSFET-C filters have similar architecture as active RC filters but replace passive resistors with a triode region transistor. Gm-C filters use transconductors and capacitors to attenuate interferers.
Because of their open loop nature, Gm-C filters have been used for high frequency application. Each filter mentioned has its own advantages and disadvantages in terms of speed, linearity, and tunability. In the next sections, these three most well known continuous time filters are overviewed.
29 2.3.1 Active RC Filter
The most widely known continuous time filter is the active RC filter. Active
RC filters demonstrate good dynamic range and low distortion. Thus, active RC
filters are still widely used in low frequency application. However, low speed due to the negative feedbacks makes the filter difficult to apply for high speed wireless communication system. Usually, the gain bandwidth(GBW) of the amplifier for active
RC filter needs to be around 20 - 30 times higher than the filter cut-off frequency to minimize phase error and any other non-idealities which occur near the GBW [5],
[11], [20]. In the case of WLAN, this implies that the amplifier needs to have 300
MHz GBW when the output load is connected. This GBW is not easy to achieve with low power consumption. Therefore, active RC filters are mostly applied in low frequency application even though the filters demonstrate superior performance.
The active RC integrator is the most basic architecture element of the active RC
filter. Most active RC filters are designed based on the integrator. In the active RC integrator, a capacitor is connected in negative feedback to function as the integrating element and a resistor is used to feed current into the capacitor [23]. Figure 2.7 shows the RC-op amp integrator. If we assume an ideal operational amplifier is used, the relation between the input and output voltage in the s-domain is given by
V (t) V −(t) d[V −(t) V (t)] in − = C − out (2.3) R dt
With i−(t)=0 1 ∞ V (t)= V (t)dt (2.4) out −RC in Z0 1 V V = in (2.5) out −RC s
30 Cn Sn
C1 S1
C
R Vin V - Vout Av(s)
Figure 2.7: RC-OP amp integrator
In the ideal integrator, the time constant is RC and the phase is 90 degrees. However, non-ideal opamp gives an impact on the integrator transfer function and quality factor of the filter [23]. Since op amp has finite dc gain ADC and the finite gain bandwidth
GBW, the transfer function of the op amp can be expressed as
GBW A(s) = (2.6) s + GBW ADC Then the integrator transfer function is changed to the following:
1 V (s) V (s) ≈ − RC in (2.7) out (1 + s )(s + 1 1 ) GBW RC ADC To work as an ideal integrator, GBW and DC gain of the amplifier must be infinite or very high [23]. However, it is difficult to obtain high GBW and DC gain at the same time since high DC gain is usually obtained with a multi-stage amplifier [45].
Therefore, the real integrator only works well in a certain frequency range.
In an active RC integrator, the resistor transfers the input voltage into current, and the feedback capacitor integrates the input current because no current flows to
31 the amplifier input [2], [23]. There are two different integrators: lossy and lossless integrators. Figure 2.7 shows a lossless integrator with binary weighted capacitor array. Lossy integrators are formed by adding a resistor in parallel with the integrating capacitor [2]. Usually opamp is used as an active element, but OTA with high output impedance and large gm can also be used for an integrator [31]. In the ideal case,
the active RC filter is insensitive to parasitic capacitance because it is connected to
a virtual ground or driven by a voltage source [28]. But due to the limited DC gain,
unity gain bandwidth, and output resistance, the parasitic capacitances slightly affect
the transfer function of the integrator.
As shown in equation 2.5, the time constant of the integrator is determined by
R and C. Due to variations in process and temperature, the time constant typically
varies by 50 %. The time constant of an active RC integrator can be tuned using ± series or parallel capacitor or resistor matrices. The series resistor and parallel ca-
pacitor matrices occupy less area [9], [23]. In practice, parallel capacitors as shown
in Figure 2.7 are used because the switch on resistance produces a LHP zero without
shifting the integrator time constant [23]. The size of the switched capacitors are
binary weighted in order to simplify the digital control of time constants. Whether
the CMOS-switches locate at the input or the output of the amplifier depends on the
requirements. At the inverting input node, the switch on-resistance has almost no
effect on the linearity, but the parasitic capacitances of the switch are added to the
inverting input [20], [23]. Alternatively, at the output node, the switch on resistance
degrades the linearity, particularly at high frequencies, but the parasitic capacitances
of the switches have minimal effect on the performance of the integrator.
32 In the parallel capacitor array, the limited on-resistance of the CMOS switches used have a minimal effect on the high frequency performance of the integrator since any resistance in series with the integrating capacitor results in a phase lead at high frequencies [23]. This phase lead reduces the high frequency phase lag deriving from the limited bandwidth of the amplifier [38].
There are many different active RC filters. Among them, Tow-Thomas filter,
Ackerberg Mossberg, and Sallen-key filter are the most well known filters. The second order Tow-Thomas and Ackerberg Mossberg filters are usually a combination of lossy, lossless integrators and adder. Adder is simply designed with parallel connection of input resistors at the integrator. Figure 2.8 shows the Tow-Thomas and Ackerberg
Mossberg filters. The Sallen-Key filter uses one amplifier, resistors, and capacitors to realize 2nd order filter. Since the structure is simple and only one amplifier is necessary, Sallen-key filters are widely used as antialias filters. Figure 2.9 shows the
Sallen-key filter. The Tow-Thomas and Sallen-key filters will be discussed in more detail in the later chapters.
2.3.2 MOSFET-C Filter
The MOSFET -C Filters are basically active RC filters but with tunable CMOS triode region transistors in place of the resistors [20], [28]. Therefore, the time con- stant can be tuned by controlling the gate voltage Vc [28], [39].
The advantage of the MOSFET-C filter is that the resistance is controlled by a control voltage, VC , resulting in an extended tuning range as the resistance increases to infinity [30], [48]. However, very high resistance values cannot be used in practice because of device mismatches and noise. In addition, rather high control voltage,
33 R1 R4
C2 C1 Vin R3 R` R2 R` V BP
V LP
(a)
R4 R` R1
R` C2 C1 Vin R3 R2
V BP V LP
(b)
Figure 2.8: (a):Tow-Thomas Filter (b): Ackerberg-Mossberg Filter
C1
Vin R1 R2 Vout K C2
Figure 2.9: Sallen-Key Filter
34 + V D i DS Vs
Vc
i DS -
-V D Vs
Figure 2.10: Fully differential MOS-resistor
VC is required to ensure the triode region operation of the transistor. However, this makes it difficult to achieve a large signal swing when supply voltage is low. Moreover,
MOSFET-C filtering technique is based on voltage mode opamp so that only a modern high-frequency performance is achieved [26], [39], [48].
The tunable CMOS resistors eliminate the use of capacitor matrices for time constant tuning. However, the triode region MOS resistor produces harmonics when the input signal is increased [28], [43]. Generally, the voltage difference between drain and source, VDS should be smaller than 20 % of the voltage difference between gate and threshold voltage, V -V [28], to ensure low harmonic components. If V V is G th G − th
1V, VDS should be smaller than 200 mV. However, if a fully differential structure as
shown in Figure 2.10 is used, the even order harmonics can be eliminated and increase
+ − the linearity [28], [38], [48]. In triode region, small signal current iDS and iDC are
W 1 i+ = µC [(V V V )(V V ) (V V )2] (2.8) DS ox L C − th − S D − S − 2 D − S W 1 i− = µC [(V V V )( V V ) ( V V )2] (2.9) DS ox L C − th − S − D − S − 2 − D − S If the above equations are subtracted.
W i = i+ i− = µC (V V )2V DS − DS ox L C − th DS 35 2V 1 then R = DS = (2.10) i+ i− µC W (V V ) DS − DS ox L c − th So, the second order equation is cancelled and the current difference is proportional to VDS and controlled by VC . As long as the transistors are in the triode region, linear
resistance can be achieved.
Usually, MOSFET-C filter can be realized when passive resistors in the filter are re-
placed with triode region MOSFETs [28], [27]. However, parasitic capacitiances of the
triode region transistor can affect the performance of the filter [28], [38]. Consequently
filter architecture insensitive to parasitics should be used. Parasitic capacitance, CP ,
can be minimized when it is connected to virtual ground or output of opamp. Figure
2.11 shows the suitable filter structure for MOSFET-C filter realization. Charge and
dischrge of Cp1 by Vs do not affect the performance. Also, the top and bottom plates
R or C
V s Vo C p1 C p2
C p3
Figure 2.11: The filter structure suitable for MOSFET-C filter
of Cp2 are connected to virtual ground and signal ground respectively. Therefore, this parasitic capacitance does not affect the performance. Output parasitic capacitance
36 Cp3 is connected to low impedance output node so the charge and discharge of the parasitic capacitance do not affet the filter much. According to Figure 2.11, a Tow thomas filter or a Sallen-key filter is a suitable structure for MOSFET-C filter [28],
[50].
2.3.3 OTA-C filter
OTA-C filters are more suited to high speed applications as opposed to the ac- tive RC and MOSFET-C filters described in the previous sections since they can be used in an open-loop configuration and thus need not be constrained by the stability requirement [18], [48], [49]. Even though OTA-C filter is often mentioned as Gm-C
filter. OTA is basically different from a transconductor. OTA is an op amp without a low impedance output stage, ideally operating with a virtual ground at its input and whose transconductance value is almost irrelevant as long as its voltage gain is high
[48]. A transconductor is a simply voltage controlled current source [48]. However,
OTA-C or Gm-C filters usually have identical filter structures and functions, OTA-C
filter in this section also includes Gm-C filter.
The drawback of using OTA in an open loop configuration is that the circuit is limited to very small input levels in order to operate the transconductor in linear region [43], [48]. Even though many different techniques have been reported to in- crease the input range while maintaining linearity, these techniques often degrade the frequency response due to additional parasitics [26], [43]. Even with the linearization technique, the input signal swing range is still small compared to the active -RC fil- ters. Another drawback of OTA-C filters is their dependence on the parameter gm
37 Vin
Out
C L
Figure 2.12: Gm-C integrator
which makes them highly susceptible to process variations. This drawback can be accounted by including some kind of automatic tuning [26].
Gm-C integrator is a basic block of the OTA-C filter. In a Gm-C integrator, the transconductance (gm) and integration capacitor C determine the unity gain frequency of the integrator. Instead of a simple transconductor, the operational transconductance amplifier (OTA) can be used. Figure 2.12 shows a Gm -C inte- grator. The input is fed into the transconductor of transconductance Gm and the output current of the transconductor is integrated by a capacitor.
gm Vo(s) = Vin(s) (2.11) sCL In a Gm-C integrator, the integration is a passive operation because the transcon- ductor merely transforms the input signal into another form [25]. Therefore, in the case of a summing operation, N transconductors are required to add N inputs. This is a clear drawback compared to active RC filters.
Figure 2.13 shows the 1st order OTA-C filters. One advantage of the OTA-C
filter is that passive components like the resistor and inductor can be realized with
OTA and capacitor [28], [38]. As shown in the Figure 2.13, the resistor is realized by connecting negative input of OTA to positive output and the function of inductor
38 Vin C Vo Vin Vo gm1 C gm2 gm2
C Vo Vo
R=1/gm gm 1 V in Vin C R=1/gm 2
(a) Low pass (b) High pass
C
Vin Vo Vo gm1 gm2 gm1 C2 gm2 C1 gm3
gyrator L R
C Vo Vo
R=1/gm2 Vin -gm1Vin L C1 R
(d) RLC (c) All pass
Figure 2.13: 1st order OTA-C filters
can be realized in certain frequency by using two OTAs and a capacitor. However, linearity of the resistors and the inductors is highly dependent on the performance of OTA. Therefore, passive resistors are often used when high linearity is required.
Figure 2.14 shows the fully differential OTA-C biquad filter. As shown in the Figure, low pass and band pass functions can be obtained from the biquad OTA-C. In this
filter, the passive resistor is replaced with OTA by negative feedback connection. This
filter is 2nd order. For the higher order filter, this biquad filter can be cascaded.
39 Vin+ Vo+
gm4 gm5 gm1 gm2 gm3
Vo- Vin-
Figure 2.14: OTA-C biquad filter
2.3.4 Tuning of filter
In order to keep filter bandwidth relatively constant with temperature and process variations, the analog filter must have a tuning circuit. The tuning circuit provides tuning signal to control time constant and Q value of filter. The filter’s time constant can be controlled in several ways. In a Gm-C filter, bias current of transconductor is controlled to vary the transconductance. Since the time constant of Gm-C filter is proportional to the inverse of transconductance, the frequency can be shifted by varying the transconductance [39], [28], [18]. In an active RC filter, binary weighted capacitor matrices are used to change the time constant. In MOSFET-C filter, gate voltage of MOS-resistor controls the resistance of the filter and change the time con- stant.
For easy and effective tuning of analog filter, there are several things which need to be considered before the design. First, the frequency and quality factor needs to be tuned independently. Sometimes the tuning of frequency causes the change of
40 quality factor which degrades the performance of filter. Usually, in a biquad filter, the frequency and quality factor can be tuned separately.
Second, it is desirable to use the same value of R and C in the filter. If this is impossible, it is recommended to choose an integer ratio of resistor or capacitor values for better matching. Instead of resistor matrices, capacitor matrices are normally used for tuning since they are better in matching the components.
Third, parasitic insensitive filter architecture is desired. Usually, a filter based on the signal flow graph is insensitive to parasitics.
For the tuning, the output of the filter must be compared with another reference frequency. The reference frequency or signal usually comes from the outside of the chip [25], [18], [38]. There are many different tuning systems such as adaptive tuning circuit, direct tuning strategy, and Master-Slave tuning circuit. Among them, Master-
Slave filter tuning is a widely used tuning method because it is relatively easy to build and demonstrates acceptable accuracy if master and slave filter are well matched [38].
Adaptive tuning circuit requires complex tuning algorithm [24] and direct tuning strategy is not an efficient way for continuous reception receivers [36]. Figure 2.15 shows the block diagram of Master-Slave tuning system.
In this tuning system, two identical filters are often integrated together. Main
filter, which is called a slave filter, is used for filtering of signal and the other filter, a master filter, is used to detect the variation of filter characteristics [38], [28]. The master filter demonstrates characteristics identical to the slave filter. This means that the master and slave filter show identical frequency shift and quality factor change due to process and temperature variation [28], [38]. Therefore, the output of the master filter is used to detect the variations and then phase comparator is used
41 Integrated circuit
Vin Main filter (slave) Vout
F-control Q-control signal signal
Frequency Q Master control control
Vref
Figure 2.15: Block diagram of Master-Slave tuning system
to compare the reference signal to the output of the master filter. If there is any difference between the reference signal and the output of the master filter, tuning signal is applied to correct the variations of the master and slave filters.
Depending on the tuning strategy, the master circuit can be a filter or an oscillator.
If filter is used, the signal delay through the master filter is compared with phase detector and tuned to a predetermined value [36]. If an oscillator is used as the master circuit, the master oscillator is made to track the reference clock in a phase locked loop configuration thereby fixing the time constants of the circuits. When filter is used as master circuit, quality factor of the master filter must be large enough [52].
This requirement often causes the mismatch between master and slave filter. Also the offset voltage of the filter directly affects tuning accuracy. If an oscillator is used as master circuit, offset problem is relaxed, but it is difficult to ensure the oscillation of
42 Oscillator or f control Voltage controlled filter
f ref Master Circuit Phase Detector LPF To Slave Filter
Peak Detector To Slave Filter V I LPF Peak Detector Qcontrol
Figure 2.16: Block diagram of Frequency tuning controller
the master circuit and oscillation amplitude must be limited to be within the linear region of the OTA [52].
Figure 2.16 shows the simplified block diagram of the frequency and Q factor tuning system when simple PLL is used. As phase detector, EXOR gate or analog multiplier is mainly utilized. If EXOR gate is used for phase detection, comparators must be used at the output of main and slave filter to convert the output signals to square waves. In PLL tuning, the output of the VCO or master filter is compared with the reference signal through a phase detector. If there is any difference between reference signal and the output, a certain level of voltage, which is proportional to phase difference between reference signal and VCO or master filter output, is produced and the voltage is filtered through low pass filter to eliminate high frequency component. Then only dc control voltage is applied to both master and main filter to correct the frequency difference. For Q factor control, amplitude detector or peak
43 detector is often used to compare the magnitude at the certain frequency [28]. Like frequency tuning, the peak of the master filter is compared with the reference signal at the certain frequency. Then peak difference is usually amplified and low pass filtered to apply Q factor control voltage to the main filter.
For more detailed discussion regarding tuning circuits, refer to texts [28] and [38].
44 CHAPTER 3
DESIGN OF FILTER AND VGA FOR WLAN
Over the last few years, unlicensed wireless networking has experienced rapid growth and is expected to continue to do so as this technology is adopted in the office, home, and leisure places. WLANs and Bluetooth have gained strong popular- ity in a number of vertical markets, including the health-care, retail, manufacturing, warehousing, and academic arenas [54]. These industries have profited from the pro- ductivity gains of using hand-held terminals and notebook computers to transmit real-time information to centralized hosts for processing. Today, WLANs are becom- ing more widely recognized as a general-purpose connectivity alternative for a broad range of business customers.
As the rapid growth of WLAN market will be evident, the WLAN products must become a common consumer product soon. As a consequence, the prices of the
WLAN products fall under heavy pressure [55]. Thus, many researchers have begun the research to increase the integration rate of the wireless transceiver set. Even though the integration of analog baseband filters are feasible, the wide bandwidth requirement in the WLAN system make the integration of the analog baseband fil- ter challenging. Since the power consumption and noise are usually increased as the
45 bandwidth increases, the integration of the baseband filters and VGAs, while main- taining low power consumption and wide dynamic range, is not easy. Therefore, the design of WLAN baseband requires careful design strategy to minimize power consumption without sacrificing linearity and dynamic range. In this chapter, three different baseband filters and VGAs for WLAN application are discussed.
3.1 Feed forward compensated amplifier based filter and VGA for WLAN application
The past few years has witnessed an emergence of wireless standards with wide channel bandwidth and high data rate capability such as WCDMA, IEEE 802.11a, b etc. Cost considerations favor integrated CMOS transceiver realizations using direct conversion radio architectures. In such architectures, channel selection is done after downconverion from RF to DC by means of highly linear, wide bandwidth integrated lowpass filters. Active-RC filters are typically preferred due to their higher linearity compared to Gm-C implementations. Unfortunately, the need to drive resistive loads makes active-RC wideband design a challenging task. Typically, large bias currents are used to maintain a high Opamp open loop unity gain frequency. However, the use of above mentioned standards in battery operated portable applications places a great premium on the device power consumption. Therefore, novel circuit techniques are required that enable realization of highly linear wide band active-RC filters with moderate power consumption. In this section the use of feedforward amplifiers in wide band filter design is introduced. A fourth order low pass Butterworth filter with a cutoff frequency of 10 MHz is implemented by cascading two Tow-Thomas biquads. Additionally a variable gain amplifier (VGA) with a gain range of 36 dB is also realized. Measured results of a prototype CMOS implementation in a 0.5µm
46 technology indicate the possible utility of the designed filter in an IEEE 802.11a receiver analog baseband chain.
3.1.1 Feed forward compensation technique
In spite of their performance, active RC filters are only applied in low frequency.
For high frequency filtering, Gm-C filter is usually applied. However, as explained before, the open loop nature of the Gm-C filter has limited dynamic range. This low dynamic range prevents Gm-C filter applying in wide dynamic range baseband filter.
In the case of active RC filters, the gain bandwidth(GBW) of amplifier should be much higher than the cut-off frequency of the filter because the phase error of the amplifier is increased near the gain bandwidth [39]. Currently, two stage or folded cascode amplifiers have been the most common structures for the active filter applications.
For accurate and fast output response of the filter, the amplifiers must have a high dc gain and a wide gain bandwidth product [45], [5]. For a low frequency filter, two stage and folded cascode amplifiers work well since their gain bandwidth and dc gain are sufficiently high. However as the filter’s bandwidth increases, the gain and phase errors of amplifiers starts degrading the performance of filter. These errors are mainly due to the low dc gain and gain bandwidth of the amplifier.
In the case of two stage amplifier, miller compensation techniques are usually used to ensure stability. In this technique, the compensation capacitor pushes dominant pole to lower frequency as shown below [18], [2].
1 ω = (3.1) d R Cc(1 + gain of the second stage) ·
where ωd is the dominant pole frequency, R is the impedance at the input of the
second stage, and Cc is the compensation capacitor.
47 By the miller compensation, the dominant pole and second pole is split and sta- bility of the amplifier is achieved. However, the GBW of the amplifier is decreased as the dominant pole moves toward lower frequency. Since the GBW is approximated as
GainBandwidth = ω A (3.2) d · dc where Adc is dc gain of amplifier, the GBW of the miller compensated amplifier is decreased as ωd decreases.
In the case of the single stage folded cascode amplifier, high gain bandwidth can be achieved with high bias currents and short channel lengths. The limitation of frequency response occurs due to the presence of a non-dominant pole at the source of the cascode device [40]. To make the amplifier stable, the non-dominant pole position must be as large as possible. This is achieved by increasing the transconductance of the cascode device by either increasing the width of the device or the current
flowing through it. However, increasing the width of the cascode device also increases parasitic capacitance but decreases the output impedance, and the increase of the biasing current increases the power consumption. In low supply voltage, too much increase in the biasing current causes the increase of the device size unreasonably [31].
Also the output swing range is restricted because of the cascode structure. Therefore, it is difficult to achieve both high gain and gain bandwidth at the same time.
To achieve both high dc gain and large gain bandwidth, other compensation tech- niques such as feed-forward compensation are encouraged. The feed-forward com- pensation technique provides feed-forward path to create LHP zero. This LHP zero is used to cancel out or minimize the effect of the second pole. Since feed-forward compensation does not use large miller capacitor, the dominant pole is not pushed
48 to lower frequency. Therefore, higher GBW product is achieved. Figure 3.1 shows the schematic of the feed-forward compensation to create LHP zero. If each stage is
Vout Vin G1 (s) G2 (s)
Gf (s)
Figure 3.1: Schematic of the feed-forward compensation
assumed to have a single pole, each stage can be modeled as [45],
G G G G (s)= 1 , G (s)= 2 , G (s)= f (3.3) 1 1+ s 2 1+ s f 1+ s ωp1 ωp2 ωpf where G1 and G2 are dc gain of the first and the second stage, and ωp1 and ωp2 are
dominant pole of the first and the second stage respectively, ωpf is the pole of feed
forward amplifier. The transfer function of the feed-forward compensated amplifier
can be derived as
Vout G1 G2 Gf = s s + s (3.4) Vin (1 + ) (1 + ) (1 + ) ωp1 ωp2 ωpf s s s G1G2(1 + ω )+ Gf (1 + ω 1 )(1 + ω 2 ) = pf p p (3.5) (1 + s )(1 + s )(1 + s ) ωp1 ωp2 ωpf If the transconductance of the second stage and the feedforward stage are designed to have same value, then the ωp2 becomes same as the ωpf because the second stage and
49 feedforward stage have same output impedance. The transfer function now becomes as [45] s V G1G2 + Gf (1 + 1 ) out ≈ ωp (3.6) V (1 + s )(1 + s ) in ωp1 ωp2
Gf s (G1G2 + Gf )(1 + (G1G2+G )ω 1 ) = f p (3.7) (1 + s )(1 + s ) ωp1 ωp2 From the above transfer function, DC gain and right half plane zero are
DC gain ≈ Gf + G1G2 (3.8)
G1G2 z1 ≈ ωp1(1 + ) (3.9) − Gf
If the LHP zero is designed to cancel out the second pole exactly, that is ωp2 =
G1G2 ωp1(1 + ), the feed-forward compensated amplifier now becomes single pole − Gf amplifier. In this case, phase margin of 90 degree is obtained without sacrificing
GBW product. This is the main concept of the feed-forward compensation. However, there can be non-dominant poles in each stage. These non-dominant poles generate additional left half plane zeros. To maximize the effect of feed forward compensation, non dominant poles must be located at much higher frequencies than GBW. To do this, the size of transistors in the signal path should be chosen carefully so as not to produce any significant parasitic capacitances. Since the non-dominant pole can disturb the operation of feed forward compensation, parasitic capacitance at the high impedance node must especially be minimized. [45].
3.1.2 Feed-forward compensated differential difference am- plifier (DDA)
The differential difference amplifier (DDA) is an extension of the concept of the op amp. It has been used in a number of applications including continuous time filters
50 and the implementation of fully-differential MOS switched capacitor filters [16]. The main difference between a conventional op amp and the DDA is the number of input ports. DDA has two differential input ports. Since the DDA has four input ports, two of them can be used for the control of offset voltage. Figure 3.2 shows the schematic of designed DDA with common mode feedbacks. As shown in the Figure 3.2, M1,
M 1 1 M 1 2
M 7 M 8
V b i a s 3
V b i a s 1 V c m 2 V o u t 1 ` V i n 1 M 1 M 2 M 3 M 4 V i n 2 ` V o u t 2 M f 1 M f 2
V c m 1
M f 3 V b i a s 2 M 9 M 5 M 6 M 1 1
C M F B 1 C M F B 2
Figure 3.2: The schematic of feed-forward compensated DDA
M2, M3, and M4 are input ports. Among them, input signals are applied to M1 and
M4. M2 and M3 are used to control the offset voltage. Because of the noise and speed consideration, PMOS is used as input. Since the DDA is designed as a two stage, it is preferable to use the NMOS transistor as second stage. In addition, the overdrive voltage of PMOS transistor is higher than NMOS transistor so PMOS is
51 selected as input transistor. Mf1 and Mf2 are feed forward stages. This is a simple
NMOS differential pair. Mf3 works as tail current sink of Mf1 and Mf2. M9 and M10
are second stage amplifier. To decide the size and bias current of the first, second
and feedforward stages, equations 3.8 and 3.9 can be used. DC gain of the DDA is
expressed as
DCgain = gm (r r r )+(gm (r r ))(gm (r r r )) (3.10) f1 dsf1|| ds11|| ds9 1 ds1|| ds5 9 ds9|| ds11|| dsf1
If the rds of current sink M5 and current source M11 are much higher than other
transistors, the DC gain is approximated as
DCgain ≈ gm (r r )+(gm r gm r r ) (3.11) f1 dsf1|| ds9 1 ds1 9 ds9|| dsf1
From the equation 3.9, the location of zero is decided as
gm (r r )gm (r r r ) z ≈ ω (1 + 1 ds1|| ds5 9 ds9|| ds11|| dsf1 ) (3.12) DDA p1 gm (r r r ) f1 dsf1|| ds11|| ds9 gm r gm (r r ) ≈ ω (1 + 1 ds1 9 ds9|| dsf1 ) (3.13) p1 gm (r r ) f1 dsf1|| ds9 According to the equation 3.11 and 3.13, high dc gain is obtained when transcon- ductances and rds of first, second and feedforward stage are large. However if the gain of first stage and second stage are too high, the zero is placed at a very high frequency. To cancel out the zero, the second pole, which is generated by the second stage, must be located at the same frequency as zero. To obtain this, the size of M9
and bias current must be highly increased. In that case, the parasitics due to the
increase of the size can make the stability worse, and power consumption of the DDA
must be increased. To place the zero at the reasonable frequency, either the gain of
the feedforward stage needs to be increased or the gain of the first and second stage
needs to be decreased. To increase the dominant pole frequency, the gain of the first
52 stage is decreased. The gain of the feedforward stage is increased to lower the zero to feasible frequency.
Even though zero and second pole are placed on the same frequency, the phase margin of the amplifier can be worse because of parasitics of the transistors. There- fore, it is very important to minimize effect of parasitics to achieve successful feed forward compensated amplifier. Although the amplifier is stable without any com- pensation capacitor, 50 fF is used as compensation capacitor to ensure the stability of the DDA. This small capacitor guarantees the stability of the amplifier in a worst case scenario. Since the capacitor is so small, it does not degrade gain bandwidth significantly.
In the feed forward compensated DDA, the noise contribution of the Mf1 and Mf2
must be investigated. The dc gain and zero frequency are highly affected according
to the transconductance variation of feedforward stage. High transconductance of
feedforward stage will increase the dc gain, and the increase of the transconductance
will make the input referred noise due to feedforward stage smaller. The input referred
thermal noise of the Figure 3.2 is calculated as follows. The input referred noise
contribution of M9, M10, M11, M12, Mf1 and Mf2 is below:
16kT V 2 = (g + g + g )(r r r )2 N |M9,10,11,12,f1,f2 3 m9 m11 mf1 O9|| O11|| Of1 × 1 h 1 2 2 + 2 2 2 2 (3.14) gmf1(rO9 rO11 rOf1) gm1gmf1(rO1 rO3 rO5) (rO9 rO11 rOf1) || || || || || || i
16kT 1 1 = (gm9 + gm11 + gmf1) 2 + 2 2 2 (3.15) 3 × gmf1 gm1gmf1(rO1 rO3 rO5) ) h || || i and the input referred noise contribution of M1−6 is as follows:
2 8kT gm1 + gm3 + gm5 VN M1−M6 =2 ( 2 ) (3.16) | × 3 gm1 53 Then the total input referred noise of the Figure 3.2 is expressed as:
16kT V 2 = (g + g + g ) N,total 3 m9 m11 mf1 × 1 h 1 gm1 + gm3 + gm5 2 + 2 2 2 + 2 (3.17) gmf1 gm1gmf1(rO1 rO3 rO5) gm1 || || i According to the equation 3.17, the transconductances of input transistor and feed- forward stage must be large enough to reduce the input referred noise. In an ordinary second stage amplifier, the input referred noise contribution of second stage is small since the noise is divided by gain of the first and second stage [35]. However, in the feed forward compensated amplifier, the noise due to feedforward compensation must be considered. As shown in the equation 3.17, total input referred noise can be higher than ordinary second stage amplifier. Since the effect of second and feedforward stage noise is dependent on the transconductance of feedforward stage, the transconduc- tance of feedforward stage must be well optimized to achieve both high dc gain and low noise.
3.1.3 Design of active RC filter and VGA
For the design of WLAN filter, the fully differential version of Tow-Thomas filter is used. Figure 3.3 shows the schematic of the filter and VGA. The advantage of
Tow-Thomas filter involves its ability to tune frequency and Q factor independently
[38], [19]. Also, resistors in the feedback path can be replaced with MOS transistors in triode region. Since input resistor at the first integrator of the Tow-Thomas filter is used to feed the current, the voltage signal is changed to small current signal through the input resistor. So signal swing after the input resistor is not large. The small signal swing will not cause any significant harmonic component and will not make
MOS transistor out of linear region. According to the Figure 3.3, input resistor of the
54 filter is omitted and directly connected to the output of the VGA. This is possible since the filter receives a current signal from the output of the VGA. In the schematic of the filter, MOS transistors in the triode region are used with passive resistors to increase tunability of the filter. In the case of MR1, only MOS transistor in the triode region is used since the current signal swing at the source is small.
MR2 SW 1 MR1
SW 2 C1 MR3 C2 Vcm i+ Vout+ Vin+ SWn Ra M3 M4 DDA DDA Vtune i- Vin- M1 M2 Vout-
bias
Low Pass Filter VGA
Figure 3.3: The Merged Filter and VGA
Since input resistor is omitted, the output of the Tow-Thomas filter can be ex- pressed as [38]
1 V = V + V − = (MR3)C2 out out − out s × −1 1 (MR2)C1 (V + V − )+ C1 (i+ i−) (3.18) s + 1 out − out s + 1 − (MR1)C1 C1(MR1) 55 1 V = − (MR3)C1C2 (i+ i−) (3.19) out 2 1 1 s + (MR1)C1 s + (MR3)(MR2)C1C2 − In the equation 3.18 and 3.19, i+ and i− are the current signal from the transcon-
ductor. Comparing the equation 3.19 to the standard form of Tow-Thomas biquad,
ωo and Q factor are obtained as follows.
1 MR1 C1 ωo = , Q = (3.20) s(MR2)(MR3)C1C2 (MR2)(MR3)rC2 An important property of the biquad circuitp is that it can be orthogonally tuned.
ωo can be tuned by adjusting MR3, and Q can be tuned by adjusting MR1 without changing ωo.
The VGA is realized with the switched resistor chain. 3 dB step attenuation is achieved with digitally programmable switches. When the transconductance as shown in the Figure 3.3 is realized with a simple differential pair, a significant amount of distortion results [23]. To avoid the distortion, low signal levels or large gate voltages should be applied when simple differential pairs are used as the transconductance element. Otherwise, distortion reduction techniques must be used. A widely used distortion reduction technique is the source degeneration technique. The linearity of a source degenerated differential pair increases with the degeneration resistance. How- ever, it may be difficult to realize very large source degeneration resistance without sacrificing significant dynamic and tuning range in low supply voltages [23]. Fur- thermore, heavily degenerated transconductances lead to large time constants so this technique is not the optimal choice for a wide bandwidth transconductor. Transcon- ductance of the MOS transistor is linear in the triode region if the drain source voltage
56 of the transistor is kept constant. For the linearity consideration of VGA, two input transistors, M1 and M2 operate in the triode region. To pin the drains of M1 and
M2 at a fixed potential Vtune, the source followers, M3 and M4, are used. Each VGA
stage provides 18 dB gain in 3 dB steps.
Figure 3.4 shows the schematic of the active RC filter and VGA for WLAN ap-
plication. Fourth order Tow-Thomas active RC filter is used to provide the cut-off
frequency of 10 MHz, and the attenuation between 10 MHz and 35 MHz is 36 dB.
The bandwidth of the filter is tuned with the MOS-resistor and the bandwidth can
be varied from 10 to 20 MHz with the gate voltage control of the MOS resistor. Two
VGAs are used to provide the 36 dB gain range.
High pass filter is applied to attenuate the static dc offset. In the WLAN appli-
cation, the use of high pass filter will not cause any significant loss of information
if the cut-off frequency is around 0.1 % of chip rate [34]. To achieve the low cut-off
frequency in the high pass filter, C or R must be very high. If a poly resistor is used to
realize high resistance, substantial amount of parasitics will impact the performance
of the filter [34]. So, MOS transistor in the triode region is used to realize high re-
sistance. To achieve 10 KHz cut-off frequency, two 10 pF capacitors and two MOS
transistors in triode region are used. Although higher order high pass filter reduces
the 3 dB cut-off frequency, it increases the inter symbol interference. Therefore, 1st
order high pass filter is implemented for the dc offset cancelation. For the amplifier
of the high pass filter, a simple transconductor as same as in the VGA is used.
The VGA stage is merged with the Tow-Thomas Filter. To minimize the distortion
due to the large signal swing at the input of transconductor, input signal swing
range at the transconductor is carefully decided. The function of VGA is realized
57 with switched resistor chain attenuator at the input of each transconductor. The attenuator attenuates signal in 3 dB step. The attenuation range of each VGA is from 0 to -18 dB. Since the transconductor of each VGA provides 18 dB gain, total
VGA gain range becomes 36 dB.
MR2 SW 1 MR1
SW 2 C1 C2 Vcm MR3 Vcm Vgate SWn i+ Ra DDA DDA Vin+ M3 M4 M3 M4 Vtune Vtune i- M1 M2 M1 M2
Vin- bias bias
High Pass Filter VGA 1 Low Pass Filter 1
MR2 SW 1 MR1
C1 SW 2 C2 MR3 Vcm
Vout+ i+ SWn Ra DDA DDA M4 M3 Vtune i- Vout- M2 M1
bias
Low Pass Filter 2 VGA2
Figure 3.4: The Merged Filter and VGA for WLAN application
58 3.1.4 Test Results
In order to verify the operation of the circuits presented in previous sections, a monolithic realization of the filter and VGA for WLAN application was done in AMI
0.5µ CMOS technology available through MOSIS. The process offers three metal and two poly layers with a high resistance implant available for realizing large resistor values. The nominal NMOS and PMOS threshold voltages are approximately 0.7V and 1V respectively and the recommended supply voltage is 5V.
The chip microphotograph of the filter and VGA is shown in Figure 3.5. A pro- totype board was fabricated to experimentally verify the performance of the filter and VGA. A supply voltage of 3 V is used. Figure 3.6 shows the frequency and phase response of the feedforward compensated DDA. To check the phase margin and gain bandwidth of the DDA, output load of 5pF was used. With this load, gain bandwidth and phase margin is 220 MHz and 88 degree respectively. The dc gain is approximately 64 dB.
To check the stability of the DDA, unity gain feedback was applied to the DDA and the corner simulations were performed with output load of 6pF. Figure 3.7 shows the corner simulation result of the unity gain feedback buffer. When NMOS and
PMOS transistors were in slow-slow mode and applied temperature was 90 degrees
Celsius, the 2.3 dB ripple was occurred at 45 MHz frequency. Except in this case, other corner simulation results were acceptable. The feedforward compensated DDA was measured with oscilloscope. The unity gain feedback was connected between input and output, and then 1.6 VPP pulse signal was applied to the input of the DDA
to check the stability of the amplifier. The DDA was loaded by a capacitor of 6 pF.
Figure 3.8 shows the output response of the DDA in a time domain. As shown in the
59 Figure 3.5: Test chip microphotograph
Figure 3.8, there is no distinct ringing or peaking in the measured pulse response.
The AC magnitude of the filter and VGA was measured with spectrum analyzer.
To drive the pad and other external capacitive load, two output buffers were imple- mented on chip. The measured AC magnitude response of the filter is shown in Figure
3.9. a in the Figure shows the AC response of the filter before the tuning signal is applied and b shows the AC response after the tuning signal is applied. Because of the process variation of the capacitors implemented in the high pass filter, the cut-off frequency of high pass filter was observed as 280 KHz before the tuning. To compen- sate the frequency shift, control voltages were applied to the gates of MOS-resistors which are implemented in the high pass filter and low pass filter. After the tuning, the measured 3 dB bandwidth of the low pass filter and high pass filter are 10.1 MHz
60 Figure 3.6: Frequency and phase response of the feedforward compensated DDA
and 36 KHz respectively. The attenuation between 10 MHz and 35 MHz is more than
35 dB.
To check the tunability of the filter, the frequency and Q factor control voltages were applied to the filter. The frequency and Q factor control voltages were applied to gate of MOS-resistor and the variations were measured. Figure 3.10 shows the measured AC magnitude response when frequency tuning signal was applied. As shown in the Figure, the cut-off frequency of the filter can be expanded to around 20
MHz.
Figure 3.11 shows the measurement result of Q factor variations when Q factor control voltage is applied. According to different control voltage, Q factor of the filter is varied as expected and the Q factor and bandwidth can be tuned independently.
61 Figure 3.7: Simulation result of corner simulations
Figure 3.8: Measured square wave input response of the DDA
62 b 0
a −10
−20
−30 dB
−40
−50
−60
−70 5 6 7 8 10 10 10 10 Frequency [Hz]
Figure 3.9: Measurement result of AC magnitude of the Filter
0
−10
−20
−30 gain [dB]
−40
−50
−60
−70 5 6 7 10 10 10 frequency [Hz]
Figure 3.10: Measurement result of AC magnitude of the Filter when tuning signal was applied
63 0
−10
−20
−30 gain [dB]
−40
−50
−60
−70 5 6 7 10 10 10 frequency [Hz]
Figure 3.11: Measurement result of Q factor variations
The AC magnitude of the VGA gain variations were measured. The measured gain range was 36 dB. Figure 3.12 shows the measured output response of the filter and VGA according to different gain settings. Since the bandwidth of VGA was wide enough, the cut-off frequency is almost constant according to different gain setting.
Figure 3.13 shows measurement result of the two tone test of the filter and VGA.
1 MHz and 1.5 MHz sine wave signals were applied and the intermodulation product located at 2 MHz was measured. The third order intermodulation components at 2
MHz is found to be 56 dB below the fundamental. Table 3.1 shows the summary of the test results.
64 40
30
20
10
0
−10
gain [dB] −20
−30
−40
−50
−60
−70 5 6 7 10 10 10 frequency [Hz]
Figure 3.12: Measurement result of gain variations of Filter and VGA
0
Fundamental −10
−20
−30
−40
−50 dB
−60 IM3
−70
−80
−90
−100 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 6 Frequency [Hz] x 10
Figure 3.13: Measurement result of two tone test of the filter and VGA
65 Parameter Test results Technology 0.5 µm Area 1300 µm 1300 µm × Supply Voltage 3.0 V Power Consumption 22 mW Stop band attenuation 40 dB DC notch filter attenuation 16 dB Gain step 3 dB Gain range 36 dB IIP3 (in band) 13 dBV Integrated noise 114µVrms SFDR 62 dB
Table 3.1: Test results of feed forward compensated amplifier based filter and VGA
3.2 Fully differential buffer based filter and VGA for WLAN application
This section presents fully differential buffer based filter and VGA for WLAN application. Since WLAN receiver requires a wide bandwidth low pass filter, the active amplifier of the filter must demonstrate high gain and wide gain bandwidth.
Voltage buffer usually has a wide frequency range and is capable of driving a small resistive load. Therefore, the voltage buffer has been applied for wide bandwidth filter realization. Usually, the buffer is designed by applying negative feedback loop between input and output of op amp or OTA. This kind of buffer shows good dynamic range and frequency response. However, the negative feedback stability must be considered carefully at the operating frequency range. Elwan’s fully differential buffer does not require this negative feedback so the feedback stability is not a concern. Furthermore, the buffer does not need any common mode feedback circuit since the gain of the
66 circuit is only 6 dB. The fully differential buffer based filter and VGA were designed in 0.18 µm technology. The designed filter and VGA can be applied in multi-standard receivers because the designed filter’s cut-off frequency can be varied according to different standard.
3.2.1 Fully differential buffer
For the proper filtering of interference, the phase error or other nonlinearities of the active component should not affect the cut-off frequency. To minimize the error, the gain bandwidth product must be high enough. Usually, in the case of active RC
filters, the gain bandwidth product needs to be at least 10 30 times higher than ∼ the filter’s cut-off frequency to minimize the effect of phase and gain errors of the amplifier. For 10 MHz cut-off frequency, the gain bandwidth of active filter must be around 100 300 MHz. Furthermore, the gain of active component should not vary ∼ much in the signal band of filter for an accurate output response.
If the active component of the filter can be obtained with simple and economic structure, the design and layout time of the filter would be saved. Also if VGA uses the same amplifier as the filter, the design time will be greatly saved. For this reason,
Elwan’s fully differential buffer was adopted to design the filter and attenuator. The fully differential buffer is able to provide 6 dB gain and 0 dB gain and demonstrates good frequency response [12]. Unlike the normal buffer amplifier, the Elwan’s fully differential buffer is not realized by negative feedback between input and output of high gain amplifier. The function of buffer is obtained from the source follower based structure. Since this buffer does not use any feedback between input and output, negative feedback stability is not a concern and the frequency response is fast. Also,
67 the buffer does not require any common mode feedback so that the common mode feedback stability is not a problem. However, the buffer’s input stage must be carefully designed so as not to affect the input signal swing. Since the function of buffer is realized with source follower based transistors, the input signal swing is directly affected by over drive voltage. To increase the input signal swing, the over drive voltage of input stage must be maximized.
Figure 3.14 shows the schematic of the fully differential buffer. The identical buffer circuit can be used to obtain 6 dB or 0 dB. For the 6 dB gain buffer, the input
M15 M13 M14
M17 Ib M16
Vo - Vo + V1 V2 M6 M5 M1 M2 M3 M4
Ib Vb1 Vb2
M10 M9 M7 M8 M11 M12
Figure 3.14: Fully Differential Buffer
signal voltages are applied to the differential pair transistors M1 and M2. The drain
currents of M1 and M2 are the same as the drain current of M5 and M3 respectively.
Since M1 - M6 are all matched and the transistor M7, M8 and M9 sink the same tail
currents, the drain current of M6 and M4 are equal to the drain current of M1 and
68 M2. Therefore, the bias current Ib can be expressed by [10]
IM1 + IM2 = Ia IM1 + IM5 = Ia (3.21)
Since the dimensionally matched differential pair carries equal differential and com-
mon mode currents, the output voltages can be expressed by
V = V (V V ) and V = V +(V V ) (3.22) o+ b1 − 1 − 2 o− b2 1 − 2
where Vb1 and V b2 are bias voltages of the circuit [10]. The differential output voltage
is then calculated by [10]
V = V V =2 (V V )+(V V ) (3.23) o o+ − o− · 2 − 1 b1 − b2
If the bias voltage Vb1 and Vb2 are equal, the differential input signal is amplified by
2 times which is 6 dB. For the 0 dB gain buffer, the differential inputs are applied to
Vb1 and Vb2 and the bias voltage is applied to V1 and V2. Then the output Vo+ and
Vo− are
V = V (V V ) and V = V (V V ) (3.24) o+ 1 − b1 − b2 o− 2 − b1 − b2
And the differential output voltage Vo is
V = V V = V V (V V )+(V V )= V V (3.25) o o+ − o− 1 − 2 − b1 − b2 b1 − b2 1 − 2
which is equal to the differential input voltage. Therefore, a 6 dB gain and 0 dB gain
buffer circuits are realized with identical buffer circuit by simple exchange of input
signals and bias voltages.
The fully differential buffer circuit has some advantages. First, the fully differential
buffer does not require any common mode feedback circuitry. The output common
mode voltage is controlled with the change of the dc bias voltage Vb1 and Vb2. The
69 transistors M7, M8 and M9 are biased to sink same currents and the transistor M1
- M6 are all matched. So the change of dc bias voltages changes the current of M6
and M4. Also the negative feedback components M16 and M17 ensure that output
common mode voltages are held at the midrail value. If Vo+ increases, the current of
M6 increases. M16 flows more currents and Vo+ decreases.
Second, the buffer circuit has a wide bandwidth that is required for the design
of the wide band filter and VGA. No feedback loop is necessary between input and
output to obtain the function of buffer. Therefore, instability caused by feedback
loop is not occurred. The output impedance is lowered because of the feedback
components M16 and M17. So the cascade of several stages are easily realized with
the fully differential buffers.
3.2.2 Design of the WLAN filter and VGA
Figure 3.15 shows the multi-standard WLAN receiver architecture. The receiver
is based on the Wide Band IF receiver structure. The first intermediate frequency is
chosen such that the two desired bands are images of each other [29]. Band selection
is achieved by adding or subtracting the outputs of the second mixer. The receiver is
capable of processing IEEE 802.11a and 11.b band. The selectivity is provided by the
low pass filter whose cut-off frequency is programmable to select the desired channel.
To simplify the design of the channel select filter and VGA, it is encouraged to
use an identical active element for both filter and VGA. The presented VGA/filter
is a programmable gain filter which has programmable bandwidths of 5M, 10M and
20MHz and incorporates digitally tunable filter coefficients, programmable gain of -6
70 Wideband IF Channel I
VGA 0 fc = 5, 10, 20MHz LNA 90 RF LO Band Select Channel Q
Wideband IF VGA
0 fc = 5, 10, 20MHz 90
Figure 3.15: WLAN receiver architecture
to 30 dB with 3 dB gain step. The filter frequency response is tuned with binary- weighted capacitor matrices. Filter sections consist of 4th order LPF and 1st order
HPF. Table 3.2 shows the targeted specification of the VGA and Filter design for the WLAN receiver. According to the Table 3.2, the Filter and VGA for WLAN
Bandwidth 5/10/20 MHz VGA Gain range -6 30 dB ∼ Adjacent CH. attenuation > 21 dB Non-adjacent CH. attenuation > 40 dB Noise Figure < 35 dB IIP3(in-band) > 6 dBV Power Consumption 20mW
Table 3.2: The specification of the filter and VGA for Wireless LAN application
should be programmable to shift 3 dB frequency from 5 to 10 or 20 MHz. In order
71 to remove dc offsets resulting from the self-mixing of LO, a high pass filtering is required. According to [34], 1st order high pass filter will not affect the processing of signal if the cut-off frequency of the high pass filter is around 0.1 % of the chip data rate. This means that the cut-off frequency is around 10 kHz. Since the data of
WLAN is included after around 140 KHz, the high pass filtering will not affect the data processing.
Figure 3.16 shows the schematic of fully differential buffer based WLAN filter and attenuator blocks. Fourth order filter was designed by cascading two 2nd order
High pass filter 6 dB attenuator Multi-standard low pass filter
20MHz 20MHz C2
R20 R20 10MHz 10MHz Vbias R10 R10
5MHz 5MHz + R5 R5 + 12pF + + C1 Vin+ Buffer Buffer Buffer 6 6 dB dB C1 12pF _ _ R5 R5 5MHz 5MHz _ _ Vin- Ibias R10 R10
10MHz 10MHz
R20 R20 20MHz 20MHz C2
C4 20MHz 20MHz
R20 R20 10MHz 10MHz
R10 R10 Vout + + 5MHz 5MHz + + + R5 R5 Buffe C3 Buffer + + 0d r 6dB Buffer Buffer Buffer _ B _ C3 dB 6 6 dB R5 - Vout _ _ 5MHz R5 5MHz _ _ R10 R10
10MHz 10MHz
R20 R20 C4 20MHz 20MHz 3 dB attenuator Multi-standard low pass filter 6 dB attenuator
Figure 3.16: Fully differential buffer based multi standard filter and VGA
72 Sallen-key low pass filters. In terms of band width and power consumption, Sallen-
Key filter architecture has several advantages. Primarily, the Sallen-Key filter uses a unity gain buffer as an active element. So the filter fully utilizes the gain band width of the amplifier to decide the cut-off frequency of the filter. Second, Sallen-key filter requires only one active element to realize second order filter. This means that power consumption is greatly minimized with Sallen-Key filter architecture. In the case of other filter topologies such as leap-frog filters, active gyrator based filters, or active RC
filters, at least two or three active elements are required for the realization of second order function. Third, the Sallen-key filter works well in low pass filter application.
In the case of unity gain buffer based Sallen-key filter, sensitivity to variation is relatively small and frequency range is wide. However, it still requires tuning circuit to minimize the frequency shift due to temperature and process variation. Since binary weighted capacitor matrices show reasonable frequency tuning performance, the capacitor matrices can be used in Sallen-key filters.
In the case of the 2nd order low pass filter, the frequency response and Q can be expressed as 1 ω = (3.26) 0 R R C C r 1 2 t 2 −1 R C R C R C Q = 2 2 + 1 2 1 t (3.27) R1Ct R2Ct − R2C2 hr r r i If same value of R is used for R1 and R2, the frequency response and Q are now
1 ω0 = (3.28) R√CtC2
−1 C C C Q = 2 + 2 t (3.29) Ct Ct − C2 hr r r i
73 Equation 3.28 and 3.29 show that the frequency response of the Sallen-key filter depends on the resistor and the capacitor. Either component can be tuned to correct the associated time constant.
The designed filter has the programmability to accommodate different bandwidths such as 5, 10, and 20MHz. Passive resistors and capacitors are used to select and tune the desired bandwidth. To achieve the multi-standard capability, each low pass filter switch resistance to change the time constant of filter. For example, 5 MHz cut-off frequency is obtained when all switches are open. For 10 MHz corner frequency, the switches for 10 MHz cut-off frequency are closed and then the resistance value for 10
MHz cut-off frequency is obtained by parallel combination of R5 and R10. For 20
MHz cut-off frequency, all switches are closed and the resistance value for 20MHz is obtained by parallel combination of R5, R10 and R20. To tune the frequency and
Q due to the process variation and temperature, the binary weighted capacitors are used.
In wide band systems, it is possible to use a high pass filter with a reasonable corner frequency to remove DC offsets. In this system, the high pass filter is realized with MOS resistors. Since the cut-off frequency of the high pass filter should be low enough, it is inevitable to use large size of resistor and capacitor if we apply normal active filters. To avoid large sizes of capacitors and resistors, the triode region MOS transistor replaces the poly resistor. In the case of WLAN, the information signal is not included until 100 KHz. Therefore, a high pass filter that has a corner frequency lower than 100 KHz can be applied to remove static dc offset. To minimize the loss of data, the corner frequency of the high pass filter is selected as 30 KHz. To achieve 30
KHz corner frequency in a simple passive high pass filter, 12pF of capacitor and 0.5M
74 ohm of resistor is required. However, if we replace the resistor with MOS transistor in triode region, we can eliminate the passive resistor and save the area. To design the 0.5M ohm resistance with MOS transistor, the dimension of the transistor must be determined base on next equation.
1 L R ≈ (3.30) µC (V V ) W ox C − T where µ is mobility, Cox is oxide thickness, VC is gate voltage and VT is threshold
voltage. According to equation 3.30, high resistance can be achieved when the length
of transistor L is large and V V is small. However, small V V can cause C − T C − T the transistor working at the saturation region, V V should be kept above certain C − T voltage level [38]. Furthermore, V V should not limit the input signal swing range. C − T
VC must be reasonably high.
Three attenuators and two filters use 6 dB gain fully differential buffer. 30 dB
gain is achieved when no attenuation is performed. Attenuators are used to attenuate
the signal in 3 dB step. In the attenuator, the resistive chains are incorporated into
the circuit design as a programmable resistive circuit element to allow the control of
resistance digitally [3]. The digital control voltage is applied through MOS switches,
and the resistors are implemented by poly layers in a CMOS process. Poly resistors
used in the attenuators are carefully designed because the attenuation is determined
by ratio of resistor values and larger size of resistors produces more noise. Figure
3.17 shows the 6 dB step attenuator. To apply attenuation, each switch is turned
on and off according to the digital control voltage. For 0 dB attenuation, the first
switch is closed and the other two switches are opened. So the input signal is directly
connected to the input of buffer. If the second switch is closed and other switches are
75 R1 R2 R3 Vin+
SW1 SW2 SW3 Vout+ + + FB (6 dB) _ _ Vout - SW1 SW2 SW3
Vin - R1 R2 R3
Figure 3.17: 6 dB step attenuator
opened, the attenuation is given by
R + R 250Ω + 250Ω 1 = 2 3 = = = 6dB (3.31) R1 + R2 + R3 500Ω + 250Ω + 250Ω 2 −
If the switch 3 is closed and the switches 1 and 2 are opened, the attenuation is given by R 250Ω 1 = 3 = = = 12dB (3.32) R1 + R2 + R3 500Ω + 250Ω + 250Ω 4 −
3.2.3 Test results
The proposed multi-standard filter and VGA chain was designed in 0.18 µm CMOS process. Each filter and attenuator block is designed on 1.8V supply voltage. The total current consumption was 12mA. The high pass filter is designed to provide 30
KHz cut-off frequency. For this cut-off frequency, two 12pF capacitors were used and triode region transistors replaced the resistors. Figure 3.18 shows the simulation result of the high pass filter frequency response. The cut-off frequency of this filter is around 30.17 KHz or approximately 30 KHz. According to the figure, the frequency
76
Figure 3.18: The simulation result of frequency response of the high pass filter
response after 20 MHz falls down gradually. However, this attenuation is not critical since the highest low pass filter cut-off frequency is 20 MHz.
Figure 3.19 shows the simulated frequency response of the cascaded WLAN filter and VGA. Figure 3.19 (a) shows the frequency response of 10 MHz cut-off frequency
filter and VGA and (b) shows the frequency response of 20 MHz cut-off frequency
filter and VGA. The corner frequencies of both filters are almost constant when the
VGA changes gain. As shown in the Figure 3.19, gain is varied in 3dB step.
The designed filter and VGA were fabricated in the 0.18 µm technology and measured. There are some differences between simulation results and measurements due to inaccurate design considerations of output load and process variation. For the measurement, the high pass filter was not fabricated together. The low pass filters and attenuators were only measured to test the frequency variation, linearity, and gain variation. Figure 3.20 shows the layout of the WLAN filter and VGA blocks.
77
(a) (b)
Figure 3.19: The simulated frequency response of the cascaded Filter and VGA blocks
Figure 3.20: The layout of the WLAN filter and VGA
78 when the cut off frequency is set to 10MHz
Figure 3.21: The measured results of the filter and VGA gain variation
The total area of the layout is 1500 µm 1500 µm. Figure 3.21 shows the × frequency response when the filter cut-off frequency is set to 20 MHz and 10 MHz.
For the 10 MHz cut-off frequency, the response was measured only when the gain is maximum.
As shown in the Figure 3.21, a ripple of around 5 dB is observed at the end of the
20MHz band for an input frequency close to 16 MHz. The gain response looks higher than expected. However, if the gain response is compared to the 0 dB gain response, the results show that the gain values are corresponding to gain set up. Figure 3.22 shows the compared results. According to the Figure 3.22, the higher gains are compressing with the frequency compared to 0 dB. In particular, the attenuation of gain is increasing when the gain is set to the maximum gain mode. At the 20 MHz,
79 When the cut-off frequency is set to 10MHz
Figure 3.22: Gain comparison to 0 dB reference
about 5 dB gain is attenuated. This effect may be caused by gain compression and the bandwidth limitation of the amplifier.
Figure 3.23 shows the frequency responses of 10 MHz and 20 MHz low pass filter when the gain is set to 21 dB. In the case of 20 MHz cut-off frequency, there is also about a 5 dB ripple around 16 MHz. The measured cut-off frequencies are 9.5 MHz and 21 MHz. In the case of 10 MHz low pass filter, cut-off frequency is decreased by
0.5 MHz. In contrast, the cut-off frequency of 20 MHz filter is increased by 1 MHz.
In the case of the 10 MHz filter, the decrease of the cut-off frequency is due to the process variation since there is no distinct ripple around 10 MHz. However, in the case of the 20 MHz filter, the increase of the frequency is caused by the ripple around
16 dB. Since the ripple caused the unexpected peak around cut-off frequency, the 3
80 Figure 3.23: The frequency response of 10 MHz and 20 MHz filter
dB frequency was expanded. If the process variation is considered, 3dB frequency change due to the ripple is more than 1 MHz.
Linearity is measured in terms of intermodulation product IIP3. This is done by applying two tones and finding the amplitude of intermodulation product. Two input frequencies were 5MHz and 5.3MHz. The power difference between 5MHz and
4.7MHz is 40.6 dB. Figure 3.24 shows the measured result of the two tone test.
To check the setup time when the gain of the VGA is changed to different value, transient response was performed. Figure 3.25 and Figure 3.26 show the transient response when gain is switched from 30 dB to 9 dB. Figure 3.26 is magnified view of the Figure 3.25. According to the Figure 3.25, 1.2 period is needed to settle the gain.
According to measurement results, it appears that the vital functions of the block are present. Concerning the ripple, 5 dB has been observed at the end of the 20 MHz
81 Figure 3.24: The measured result of two tone test
band. Also 1.5-period is needed to settle the gain when the gain is switched from 30 dB to 9 dB. Table 3.3 shows the summary of the performance.
82 Figure 3.25: The transient response when the gain is switched from 30 dB to 9 dB
Figure 3.26: The magnified view of the Figure 3.25
83 Parameter Test results Technology 0.18 µm Area 1500 µm 1500 µm × Supply Voltage 1.8 V Current Consumption 11.1 mA Stop band attenuation 40 dB Gain step 3 dB Gain range 30 dB IIP3 (in band) 4 dBV
Table 3.3: Test results of Fully differential buffer based filter and VGA
3.3 Folded cascode amplifier and DDA based WLAN VGA and filter
This section discusses the WLAN filter and VGA based on DDA and folded cas- code amplifier. DDA is used for implementation of Sallen-Key filter, and folded cascode amplifier is used to build a VGA. To realize sixth order low pass filter, two third order Sallen-key filters are used. Each third order filter is obtained with the cascade of 1st order passive R and C combination and 2nd order Sallen-key low pass
filter. For the VGA, the ratio between feedback resistor and input resistor is used to obtain gain variation in dB scale.
3.3.1 Folded cascode amplifier and Fully differential buffer based on DDA
In this section, DDA and folded cascode amplifier for WLAN filter and VGA are introduced. As mentioned before, WLAN filter and VGA require high gain bandwidth
(GBW) and large dc gain amplifier. In the case of VGA, the bandwidth must be higher than the cut-off frequency of the filter in any gain mode. If not, the bandwidth of
84 the filter could be dependent on the different gain setting of VGA and phase error of the VGA could affect the performance of the filter. High dc gain of the amplifier is also preferred since large open loop gain linearizes the transfer function of the active amplifier stage. In the negative feedback scheme which is often used in VGA design, gain error is increased as dc gain is decreased.
In terms of gain bandwidth and dc gain, folded cascode amplifier shows reasonable performances. Since cascode stage is used at the output, high dc gain is achieved with single stage amplifier [35]. Also stability issue is not as serious as two stage ampli-
fier. Unlike two stage amplifier, folded cascode amplifier does not require any phase compensation. Therefore, dominant pole of the amplifier is only dependent on the output load. Figure 3.27 shows the schematic of the folded cascode amplifier. Since
M7 M8 C5
M9 M10 Vin- Vin+ M1 M2 Vout+ Vout- M5 M6 C1 C3 C4 C2
Vbias1 Vcn
C6 C7 M11 M3 M4 M12 Vbias2
Figure 3.27: Folded cascode amplifier
source follower buffer stage, M9 and M10 are used at the output, the dominant pole
of the folded cascode amplifier is not highly affected by the output load capacitance.
85 If the pole generated by the source follower is much higher than the dominant pole, the dominant pole and GBW are approximated as
1 ω ≈ (3.33) d (r gm (r r ))(C + C + C ) ds3 5 ds5|| ds7 gs9 gd7 gd5 Then
ω ≈ ω gm r (3.34) GBW d · 1 out
1 ω = GBW (r gm (r r ))(C + C + C ) ds3 5 ds5|| ds7 gs9 gd7 gd5 gm (r gm (r r ))(C + C + C ) (3.35) × 1 ds3 5 ds5|| ds7 gs9 gd7 gd5
As shown in the equation 3.34, the GBW of the folded cascode amplifier is de- cided by the transconductance of the input transistors and output impedance [35].
The output impedance is high due to the cascode structure of the amplifier, but transconductance is dependent on the size and bias current of input transistor. The transconductance of the amplifier is maximized when large W/L ratio and bias current is used according to the well-known equation 3.36:
gm ≈ 2K(W/L)Io (3.36) p To obtain high transconductance, the width W and bias current Io must be increased.
If larger W is used, one of the parasitic pole frequencies decreases remarkably because
of the increasing gate capacitance [31]. That would cause uncontrolled variation. Also
the bias current cannot be increased much without dropping the bias transistor out
of the saturation region. Therefore, it is important to find out optimum value of W
and bias current without increasing unwanted variation. Because of the noise and
86 overdrive voltage consideration, PMOS transistors were selected as input [18]. Also, input transistor channel lengths of the amplifier are kept to a minimum in order to maximize the internal parasitic pole frequency.
Nonlinearity is mainly caused by the changes in the open loop gain as a function of the output voltage [31]. So it is important that the open loop gain is constant over the specified amplitude range. Since the variation of the output conductance and transconductance of the input transistor have effects on the open loop gain, the variations should be minimized. Maximization of the input bias current minimizes the relative variation of the drain current and variation of the transconductance. The other sources of the nonlinearity are the nonlinearities in the passive components.
The input referred thermal noise contribution of folded cascode amplifier is cal- culated as follows.
2 2 2gm7,8 2gm3,4 2 2gm11,12 Vin =8kT + 2 + 2 + 2 + 2 (3.37) 3gm1,2 3gm1,2 gm1,2 gm9,10g m1, 2 (gm9,10gm1,2) The equation 3.37 shows that M3, M4, M7, and M8 are main noise contributor of the folded cascode amplifier. The noise due to source follower stage M9 -M11 can be
ignored. To reduce the noise, the transconductances of M3, M4, M7, and M8 must
be minimized.
For the filter realization, fully differential buffer based on DDA is used. Figure
3.28 shows the schematic of the buffer. As explained before, the differential difference
amplifier (DDA) is an extension of the concept of the op amp. DDA has been used
in number of applications including continuous time filters, the implementation of
fully-differential MOS switched capacitor filters [16]. The main difference between
conventional op amp and DDA is the number of input ports. DDA has two differ-
ential input ports. Since DDA has four input ports, fully differential buffer can be
87 realized as shown in the Figure 3.28. With unity gain feedbacks, the proposed fully
M5 M6
M7 M8
Vcm Ibias2
Vout+ Vout- M1 M2 M3 M4
Vin+ Vin- Ibias1 M9 M10
Figure 3.28: The schematic of DDA
differential buffer exploits the entire frequency operating range of the DDA that is its unity gain frequency [10]. To push the second pole higher than GBW, 70 % of total current consumption was used at the second stage. The high second pole frequency minimizes the size of compensation capacitor because the pole splitting between the dominant pole and the second pole is partially performed by high frequency second pole. Furthermore, the minimum size of compensation capacitor increases dominant pole frequency, and GBW is increased.
Input referred noise is mainly determined by first stage. Since noise of second stage is divided by gain of the first and second stage, input referred noise of the second stage is highly decreased. The input referred thermal noise contribution of the second stage is obtained by dividing the resulting output noise voltage by the
88 total gain [35], and doubling the power.
2 1 V 2 = 2 4kT (g + g )(r r )2 2,3,7,8,9,10 × 3 m7 m9 O7|| O9 g2 (r r )2g2 (r r )2 m1 O1|| O5 m7 O7|| O9 16kT g + g = m7 m9 (3.38) 3 g2 (r r )2g2 m1 O1|| O5 m7 The noise contribution of the first stage is [35]
2 16kT gm1 + gm5 V1,4,5,6 = 2 (3.39) 3 gm1
Then total input referred thermal noise is obtained as follows.
2 2 2 16kT gm7 + gm9 + gm2 gm1 + gm5 Vin = V2,3,7,8,9,10 + V1,4,5,6 = 2 2 + 2 (3.40) 3 gm1(rO1 rO5)gm7 gm1 || As shown in the equation 3.40, the input referred noise contribution of second stage is highly decreased because the noise is divided by g2 (r r )g2 . To minimize the m1 O1|| O5 m7
input referred noise, the transconductance of the current source, M5 and M6, must
be minimized.
3.3.2 DDA based filter and folded cascode amplifier based VGA
Although Gm-C filters are the most common type of continuous time filters
used in integrated circuit applications, another closely related technique involves the
MOSFET-C filters. MOSFET-C filters are similar to fully differential active RC fil-
ters, except resistors are replaced with equivalent MOS resistors operating in the
triode region. A fully differential version of the third order Sallen-Key lowpass fil-
ter is realized with MOSFET-C filters. Because of the linearity consideration, the
MOSFET resistors are used in parallel with passive resistors. Figure 3.29 shows the
tunable MOSFET-C filter. In the Figure 3.29, third order filter was realized by cas-
89 Vg
Rb Rb C2
Vin+ Vo+ Ra Rw Rw C1
Ra Rw Rw C1 Vo- Vin-
C2 Rb Rb
Vg
Figure 3.29: The Tunable MOSFET-C Filter
cading the second order filter and first order filter which is realized with Ra and Ca.
This configuration is only possible in the low pass filter realization. In the second order filter section, two different sets of resistors Rw and Rb are used with switches.
By switching the resistors, the bandwidth of the filter is changed. For example, Rw is for WLAN filter and Rb is for bluetooth filter. Also MOS resistors and poly resistors are combined in parallel because of linearity consideration. If the MOS resistor is used alone, large signal swing at the source of the MOS resistor would cause the transistor out of linear region. But the parallel combination of MOS resistor and passive resistor allows wider signal swing range. The MOS resistors can be used to tune the filter coefficients according to the gate voltage control signal. However, the tunability of the MOS resistor is not large enough because of the parallel combination. Therefore, additional tuning method such as capacitor matrices is often necessary.
90 The filter characteristics are determined by the numerical values of the coefficients in the filter transfer function. For a Butterworth lowpass filter, the bandwidth of the
filter can be varied without changing quality factor by tuning the resistors together.
Programmability can be achieved by using resistors or capacitor arrays [11]. The
filter in Figure 3.29 uses MOS resistors and capacitor array to tune the frequency response.
For VGA realization, the ratio between feedback resistor and input resistor is used as shown in Figure 3.30. By switching the input resistors, the ratio between feedback
R6
R f
Vin+ R1 Vo+
Folded cascode Amp Vo- Vin-
R f
Figure 3.30: The VGA based on the folded cascode amplifier
resistor and input resistor is changed by next relation.
R Gain = F (3.41) − RI where RF is feedback resistor and RI is input resistor. To achieve gain step in dB,
feedback and input resistor ratio should be well defined. Because poly resistors are
sensitive to process variation, the gain variation due to process variation should be
considered. The disadvantage of the VGA based on the inverting amplifier is that the
91 bandwidth is changed according to the input resistor RI . Therefore, the maximum
gain of the VGA should be limited to avoid decrease of the corner frequency lower
than the filter’s 3 dB bandwidth. In the presented VGA, the maximum gain was
limited to 15 dB.
Since the input resistors and feedback resistor increases input referred noise, the
size of the resistors must be minimized. However, the small resistors in the feedback
can affect the stability since loop gain is increased. Also, too small size of input
resistor makes the input impedance small. So reasonable sizes of the resistors, which
satisfy both noise and stability requirement, must be selected carefully. Figure 3.31
shows the schematic of the multi-standard filter and VGA blocks. Two third order
Butterworth lowpass filters are cascaded to realize 6th order filter. The 3 dB frequency
of the filter is 10MHz, and it can shift the cut-off frequency to 11 MHz and 1 MHz
by switching the resistors. Three VGA blocks are used to provide the gain range of
45 dB in steps of 3 dB. To reduce the static dc offset, 1st order high pass filter is
used. The WLAN does not transmit between dc and a hundred KHz. Therefore, if
the 3 dB cut-off frequency of the high pass filter is below than 100 KHz, the static dc
offset will be eliminated without the loss of information. Higher order high pass filter
can be implemented to reduce the cut-off frequency but the higher order filter will
increase the phase error and inter symbol interference. When the cut-off frequency
is around 0.1 % of data rate, the data transmission is not distorted [34]. To achieve
very low cut-off frequency, capacitor and resistor sizes must be large. If the capacitor
is fixed as 10 pF, the size of resistor needs to be around several mega ohm. However,
the implementation of mega ohm range resistor with poly will consume a large area
and produce huge parasitics. Therefore, MOS transistor in the triode region was used
92 MOSRes Vc R6
R f BR BR
Vin+ R1 WR WR Folded DDA DDA cascode Buffer V G Buffer Amp
Vin-
R f Vc
Vc
Vout+ Folded DDA Folded cascode Buffer cascode Vout- Amp WR WR Amp
BR BR
Vc
MOSRes
Figure 3.31: The schematic of the multi-standard filter and VGA
to replace the poly resistor. For MOS transistor in the triode region, W/L of 6µ/40µ
was used. With two cascaded third order filter, more than 35 dB attenuation was
achieved at 35 MHz.
3.3.3 Test results
The filter and VGA blocks based on the DDA and the folded cascode amplifier
were designed in the CMOS 0.5µ technology. The supply voltage is 3V and total
power consumption is 15mW. Figure 3.32 shows the post layout simulation result of
the cascaded Filter and VGA blocks. The cut-off frequency was around 10 MHz and
can be shifted to 11 MHz with tuning. The cut-off frequency was tunable when the
93 MOS resistor values were changed. After the layout, the achieved attenuation was around 36 dB at 35 MHz. To minimize static dc offset, 1st order high pass filter was used. The simulated result of the post layout shows that the cut-off frequency is around 20 KHz. The attenuation at dc is more than 20 dB. In order to check the gain
Figure 3.32: The post layout simulation result of the WLAN filter/VGA blocks
step of the VGA, the post layout of VGA blocks were simulated and compared with schematic simulation result. As shown in the Figure 3.33, the frequency response of post layout case was slightly different around 12MHz. In low gain setting, the post layout simulation result shows a small ripple around the cut-off frequency region.
This small ripple would be caused by additional parasitics in the switches or feedback.
According to the post layout simulation result, the gain step was exactly 3dB. The gain range was 36 dB and this figure shows only 5 different gain steps.
94 Figure 3.33: The post layout simulation result of the VGA
Figure 3.34: The simulated result of low pass filter noise figure
95 Figure 3.35: The simulated result of VGA noise figure
Figure 3.34 and 3.35 show the simulated noise figure of sixth order low pass filter and VGA blocks. The noise figure of the filter shows that the value is minimum around 3 MHz. The noise figure is high around dc because of low frequency flicker noise. However, WLAN system does not transmit information near dc so high noise
figure around dc will not create loss of signal. As the frequency increases, the noise
figure increases. At the cut-off frequency of the filter, the noise figure is around 24 dB. In the case of VGA, the noise figure is slightly higher than the low pas filter.
The folded cascode based VGA was fabricated in 0.5µ CMOS technology. Total area of the VGA was 900 µm 1200µm. Figure 3.36 shows the microphotograph of × the VGA test chip. The VGA was packaged in Dip 40 chip and tested on the bread board. Figure 3.37 shows the measurement result of the VGA.
Since the output load was higher than expected at the design time, the bandwidth of the VGA was lower than the 10 MHz. Because of the load due to bread board and other cable connection, the bandwidth of the VGA was reduced. However, the gain step was almost 3dB as expected. This result shows that the poly resistors used
96 Figure 3.36: The test chip microphotograph
wlan vga 15
10
5
0
−5
gain [dB] −10
−15
−20
−25
−30 5 6 7 10 10 10 frequency [Hz]
Figure 3.37: The measured result of the gain variation
97 Figure 3.38: The measured result of gain variation in time domain
in the VGA are well matched. Figure 3.38 demonstrates the measurement result of the VGA gain variation in time domain. The maximum peak to peak voltage was about 2.5 V in 3.3 supply voltage. Figure 3.39 shows the measurement result of VGA when the square wave input was applied. As shown in the Figure 3.39, there is no indication of significant ringing. This indicates that the VGA blocks are stable.
Figure 3.40 shows the measured result of the two tone test. When 620 and 700 KHz signals were applied, IM3 product was appeared at around 530 KHz. The difference between the fundamental signal and IM3 is around 47 dB when -10 dBm input signal is applied. Table 4.1 shows the summary of the test results.
98 Figure 3.39: The output response of the VGA when pulse input signal was applied
wlan vga imd3 0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100 5 5.5 6 6.5 7 7.5 8 5 frequency [Hz] x 10
Figure 3.40: The measured result of two tone test
99 Parameter Test results Technology 0.5 µm Area (Filter) 1500 µm 1500 µm × Area (VGA) 900 µm 1200 µm × Supply Voltage 3 V Current Consumption (Filter) 3 mA Current Consumption (VGA) 1.8 mA Stop band attenuation 36 dB Gain step 3 dB Gain range 45 dB Gain error +/-0.5 dB IIP3 (in band, Filter) 9 dBV IIP3 (in band, VGA) 11 dBV Input referred noise density Filter:19 nV/√Hz (simulated) VGA :24 nV/√Hz (simulated)
Table 3.4: Test results of the filter and VGA
100 CHAPTER 4
DESIGN OF FILTER AND VGA FOR BASE STATION
Numerous monolithic integrated circuits of mobile radio handsets have been re- ported, but monolithic ICs for base stations have not been reported. This is because the base station requires strong linearity and power compression behavior. Normally, the designs of base station receivers must be related to mobile portables since they use same air interface and protocol [7]. Therefore, there is similarity in transceiver designs between base station and mobile portables. As technology is developed for mobile handsets, the technology is directly applied to the design of base station trans- ceivers. However, the technology for cellular chip-sets is not often suited to the design of base stations. For example, unlike the mobile handset, the base station receivers often adopt wide band data converters for faster and multi-channel data processing.
In this case, I and Q phase separation is not necessary because final down conversion to dc and channel selection is performed in the digital domain. Because the filter and
VGA preceding the wide band data converter is located at the IF, bandwidth of filter and VGA should be wider than baseband channel select filter in the mobile handset and linearity must be higher since wide band ADC requires a wider dynamic range than single channel ADC. Low power consumption is also not a primary design factor
101 in the base station [21]. Higher power consumption is allowed in the base station re- ceiver to increase linearity, but, larger transistors must be used to allow large current
flowing and this increases parasitics at transistors.
In traditional base station receivers, many external filters are used for band and channel selections since integrated filters do not reach the required selectivity and linearity. So the external filters have become the barriers for monolithic IC realization.
The Universal Base Station that employs wideband data converter eliminates many passive analog components. Since channel selection is done in digital domain, the
Universal Base Station receiver does not require I and Q phase separation and highly selective narrow band pass filters prior to the ADC [29]. But it still demands a low
IF band pass filter and VGA to maintain the dynamic range of the wide band ADC.
The band pass filter needs to maintain reasonable selectivity and linearity during the wide signal band. VGA must also not corrupt the linearity of the filter while adjusting the gain of signal. So it must be a challenging task to integrate the band pass filter with VGA to achieve high linearity and wide dynamic range in low IF range. In this chapter, the design of wide band pass filter and VGA for the Universal
Base Station receiver is discussed as well as VGA-Filter combination to achieve the required linearity in the base station is presented. In section 4.1, two different base station receiver architectures are introduced. In section 4.2, system level analysis and calculations are performed with system level simulation results. In section 4.3, the
VGA-Filter combination structure is introduced and explained. In section 4.4, test results of VGA-Filter combination are discussed.
102 4.1 The base station architectures
Figure 4.1 shows a simplified block diagram of a traditional digital base station. In this architecture, the variable frequency synthesizer selects one narrowband channel from an operating range [7]. Several external narrow band pass filters and amplifiers are used to attenuate strong-out of band signals and to accurately recover weak signals as well as strong signals. For this single channel architecture, a variable gain amplifier
AMP ADC
BPF LNA BPF AMP B PF AMP DSP
AMP ADC
Frequency Synthesize r AMP ADC
RSSI
Figure 4.1: Traditional Digital Base Station Architecture
provides automatic gain control to amplify weak signals and attenuate large signals.
As shown in the above figure, the signal must be mixed down, filtered, and the I and Q components separated prior to ADC conversion. Since the demodulator must match amplitude and phase of the I and Q signals in the analog domain, the circuit design of the demodulator is complex as higher order modulation scheme is used [7]. Also
103 the feedback path shown in Figure 4.1 works fine for some applications. However, failure to adjust gain quickly can result in saturation of subsequent processing stages.
To solve the problems that occurred in the traditional base station receiver, the
Universal Base station receiver is introduced. This receiver is based on the Digital
IF receiver architecture. As shown in Figure 4.2, the Universal Base Station uses wideband data converters to allow the capacity from one standard to another standard
[21]. In this design, the front end variable local oscillator has been replaced with a
fixed oscillator and the back end has been replaced with a wide dynamic range ADC, digital tuner and DSP. With this architecture, multi-channel processing is possible at the same time and a transceiver can be programmed to accommodate TDMA, CDMA, or a combination [7]. In the Universal Base station, an IF signal is applied directly
Multi - Channels
WIDE LPF BPF LNA VGA BAND BPF ADC
LPF
NCO Oscillator DSP
Figure 4.2: Universal Base Station Architecture
to the input of wide band ADC so down conversion to baseband, individual channel
104 selection and filtering is done in the digital domain. The Universal Base station has several advantages over the traditional base station. First, multiple channel selection is performed in digital domain so that the channel selection can be controlled easily and quickly. Second, many passive discrete components have been eliminated that formed the tuning and filtering functions. As a result, whole transceiver design time can be saved because the passive components often require adjustment and special handling during assembly. Third, the control of channel selection filter is easier since
DSP controls pass band ripple and cut-off frequency variation [7]. The tuning and
filtering characteristics of the wide band filter in the analog domain can also be controlled through software.
The ADC receives wide band IF signals unlike the ADC in the single channel architecture. Therefore, any nonlinear product in signal band from the preceding stage can be a burden for ADC. As shown in Figure 4.3, the input spectrum of the wide band ADC can contain many intermodulation products of two in-band signals.
This intermodulation product cannot be filtered. In the worst case, the 3rd order intermodulation product can block the desired signal as shown in Figure 4.3. Then the input dynamic range of ADC is highly decreased by the shadowing of the signal with intermodulation product [7], [11]. Therefore, the wide band filter and IF VGA preceding the ADC must not produce any significant power of 3rd order intermodula- tion products in the signal band. Further noise level must be very low not to influence the dynamic range. To maintain the best possible dynamic range of the ADC, the
filtering operation must be accompanied by signal amplification. The combined fil- tering and gain operation ensures that the out-of-band signals are attenuated, while
105 Analog filter response
A B C
(Intermodulation Product of Signal A and B)
Figure 4.3: Input Spectrum of the Wide Band ADC
the desired in-band signal is amplified [11]. This simultaneously improves the linear- ity and overall noise figure of the receiver. For optimum operation of the filter and
VGA, the programmability of the wide band filter and VGA is encouraged because the Universal Base Station controls the frequency tuning and gain variation through
DSP.
4.2 Design Consideration
In Universal Base Stations, The bandwidth of 10 MHz is simultaneously down- converted to an IF frequency suitable for digitizing with a wideband ADC. The pur- pose of a low IF band pass filter and VGA is two-fold: 1) To maintain the dynamic range requirement of the wide band data converter 2) To eliminate out-of-band inter- ference and perform an anti-aliasing operation before sampling. Since the dynamic range of the ADC is highly affected by the performance of the filter and VGA, linear and low noise wide band pass filter and VGA are necessary [44].
106 The dynamic range is inversely proportional to the signal bandwidth if the power consumption is fixed. Therefore, it is difficult to design low noise and highly linear
filter with wide signal bandwidth. Fortunately, power consumption is not a major design factor in base station receiver design. In this section, the filter and VGA structure that satisfies both linearity and noise requirement is discussed. Then the relation between power consumption and dynamic range is studied and the trade off between noise figure and linearity is discussed.
4.2.1 Filter and VGA Structure
As shown in Figure 4.2, the low IF band-pass filter is necessary in the Universal
Base Station receiver. The band width of the filter must be wide to contain the 10
MHz. To reach the expected linearity in the signal band, the out-of-band interferers must be attenuated enough not to cause any significant intermodulation products in the signal band. Pass band ripple also must not exceed 1 dB for the linear signal processing. With the center frequency was selected as 15 MHz, which is the lowest possible, the passband spans 10-20 MHz. To realize the bandpass filter, several low pass and high pass filters are cascaded and the lower and upper cut-off frequencies are independently adjusted. In the case of VGA, 1 dB step gain variation is required for the linear operation and the bandwidth of the VGA must be wide enough not to affect the filter’s cut-off frequency. As mentioned in the 4.1, the combined filtering and gain operation is preferred since the combination simultaneously improves the linearity and overall noise figure of the receiver [11], [6].
Since the linearity and NF are highly affected according to the arrangement of
filter and VGA combination, it is necessary to compare the trade off among the
107 combinations of filter and VGA. Equation 4.1 and 4.2 shows well how noise figure and linearity are affected by the arrangement of individual block [33], [15].
NF 1 NF 1 NF =1+(NF 1) + 2 − + + m − (4.1) T otal 1 − A ··· A A P 1 p1 ··· p(m−1) 2 2 2 1 1 a1 a1b1 2 2 + 2 + 2 (4.2) AIP 3 ≈ AIP 3,1 AIP 3,2 AIP 3,3
In the above equations, NFn is noise figure of nth stage, Apn is gain of nth stage and
AIP 3,n is the IP3 value of nth stage.
According to the equation 4.1, the noise figure after the first stage is divided by
the gain of first and subsequent amplifiers. Therefore, amplification of the first block
does critical role to decrease total NF of a cascaded stages. The IP3 of each stage is
effectively scaled down by the total gain preceding that stage [37]. For low noise and
high linear filter and VGA combination, the amplification must be performed at the
beginning and the latter blocks must be more linear. Figure 4.4 shows the relation
between input signal level and IMFDR3 which is difference between magnitude of
fundamental signal and magnitude of 3rd order intermodulation product. According
Output level
IMFDR 3, B < IMFDR 3, A IMFDR 3, B Input level B > Input level A
IMFDR 3, A
Noise floor
A B Input level
Figure 4.4: The relation between IMFDR3 vs SNR.
108 to the Figure 4.4, IMFDR3 is decreased as input power level is increased. This means that the signal to noise ratio is increased as input signal is increased but linearity is decreased. In contrast, as IMFDR3 is increased, input signal level is decreased which
means that signal to noise ratio is decreased. Therefore, the optimum signal level must
be checked to satisfy both linearity and signal to noise ratio requirement. Figure 4.5
shows three possible combinations of filter and VGA. For the fair comparison, each
filter and VGA blocks are assumed to have the same linearity and noise characteristics.
In the first case of VGA/filter combination, the VGA section is followed by filters. In
Filter ( a) VGA
( b) VGA Filter
VGA Filter VGA Filter ( c)
Figure 4.5: Three possible combinations of filter and VGA
this case, the linearity is not highly affected since the filter handles minimum signal level. However, noise figure is sacrificed because all VGAs are located in the latter part of the combination [33]. Also the VGA must be very linear not to generate any significant in-band or out-of-band interferers. In the second case, the filters are followed by VGAs. The total noise figure is lower than the first case since all VGAs are placed at the beginning of the chain. In this specific case, the filters should
109 handle maximum signal levels and interferers amplified through VGA stages. Since any filtering is not done prior to the VGA stages, all amplified out-of-band interferers by VGA stages must be filtered in the latter stages without sacrificing the in-band linearity.
In the third case, VGA and filters are combined in interleaving way. So the
first VGA amplifies the signal to a certain amounts, and then the filter in the next stage attenuates the part of out-of-band interferers. The amplification and filtering procedures are repeated through the combined filter/VGA structure. Since each filter and VGA stage only need to attenuate and amplify by a small amount, the filter and
VGA are not forced to handle large signals and nonlinear products at the same time.
Both noise figure and linearity are not greatly sacrificed because the amplification and the attenuation are performed with same intervals. This structure compromises the linearity and noise figure requirement well so that this structure is chosen for the design of wide band filter and VGA.
With the third architecture of VGA-filter combination, SNR and IMFDR3 re-
quirements are simulated with systemview. To check the realizable input signal level,
IMFDR3 vs input signal level is plotted. the next figure is only simulated result
when input referred noises of the filter VGA chain is assumed as reasonable values.
Figure 4.6 shows the change of IMFDR3 values according to the change of input
signal. As shown in Figure 4.6, the IMFDR3 is decreased as the input signal level is
increased. When the total input referred noise density is assumed as 19.6 nV/√HZ which is not easy to obtain at the low IF, the possible input signal is about 39 mVrms
to obtain 55 dBc IMFDR3 when maximum gain is applied. This input voltage cor-
responds to SNR of 56 dB. From the plot, if the IMFDR3 requirement is decreased,
110 the input signal level and SNR value are increased if the noise level is not changed.
Therefore, when the input signal level which satisfies the required SNR is known, the correspond IMFDR3 requirement can be known. Then the design can be optimized to meet both SNR and IMFDR3 requirements together.
IM3 (dBm)
IM3 (10nV) IM3 (16.97nV)
IM3 (19.6nV)
IM3 (23.7nV)
Figure 4.6: IMFDR3 vs. Input voltage (rms)
4.2.2 Trade off between Power consumption and dynamic range
Since multistage filters and VGAs should be used, latter stages must have higher dynamic range since they need to handle larger signals [11]. The dynamic range is usually increased when DC power consumption is increased [15]. It is not clear, however, that only power will optimize the dynamic range requirement. So it is necessary to investigate the relation between power consumption and dynamic range.
111 To realize the band pass filter and VGA together, several filter and VGA blocks must be cascaded. When many stages are cascaded together, the 3rd order intercept point of the cascaded filter and VGA can be expressed by the well-known equation,
1 G G G 1 G G G G G G 1 = 1 2 ··· N = + 1 + 1 2 + + 1 2 N − (4.3) IIP OIP IIP 1 IIP2 IIP3 ··· IIPN where Gn is the gain of nth stage and IIPn is IIP of nth stage. According to the
equation 4.3, the IIP of the second and succeeding stages are reduced by the gain of
the preceding stages [15], [22]. However, the IIP3 point is increased as more dc power
is consumed. The IIP of i th stage can be expressed as
OIPi Pdci IIPi = = Bi (4.4) Gi · Gi where Bi is the output linearity efficiency and Pdci is the power consumption of the
i th stage. If the dynamic range is defined as the difference between signal level and
the level where intermodulation products first appear from noise, the dynamic range
of N stages is IIP 2 DR = n (4.5) Pn · 3 where IIPn is the input intercept point of N stages and Pn is the noise floor of the N
stages, respectively. Pn is expressed as [15]
P = kB(NF 1)T (4.6) n − 0 where k is the Boltzmann constant, B bandwidth of system, NF noise figure of the
system, and T0 is the reference temperature (290K). Using the equation 4.1 and
previously derived equations, the DR is given by 2 3/2 Pdc (OIP/Pdc) √G 1 d = N − kBTG G √G−N 1! − 1 G−1 − (4.7) × (NF 1)(1 G−N )+(1 G−1) − − − 112 where G is gain, NF is noise figure.
If the GN = G which is total gain and gain is high, G−N 0.Then the dynamic t ≈ range in dB scale is
2 P 2 (OIP/P )(1 √G−1)2(1 G−1) D 10log dc + 10log dc − − (4.8) ' 3 kT BG 3 NF G−1 0 t − ! The first factor in the equation 4.8 depends only on system parameters such as bandwidth, total gain, and dc power consumption. The second part contains factors specific to the device such as gain, noise figure, and linearity. According to the equation 4.8, the dynamic range decreases as signal bandwidth incrases if total power consumption is fixed. The increase of noise figure also decreases the dynamic range.
To increase dynamic range, either power consumption must increase or NF must decrease. Decreasing NF is much more difficult. So increase of power consumption will be an easier choice to obtain wide dynamic range. But, the dynamic range will be saturated in some point since the signal swing range is limited by supply voltage. Increase of power corresponds to increase of current in a fixed supply voltage.
Increasing bias current will cause more noise. This will decrease dyanmic range.
As mentioned in 4.2, IMFDR3, is often mentioned as dynamic range, but when
the IMFDR3 requirement is satisfied, the SNR requirement may not be met because
of the following relation. A 3 a A IM3 = | 3 | in2 (4.9) A 4 a ω1,ω2 | 1 | where AIM3 is the amplitude of the 3rd order intermodulation, Aω1,ω2 is the amplitude
of the output components at two fundamental frequencies and Ain2 is the input level
at each frequency. According to the equation 4.9, the 3rd order intermodulation
113 products are getting smaller as input signal levels are smaller. Small input signal levels that meet IMFDR3 requirement may not satisfy the SNR. Therefore, IMFDR3
requirement should be checked with SNR at the same time. To obtain the possible
maximum dynamic range and SNR, the trade off between allowable noise floor and
linearity must be known. For more detailed analysis, we can derive the relation
between IMFDR3 and IIP3 from following equations. The input intercept point of
a system is expressed as DR IIP = Sbb + (4.10) 3 2 where IIP3 is input IP3 point, Sbb is input signal power. Then the input signal power can be expressed as
Sbb = SNR +( 174 + 10log(BW )+ NF ) (4.11) min −
Where SNRmin is minimum signal to noise ratio and BW is the bandwidth of the noise to be integrated and NF is the noise figure of the system. If the equation 4.11 is applied to the equation 4.10, then IMFDR3 can be expressed as [33]
DR =2IIP 2SNR 2( 174 + 10log(BW )+ NF ) (4.12) 3 − min − −
From the equation , the requirement of IMFDR3 can be obtained. In the case of universal base station, SNRmin needs to be around 60 dB when noise is integrated
from 12.5MHz to 17.5 MHz. With the 60 dB of SNRmin, the IMFDR3 is
IMFDR =2IIP + 74 2NF (4.13) 3 3 −
To obtain the desired value of IMFDR3, the linearity requirement must be increased
as the noise figure increases. For example, when noise figure of the system is 20 dB,
the IIP3 must be 8 dBm to achieve 53 dBc of IMFDR3. If the IIP3 is lower than 8
114 dBm, the noise figure must be lower than 20 dB. Figure 4.7 shows the changes of NF and IMFDR3 according to the different IIP3 values.
90
80
70
60 IIP3 = 10 dBm
IIP3 = 5 dBm 50
40 IIP3 = 0 dBm IMFDR3
30 IIP3 = −5 dBm
20
10
0
−10 0 5 10 15 20 25 30 NF
Figure 4.7: The change of IMFDR3 and NF according to different IIP3
As shown in the equation 4.8, dynamic range is increased as power consumption
increases. Since the base staion is not battery-operated, power consumption is not a
major design factor. So the simplest and efficient way of increasing dynamic range
is increasing the power consumption. However, the range of possible dynamic range
with a certain number of IIP3 and noise figure should be investigated first to obtain
feasible design factors.
According to the Figure 4.7, if NF is 20 dB and IIP3 = 10 dBm, a possible
IMFDR3 value is around 45 dBc. If we want to achieve at least 55 dBc, the IIP3
must be increased to around 30 dBm. If the IIP3 value can not reach the 30 dBm,
noise figure must be decreased. If the noise figure is higher than 25 or 30 dB, the IIP3
must be higher than 40 dBm. Therefore, the VGA and filter should maintain a low
115 noise figure to meet the dynamic range requirement. With IIP3 of 10 dBm, it is almost impossible to meet the dynamic range requirement unless the noise figure is decreased to an unreasonable value. Therefore, IIP3 of the VGA and filter combination should be around 30 dBm and NF should be kept at a minimum value.
4.3 Design of Filter and VGA
Based on the previous discussions and design considerations, the VGA-filter com- bination is presented as shown in the Figure 4.8. The presented VGA-filter combina- tion shows following characteristics:
1. Signal amplification is executed with filters and simply designed attenuators are
applied to carry out the attenuation in the required step.
2. Identical amplifiers are re-used for both filter and attenuators.
3. The VGA-filter combination is designed in an interleaving manner to satisfy
both high linearity and a low noise figure.
4. Input bias currents of amplifiers are maximized to achieve both high linearity
and low noise.
5. Tuning of the filter and variable gain setting of the VGA are digitally controlled.
As shown in the Figure 4.8, seven filters and five attenuators are cascaded in an interleaving way to satisfy both linearity and noise requirement. The active compo- nents used for filters and VGA are 6 dB and 0 dB gain linear fully differential buffers.
Both buffers are identical except that the input signals are applied to different nodes.
According to the input nodes, 6 dB gain or 0 dB gain is obtained. Bias currents of
116 H1 L2 H2 L2 H2 L2 L2 Vin+ Vout+
Vin - Vout -
6dB step 3dB step 6dB step 6dB step 1dB step (0 ~ -12) dB (0 ~ -9) dB (0 ~ -12) dB (0 ~ -12) dB (0 ~ -3) dB
L2: 2nd order low pass filter H2: 2nd order high pass filter H1: 1st order high pass filter
Figure 4.8: Filter and VGA for basestation
input differential pair are highly increased to obtain large transconductance value.
Since the linearity of the amplifier is affected by variation of input transconductance, large input bias current minimizes the relative variation of input transconductance.
The large bias current increase linearity and decrease input referred noise. These fully differential buffer circuits do not require any common mode feedback, so the design is simpler than ordinary fully differential circuits [12]. The fully differential buffer will be explained in the next section. For band pass filter realization, the Sallen-key
filters are used. The Sallen-key filters are well-suited to achieve the design goal of the VGA-filter combination because they require a minimum number of active com- ponents for the same attenuation [50]. Second order attenuation is obtained with an amplifier. Further the Sallen-key filter utilizes the 6 dB gain buffer as the active com- ponent so the amplification is easily executed with the cascade of the filters. Since
117 gain is already obtained with filters, only simple resistor divider based attenuators are necessary for the function of VGA. Five digitally controllable attenuators are used to acquire the 1dB step of gain variation. Since the identical components are reused in both filter and attenuator stages, the overall design time is greatly saved. Also the fully differential buffers are useful for the cascade of several stages since they show the low output impedance characteristics. For the interface with digital control signals, each filter and attenuator apply the bank of digitally controllable switches. In the case of the filter, binary weighted capacitors with switches are connected in parallel.
Also resistors in each attenuator are combined with digitally controllable switches so that the variable gain settings are controlled by digital signal.
In the design of wide band pass filter and VGA, static DC offset problem is not a big concern. Since desired signals are located in low IF and three high pass filters that have a cut-off frequency around 10 MHz are placed between attenuators, static
DC offset will be filtered after passing through these high pass filters. All pass filter is not shown in the Figure 4.8, but 2nd order all pass filter was cascaded at the end of the VGA-filter combination to reduce the group delay.
4.3.1 Fully differential buffer without common mode feed- back
For the active components of the filters and attenuators, the fully differential buffer circuit, which was presented in the section 3.2, is used. Figure 4.9 shows the schematic of the fully differential buffer. This buffer is almost identical to the buffer discussed in the section 3.2 except for the cascode transistors, M18 and M19. The
cascoded trasnsistors are used to increase the linearity of the buffer. The cascode
118 transistors decrease the variations of the impedance so that the linearity is improved.
M13 M14
M15 M18 M19
Vbias M17 Ib M16
Vo - Vo + V1 V2 M6 M5 M1 M2 M3 M4
Ib Vb1 Vb2
M10 M9 M7 M8 M11 M12
Figure 4.9: Fully Differential Buffer
Large input transconductance are required to achive both high linearity and low input referred noise. By increasing the bias curret of input differential pair, the variation of input transconductance value is decreased and high linearity is achieved.
Low input referred noise is also obtained with large input transconductance.
As explained before, the input signal voltages are applied to the differential pair transistors M1 and M2. The drain currents of M1 and M2 are the same as the drain
current of M5 and M3 respectively. Since M1 - M6 are all matched and the transistor
M7, M8 and M9 sink the same tail currents, the drain current of M6 and M4 are equal
to the drain current of M1 and M2. Therefore, the bias current Ib can be expressed
119 by [11], [10]
IM1 + IM2 = Ia IM1 + IM5 = Ia (4.14)
Since the dimensionally matched differential pair carries equal differential and com-
mon mode currents, the output voltages can be expressed by
V = V (V V ) and V = V +(V V ) (4.15) o+ b1 − 1 − 2 o− b2 1 − 2
where Vb1 and V b2 are bias voltages of the circuit [7]. The differential output voltage
is then calculated by [10]
V = V V =2 (V V )+(V V ) (4.16) o o+ − o− · 2 − 1 b1 − b2
If the bias voltage Vb1 and Vb2 are equal, the differential input is amplified by 2 times.
For the 0 dB gain buffer, the differential inputs are applied to Vb1 and Vb2 and the
bias voltage is applied to V1 and V2. Then the output Vo+ and Vo− are [10]
V = V (V V ) and V = V (V V ) (4.17) o+ 1 − b1 − b2 o− 2 − b1 − b2
And the differential output voltage Vo is
V = V V = V V (V V )+(V V )= V V (4.18) o o+ − o− 1 − 2 − b1 − b2 b1 − b2 1 − 2
which is equal to the differential input voltage. Therefore, the 6 dB gain and 0 dB
gain buffer circuits are realized with identical buffer circuit by simple exchange of
input signals and bias voltages.
4.3.2 Design of the band pass filter
For realization of IF band pass filter, four 2nd order low pass filters and three
high pass filters are cascaded to give 8th order attenuation at the low pass filter
120 end of the response (high frequency end) and 5th order attenuation at the high pass
filter end of the response (low frequency end). Sallen-key filter configurations are used to implement the wide band pass filter. Although Gm-C filters are the most popular continuous time filters, the lack of very linear and efficient voltage-to current transducers prevent Gm-C filters using in the highly linear and wide dynamic range
filter application [48]. The ordinary active filters also cannot be used for the IF applications since the bandwidth of the operational amplifier is too narrow to apply the filter at IF region even though the amplifier demonstrates the characteristic.
However Sallen-key filters provide linear and wide band filters if the filters require low values of Q. Since the wide band pass filter does not require high value of Q, the
Sallen-key filter configuration is a suitable choice. Sallen-key filters are also easy to design. Only one amplifier is used to realize a 2nd order filter. Therefore, Sallen-key
filter uses a minimum number of amplifiers to yield the required attenuation. The cascade of each block is easier with the Sallen-Key structure because it adopts a buffer as an active component. However, the Sallen-key filters are sensitive to process and temperature variation and high frequency parasitic capacitance [28], [41]. Therefore, tuning terminal for accurate frequency characteristic is required. Since Poly-silicon resistors and Poly-Poly capacitors are used to achieve high linearity and low-signal distortion, the tuning terminals must be able to control the process variation of 30 -
50 %. Figure 4.10 shows a Sallen-key filter with capacitor stack for frequency tuning.
Figure 4.10 (a) is the 2nd order low pass filter and Figure 4.10 (b) is the 2nd order high pass filter. In the case of the 2nd order low pass filter, the frequency response and Q can be expressed as 1 ω = (4.19) 0 R R C C r 1 2 t 2
121 C t R
R1 R2 C C Vin+ Vin + Vout + Vout+ C2 + + + + FB FB Cn (6 dB) Ct1 Ctn (6 dB ) C2 _ _ _ Vout - _ Vout - Vin - Vin - R1 R2 C C
Ct R (a) (b)
Figure 4.10: Sallen-Key filter with capacitor stack
−1 R C R C R C Q = 2 2 + 1 2 1 t (4.20) R1Ct R2Ct − R2C2 hr r r i If the same value of R is used for R1 and R2, the frequency response and Q are now
1 ω0 = (4.21) R√CtC2
−1 C C C Q = 2 + 2 t (4.22) Ct Ct − C2 hr r r i Equation 4.21 and 4.22 show that the frequency response of the Sallen-key filter depends on the resistor and the capacitor. Either component can be tuned to correct the associated time constant, but tuning the capacitor is preferred [39]. The reason for this can be understood if we first recognize that either series resistors or parallel capacitors are more efficient area. Parallel capacitors are preferred to series resistors because the effect of the switch on-resistance has no direct impact on the frequency
122 response but there is a second order effect, namely parastic zero [9]. Unlike Gm-
C filters, current biasing tuning scheme is not available with the Sallen-key filter.
Also, the use of capacitor stacks are usually better to maintain the linearity than the current biasing scheme. Thus four bit binary weighted capacitor stacks are used for the frequency tuning. The size of MOS switch in the capacitor stack is also carefully chosen to minimize parasitic capacitance and signal distortion.
4.3.3 Digitally programmable attenuators
The attenuators use resistive chains to control the gain in 1dB steps. For the
1 dB gain variation, five different attenuators are used to vary the loss in steps of
1dB/3dB/6dB. Three 6 dB step, a 3 dB step and a 1 dB step attenuators can give the required gain variation. The gain setting for the entire VGA/Filter chain is controlled by digitally programming the loss in the attenuator blocks. Figure 4.11 shows the schematic of an attenuator capable of providing programmable gain from 0 to -12 dB in steps of 6 dB and 0 to -3 dB in steps of 1 dB. Figure 4.11 (a) is 6 dB step attenuator and Figure 4.11 (b) is 1 dB step attenuator. The resistive chains are incorporated into the circuit design as a programmable resistive circuit element to allow the control of resistance digitally. The digital control word is applied through
MOS switches and the resistors are implemented by poly layers in a CMOS process.
Poly resistors used in the attenuators are designed carefully because the attenuation is determined by ratios of resistor values. Larger size of resistors also produces more noise [13]. The minimum size which does not damage matching between resistors were used. To yield attenuation in the case of 6 dB step attenuator, each switch is turned on and off according to the digital control word. For 0 dB attenuation, switch
123 R1 R2 R3 R1 R2 R3 R4 Vin+ Vin+
1 2 3 1 2 3 4 Vout+ Vout+ + + + + FB FB 0 dB (0dB) _ _ _ _ Vout - Vout -
Vin - Vin - R1 R 2 R 3 R4 R1 R2 R3
(b) (a)
Figure 4.11: 6 dB step and 1 dB step attenuators
1 is closed and the two other switches are opened. Then the input signal is directly connected to the input of buffer. If switch 2 is closed and other switches are opened, the attenuation is given by
R + R 250Ω + 250Ω 1 = 2 3 = = = 6dB (4.23) R1 + R2 + R3 500Ω + 250Ω + 250Ω 2 −
If switch 3 is closed and switch 1 and 2 are opened, the attenuation is given by
R 250Ω 1 = 3 = = = 12dB (4.24) R1 + R2 + R3 500Ω + 250Ω + 250Ω 4 −
The operation mechanism of 3 dB and 1 dB attenuators are the same as the 6 dB attenuator.
124 4.4 Test Results
The VGA and filter combination was designed in 0.5 µm technology. This design was fabricated in the AMI 0.5µm technology and measured. For bandpass filter re- alization, four 2nd order low pass filters and three high pass filters were designed.
Since each filter already produces a gain of 6 dB, the VGA section simply attenuates the signal for the gain variation. Total power consumption of the VGA-Filter combi- nation is 250mW. Each fully differential buffer consumes 3mA of the current. Figure
4.12 shows the simulated result of the fully differential buffer. (a) is the schematic and post layout frequency response and (b) is the dc transfer curve. As shown in
Figure 4.12, the post layout simulation result is almost identical to the schematic result.
Post layout simulation result
(a) (b)
Figure 4.12: Frequency response of the Fully differential buffer
125 Figure 4.13 shows the simulated frequency response of the filter. As shown in
40
20
0
−20 Gain [dB] −40
−60
−80
−100 6 7 10 10 Frequency [Hz]
Figure 4.13: Frequency response of the VGA-Filter combination when the gain is maximum
the simulation result, the low frequency end of the filter is around 10 MHz and high frequency end of the filter is 20 MHz. The attenuations for the low frequency end and the high frequency end are larger than 25 dB at the 5 MHz span and 20 MHz span from the each cut-off frequency respectively. To minimize the passband ripple, the butterworth filter was employed. Therefore, the ripple must be small. However, the bandpass filter was designed by the combined structure of the low pass filters and high pass filters, the ripple could be larger than the expected value. In the simulation level, the passband ripple was around 0.9 dB in the worst case. Figure 4.14 shows the magnified view of the passband region to check the ripple.
126 Figure 4.14: The passband ripple
Analog filter is sensitive to process and temperature variation. Usually the vari- ation of the poly resistor and capacitor are 25% and 10%. So the tuning circuit ± ± should be able to restore the shifted frequency response to original location. Figure
4.15 shows the frequency response of the filter when tuning capacitor array is acti- vated. As shown in the figure, the frequency response is shifited according to the switching of the capacitor array without significant distortion.
Although the group delay of the butterworth filter in the passband is small, the group delay is increased as several blocks are cascaded. In the passband region, group delay difference should be minimized to avoid inter symbol interference. Therefore, the allpass filter is often implemented to decrease the group delay difference. Figure
4.16 shows the group delay of the VGA-Filter combination.
According to the Figure 4.16, the group delay in the pass band is approximately
100ns. The delay is highest around 10MHz because the 2nd order high pass filter
127 40
20
0
−20
−40 Gain [dB]
−60
−80
−100
−120 6 7 8 10 10 10 Frequency [Hz]
Figure 4.15: The simulated plot of the frequency shift when the capacitor array is switched
has a high Q value around 10 MHz. To decrease the group delay difference in the pass band, 2nd order all pass filter was applied. All pass filter also increases total group delay but it minimizes the delay difference. Figure 4.17 shows the group delay difference after the 2nd order all pass filter is cascaded at the output of the VGA-Filter combination. Because of the resolution problem at the output data of the cadence, the plot was not drawn smoothly. But this plot shows that the group delay difference is decreased.
Figure 4.18 shows the 1 dB step gain variation of the VGA-Filter combination.
The maximum gain error was observed at the lowest gain setting. Regardless of the gain variation, the cut-off frequency of the filter is almost constant. Figure 4.19 shows the simulated result of two tone test of the VGA-Filter combination. The
128 −7 x 10 2
1.8
1.6
1.4
Group delay 1.2
1
0.8
0.6 0 0.5 1 1.5 2 2.5 3 7 Frequency (linear scale) x 10
Figure 4.16: The group delay of the VGA-Filter
simulation was performed when 10MHz and 15MHz input signals were applied. As shown in Figure 4.19, the 3rd order intermodulation products are placed on 5MHz and 20MHz. IMFDR3 is approxmately 56 dBc at the maximum gain mode. Figure
4.20 shows the output noise of the VGA-Filter combination. Around the 10 MHz, the output noise is maximum, around 780nV/√Hz. The output noise has similar shape to the filter response since the output noise is filtered out at the out of pass band region.
As mentioned before, the VGA-Filter design was fabricated and measured. Filter and VGA blocks are fabricated separately. Figure 4.21 and 4.22 shows the chip photograph of the filter and VGA respectively. The area of 3000 µm 1500µm was × used for the band pass filter and 1500 µm 1500µm was used for the VGA. ×
129 −7 x 10 2.2
2
1.8
1.6
1.4 Group delay
1.2
1
0.8
0.6 0 0.5 1 1.5 2 2.5 3 7 Frequency (linear scale) x 10
Figure 4.17: The group delay of the VGA-Filter when 2nd order all pass filter is cascaded
Figure 4.23 shows the measured frequency response of the filter. One plot is the originally measured data and the other one is the response when the capacitor array is switched. Even though the output response is shifted a little bit, the cut-off frequency is still located on the lower frequency than simulated result. This frequency shift is due to process variation and higher output capacitance load due to input capacitances of external buffers. Two external buffers were used to drive the huge capacitance load of the cable and spectrum analyzer. But the input capacitances of the external buffers and wire connection between output of the filter and input of the external buffer increased the output load of the filter than expected value. Figure 4.24 shows the measured frequency response of the attenuators. As shown in the figure, the gain is varied by 1 dB step. Since the gain variation is performed by the ratio of the resistors,
130 Figure 4.18: The gain variation of the VGA-Filter
the gain was not greatly affected by the process variation. Because of the noise during the measurement, there are small ripples around the cut-off frequency region. For the linearity test, the two tone test was performed. Figure 4.25 shows the intermodulation product of the VGA. As shown in the Figure, in-band intermodulation product was measured. When two tone signals at 1.8 MHz and 2 MHz are applied, third order intermodulation products were produced at 1.6 and 2.2 MHz. The difference between fundamental signals and third order intermodulation products are about 55 dBc when two -10 dBV of input signals are applied.
131 0
−10
−20
−30
−40
−50
−60
−70
1.6 1.7 1.8 1.9 2 2.1 2.2 7 x 10
Figure 4.19: The simulation result of two tone test of the VGA-Filter combination
Figure 4.20: The simulated output noise of the VGA-Filter
132 Figure 4.21: The Chip Microphotograph of the Filter
Figure 4.22: The Chip Microphotograph of the VGA
133 0
−5
Original −10
Tuned frequency response −15 dB
−20
−25
−30
−35 7 10
Frequency [Hz]
Figure 4.23: The measured output response of the filter
14
12
10
8
6 Gain [dB]
4
2
0
−2 3 4 5 6 7 10 10 10 10 10 Frequency [Hz]
Figure 4.24: The measured output response of the VGA
134 −10
−20
−30
−40 dB
−50
−60
−70
−80 1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 6 Frequency [Hz] x 10
Figure 4.25: The measured result of the VGA two tone test
Parameter Test results Technology 0.5 µm Area (Filter) 3000 µm 1500 µm × Area (VGA) 1500 µm 1500 µm × Supply Voltage 3.3 V Current Consumption (Filter) 42 mA Current Consumption (VGA) 33 mA Stop band attenuation 24 dB (@ 5MHz and 40MHz) Gain step 1 dB Gain range 36 dB Gain error +/-0.5 dB Pass band ripple 0.9 dB Group delay 50 ns IIP3 (in band, Filter) 15 dBV IIP3 (in band, VGA) 14 dBV Input referred noise density 21 nV/√Hz (simulated)
Table 4.1: Test results of the filter and VGA for base station receiver
135 CHAPTER 5
FILTER AND VGA BASED ON A LOW VOLTAGE TRANSRESISTANCE AMPLIFIER
As low power consumption is required in mobile handsets, low supply voltage is desired to reduce power consumption. To achieve low supply voltage, low threshold voltage CMOS technology is often used. Low threshold voltage (0.4 V of threshold voltage in the case of 0.18 µ process) leads to a reduction in device overdrive voltage, and this results in low supply voltage. However, the threshold voltage has not scaled down proportionally according to the reduction of supply voltage. For example, typ- ical NMOS device threshold voltages have gone down from approximately 1V for 2µ
CMOS technologies to around 0.4V for 0.18µ processes, whereas supply voltages have gone down from 5 V to 1.8 V. This dissimilar scaling of supply and threshold volt- ages has led to a reduction in the device overdrive voltage, adversely affecting circuit performance in terms of linearity and dynamic range. Thus new circuit topologies are required to circumvent the problem of low dynamic range and linearity and to exhibit robust operation at reduced supply voltages.
This chapter discusses the transresistance amplifier based filter and VGA. This low voltage transresistance amplifier (LVTA) is capable of operation at a supply voltage as low as 1.5V in a 5V CMOS technology [53]. Since the amplifier employs current
136 feedback to reduce stacking of devices between the supply rails and to lower voltage signal swings, the feedback does not require high impedance output node and allows for low voltage operation. The LVTA is applied to implementation of filter and VGA to test the performance. Since the LVTA based filter receives current signal as input, the cascade with mixer is easier. The output impedance of mixer is usually high in voltage mode so that a buffer circuit is often required for impedance matching.
However, in current mode, output current of mixer can be directly applied to the
LVTA based filter since the impedance matching is not required. The LVTA based
filter and VGA are not designed for targeting particular application. To demonstrate the performance of LVTA in low supply voltage, the amplifier is used to implement
filter and VGA. For more detailed analysis and explanation of LVTA, please refer to
[53].
5.1 Low Voltage Transresistance Amplifier
For reliability reasons, the scaling of device dimensions requires a lowering of the maximum operating voltages. Therefore, supply voltages have gone down from 5V for 2µ CMOS technologies to 1.8V in today’s processes. A further reduction to 1V and lower is anticipated in the coming decade [8], [42]. The reduction in device dimensions and supply voltages has immensely benefited digital circuitry in terms of higher speed and lower power consumption without having to change fundamental the circuit topology. Unfortunately, the same has not been true for analog circuits.
While MOS transistors in digital circuits operate as switches, in analog circuits they are typically biased to operate in strong inversion region where a part of the supply
137 voltage is used in biasing the device. Therefore, new circuit topology is often required to operate in low supply voltage in case of analog circuits.
As mentioned before, reduction in supply voltage leads to reduced device overdrive voltage and reduced dynamic range in analog circuits. Therefore, popular high voltage gain circuit topologies like cascode amplifiers are harder to implement at low supply voltages. One solution to this problem is the use of low threshold voltage (VTH )
devices. However, reducing the threshold voltage is detrimental to the digital part of
mixed signal circuit as it leads to a greater leakage current [51]. A compromise is to
replace selected transistors with low-VTH devices. However, this requires additional
steps in fabrication with an accompanying increase in cost.
Figure 5.1 shows the input stage of an NMOS differential pair amplifier widely used
in constructing Operational Amplifiers (Opamps) and Operational Transconductance
Amplifiers (OTAs). The input DC voltage is maintained at mid rail in order to
V DD /2 V / DD 2
V GS
V bias V overdrive
Figure 5.1: The input stage of an NMOS differential pair amplifier
138 maximize the swing range of the amplifier. Analysis shows that
VDD Vin,DC = 2 = VGS,inputpair + Voverdrive,bias
V =4V 2V (5.1) DD GS − TH,n
where VTH,n is the NMOS threshold voltage. In a 0.5 µ CMOS technology with a
VTH,n of 0.7V, this translates to minimum required supply of around 2.2V.
In order to overcome the supply voltage, the requirement of the input DC level
to be at midrail must be decoupled from the requirement for this voltage to be high
enough to bias the input differential pair. This can be achieved by applying the input
as a current, instead of a voltage, using a transresistance amplifier. Current domain
signal processing demonstrates the advantages of reduced voltage swings and a high
bandwidth due to the presence of low impedance nodes in current mode circuits [47].
The conversion of voltage to current and the use of a transresistance stage implies
that the signal amplification is done in the current domain. As shown in Figure 5.2,
use of a transresistance stage implies that in a closed loop feedback configuration,
the sensed signal at the output is a voltage and the feedback signal is a current. The
shunt-shunt feedback places the amplifier and the feedback network in parallel. Such
a configuration avoids stacking of devices, making it inherently more amenable to low
voltage operation [14].
The transresistance amplifier has a current input and therefore requires a low
impedance input stage. The sub-circuit enclosed by the dashed lines in Figure 5.3
achieves this.
The circuit is a two-stage amplifier connected in a unity gain feedback configura-
tion. As shown in the next, feedback provides a low impedance node for the input
current. The voltage VCM sets the DC bias voltage for the differential pair. The use of
139 LVTA
I V V out
I in I
I V
I feedback Feedback Stage
Figure 5.2: The conversion of voltage to current
V BIAS
V out I bias
I in V CM
Figure 5.3: The closed amplifier configuration
a current input means that the relation between DC level at the input and the supply voltage which shown in equation 5.1 is not present. Consequently, the bias voltage can be set at any convenient voltage level. In order to convert the input current to a voltage, a method similar to [14] is used. As seen in Figure 5.3, a PMOS input common-source stage senses the variation of the bias current in the input stage by a current mirror action. The output impedance of the circuit is then used to convert
140 this current variation into a voltage signal thus realizing the LVTA. In order to boost the gain of the amplifier, a second NMOS input common-source stage is employed.
In order to place the amplifier in a feedback configuration, a voltage to current converter is required, a resistor as a feedback element is used as shown in Figure 5.4.
In the case of the circuit shown in Figure 5.3, a positive input current (positive current defined as flowing into a node), results in an increasing voltage at the output, which makes the feedback positive. Therefore, the feedback needs to be made negative by either using a third common source amplifier stage or by using a current buffer at the input to invert the direction of the input current.
LVTA
I V V out
I in I
R F I feedback
Figure 5.4: The closed amplifier configuration
The latter approach constitutes a current mode block and does not exhibit a similar bandwidth limitation owing to the presence of low impedance nodes. In order to realize the current buffer a circuit similar to the one described above can be utilized as shown in Figure 5.5. Since no voltage gain is required, the second common-source stage is not used. The final circuit implementation of the LVTA is given in Figure
5.6. The use of current-mode signal processing and a minimum number of transistors
141 between the supply rails aids in a low voltage operation. If a voltage input is desired, a resistor can be used to convert the input voltage to an input current.
I bias
V CM I in I out
Figure 5.5: The current buffer
In the case of the circuit shown in Figure 5.6, open loop transresistance, input resistance, output resistance, and closed loop transresistance are calculated as follows.
≈ gm1gm8(ro8 ro9)(ro10 ro11) ≈ 2 ROL 2 || || gmro (5.2) ( −1 gm6) gm1(gm4||ro2||ro4)(ro6||ro7) −
2 ≈ 2 Rin = −1 (5.3) g g (g r r ) gm m1 m6 m4|| o2|| o4
R ≈ r r ≈ r (5.4) out o10|| o11 o
vo Rf RCL = − = (5.5) Rf ii 1+ ROL
Where ROL is the open loop transresistance, Rin is the input resistance, Rout is
the output resistance and RCL is the closed loop transresistance. If the open loop
142 Vbia s
M 14 M 15 M 17 M 19 M 3 M 4 M 6 M 8
Rc
Vo Cc I bias I bias M M 13 V M M 2 12 CM I in 1 V CM
M 16 M 18 M 20 M 5 M 7 M 9 M 11
Figure 5.6: The LVTA
transresistance ROL is high enough, then RCL≈Rf . The shunt-shunt feedback due
to the feedback resistor Rf causes the input and output resistance to be lowered.
Approximate expressions for the closed loop input and output resistances are given
by
(2/gm) 2Rf Rin,closed ≈ ≈ (5.6) 1+ ROL g2 r2 Rf m o
r R R ≈ o ≈ f (5.7) out,closed ROL 1+ gmro Rf To analyze the frequency response of the open loop LVTA, we identify nodes corresponding to the location of poles and zeros in the circuit and present approximate analytical expressions. As shown in Figure 5.6, a compensation capacitor CC and a
resistor RC are used between the outputs of the second and third common source
stage to improve the phase margin of the circuit.
143 Assuming on chip load capacitors, Miller multiplication of the compensation ca- pacitor implies that the dominant pole is given by [18]
1 1 ω ≈ − ≈ − (5.8) p1 (r r )C g (r r ) g C r2 o8|| o9 c m11 o10|| o11 m c o The second pole is associated with the output node and is approximately given by
gm11 gm ωp2 ≈ − ≈ − (5.9) (CL + Cgs11) CL
The use of series compensation causes a zero, which can be shifted to the left half plane by choosing an appropriate value for the compensation resistor Rc. An approximate expression for this zero is given by
1 ω ≈ (5.10) z1 C (g−1 R ) c m11 − c
In a closed loop configuration, the feedback resistor RF modifies the expression for
the dominant pole given by Equation 5.8. An approximate expression for the closed
loop modified dominant pole can be derived by considering a one pole approximation
of the open loop transfer function. The modified dominant pole is given by
0 ≈ ROL ≈ 1 ωp1 − ωp1 (5.11) RF RF Cc
As seen in Equation 5.11, the location of the dominant pole is determined by the magnitude of the feedback resistor RF . A higher value of RF increases the separation
between the first and second poles, improving the phase margin of the circuit. Thus,
lowering the value of RF results in a greater unity gain frequency and lower phase
margin. Intuitively, a higher value of RF decreases the feedback current leading to
a more stable circuit. The LVTA permits stability-bandwidth tradeoff control by
adjusting the value of the feedback resistor depending on load conditions.
144 The major noise contributors to the LVTA shown in Figure 5.6 are the input stage, the PMOS common source stage and the NMOS common source stage. Referring the noise to the output of the circuit we have the following:
2 2 2 2 Vout = Vout,input + Vout,NMOSC S + Vout,PMOSCS (5.12)
Considering the thermal and 1/f transistor noise sources referred to the output, we can develop approximate expressions for the individual noise source of Equation 5.13.
For noise contribution due to the input stage we have
0 00 00 2 2 Kn 1 2 Kp 1 2 2 Vout,input = 4kT ( )(gm)+ (gmn) + (gmp) ROL (5.13) 3 COX W L f COX W L f where
0 gm = gm6 + gm7 + gm17 + gm18 + gm19 + gm20 (5.14)
2 00 2 2 2 (gmn) = gm7 + gm18 + gm20 (5.15)
2 00 2 00 2 00 2 00 (gmp) = (gm6) +(gm17) +(gm19) (5.16)
Kn and Kp are the NMOS and PMOS flicker noise parameters respectively. Similar expressions can be derived for the other noise sources due to transistors M8, M9
(NMOSCS) and M10, M11 (PMOSCS)
∼ 2 Comparing the transresistance gain of the LVTA ( gmro) to the voltage gain
∼ 2 2 of an Opamp ( gm ro), LVTA has one less gm factor compared to the Opamp.
The variation of gm with the input signal results in nonlinear behavior of the circuit.
Intuitively, the one less gm in the transresistance of the LVTA as compared to the voltage gain of an Opamp makes the LVTA inherently more linear. In the operation of the LVTA as a voltage amplifier (Figure5.10), a passive resistor converts the input voltage to an input current without degrading the linearity. Thus the LVTA exhibits higher linearity as compared to the opamp.
145 5.2 Filter and Variable Gain Amplifier
Filter and variable gain amplifiers (VGA) find wide use in a number of mixed signal applications where they attenuate undesired interferers and amplify the signal relaxing the noise requirements of the succeeding stages. Also they realize gain control providing a constant signal level to the analog-to-digital converter (ADC) in the presence of varying signal strengths. As shown in Figure 5.7, the VGA is a part of a control loop where the control signals for the VGA are obtained from a digital signal processor (DSP).
VGA Filter Input signal ADC DSP
Figure 5.7: The simplified view of the receiver
In applications such as in communication receivers, it is desirable for the signal amplification to be accompanied by a filtering operation so that the undesirable com- ponents of the signal may be reduced and the wanted signal amplified. Filtering is required for anti-aliasing and to remove unwanted signal components to reduce the dynamic range requirement of the ADC. In LVTA, a lossy integrator can be realized
146 by adding a feedback capacitor CF in parallel to the feedback resistor RF and loss-
less integrator is realized by only feedback capacitor. A Tow-Thomas biquad [46] is
implemented using a lossy integrator, a lossless integrator and an inverting amplifier
as shown in Figure 5.8. The filter transfer function is given by
Vin R1 R2 R` LVTA LVTA LVTA
C1 C2 R`
R3 R4
Figure 5.8: The Tow Thomas Filter
1 A (S) = R1R2C1C2 (5.17) v 2 s 1 −s + R3C1 + R2R4C1C2 The DC gain, the cutoff frequency and the Q of the filter are given by
R4 Av = (5.18) −R1
1 ω = (5.19) o R R C C r 2 4 1 2
C Q = R 1 (5.20) 3 R R C r 2 4 2
147 If C1 = C2 = C and R2 = R4 = R then the above expressions simplify to Av = -R/R1,
ωo = 1/RC and Q = R3/R. The resistors in the biquad R3 and R convert a voltage to
a current. These can be implemented as R-2R ladders, enabling independent digital
tuning of cutoff frequency and Q of the filter. R-2R ladders can be used to realize
large resistor values, making possible on-chip realization of low filter frequency cutoffs
in an area efficient manner.
In order to realize a variable gain amplifier, a resistor Ri is used to convert the
input voltage to an input current. According to equation 5.5, the closed loop tran-
sresistance RCL is approximately RF . If a resistor Ri is used to convert the input
voltage to an input current for the transresistance amplifier, the closed loop voltage
gain is given by
RF Av = (5.21) − Ri
By fixing RF and varying Ri, the voltage gain of the amplifier can be varied thus realizing a variable gain amplifier (VGA). Unlike inverting Opamp configurations, the feedback is determined by the feedback resistor RF , which is seen in equation 5.11
sets the closed loop bandwidth. This implies that by fixing RF , the bandwidth of the
voltage amplifier is independent of the voltage gain realized by the circuit.
Several techniques can be used to implement a programmable Ri. In one approach,
a triode region MOS transistor is used to realize Ri. Although this technique allows
convenient tuning of the input resistance, it shows poor linearity since the resistance
realized depends on the input voltage. An alternate method is to use an array of
binary weighted polysilicon resistors in implementing Ri. While this approach enjoys
a good linearity, it suffers from a large component spread, limiting the gain values/gain
steps that can be realized in a monolithic implementation.
148 Vin/2R Vin/4R Vin/8R Vin/16R Vin/2 n-1 R I V out V CM b2 V CM b3 V CM b V CM b CM b 1 4 n 2R 2R 2R 2R 2R V in 2R R R R V CM
Figure 5.9: The R-2R ladder
R-2R ladders allow a large gain range to be realized in a compact fashion using polysilicon resistors. The use of R-2R ladders have found extensive use in compact realizations of digital to analog converters [18]. More recently, they have been used as tuning elements in digitally programmable integrated analog filters [4] where R-2R ladders are considered as digitally programmable resistors.
The n-bit R-2R ladder is shown in Figure 5.9, where the output current IOUT is
given by N b V I = i i (5.22) out 2i−1 2R i=1 X Where Vi is the input voltage, and b is the N bit digital input to the ladder. As shown in [4], the equivalent resistance between the input and output nodes is given by
Vi 1 Req = = βR where β = (5.23) I N bi i i=1 2i The R-2R ladder can thus be used to realize a digitallyP programmable resistor Ri.
With such an implementation of a variable resistor, DC transfer function of the VGA
149 Coarse tuning Fine tuning R-2R R-2R V V in LVTA out ladder ladder LVTA
d1, d2, d3,,, dn d1,d2,d3,,,d n
R F R F
Figure 5.10: The programmable gain amplifier by using R-2R ladder
is given by R N b A = F i (5.24) v − R 2i i=1 X RF 1 RF From Equation 5.24 it can be seen that the gain range extends from R 2N to 2R in
RF 1 steps of R 2N . As shown in Figure 5.9, the VGA circuit described above can be cascaded to realize coarse and fine tuning stages. The use of a direct digital input to the VGA simplifies the DSP interface in the VGA control loop.
5.3 Test Results
To test the performance of LVTA, LVTA based Tow-Thomas filter was designed and simulated. Also a monolithic realization of the LVTA and R-2R VGA was done in AMI 0.5µ CMOS technology available through MOSIS. The process offers three metal and two poly layers with a high resistance implant available for realizing large resistor values. The nominal NMOS and PMOS threshold voltages are approximately
0.7V and 1V respectively and the recommended supply voltage is 5V.
150 Figure 5.11: The microphotograph of the LVTA
The chip microphotograph of the LVTA is shown in Figure 5.11. A prototype board was fabricated to experimentally verify the performance of the LVTA and the
VGA. A supply voltage of 1.8 V was used, and the VCM value (see Figure 5.6) was set
to 1.1V. External resistors were used to realize the input and the feedback resistors.
Figure 5.12 shows the frequency response at a fixed RF = 56 kΩ and different values
of Ri from 22 kΩ to 220 kΩ. The circuit shows a measured gain range of 23 dB with
a relatively constant bandwidth of 1.6 MHz driving a load of 5pF.
To study the effects of changing RF on the stability of the LVTA, the gain was fixed
at unity and different values of RF = Ri ranging from 5.6 kΩ to 82 kΩ were chosen.
As seen in Figure 5.13, the circuit exhibits substantial peaking at lower values of RF
indicating a low phase margin. This response agrees with the stability analysis. Figure
5.14 shows the frequency response of the LVTA with different feedback capacitor CF
151 5 Ri = 22K
0
Ri = 56K −5 Ri = 82K −10 Ri = 120K
−15 Ri = 220K
−20 Gain (dB)
−25
−30
−35
−40
−45 3 4 5 6 7 10 10 10 10 10
Frequency (Hz)
Figure 5.12: The frequency response of LVTA when Ri is changed
10 Rf = Ri = 5.6K
5 Rf = Ri = 10K
0
−5
Rf = Ri = 22K −10 Rf = Ri = 56K −15 Rf = Ri = 82K Gain (dB) −20
−25
−30
−35
−40 3 4 5 6 7 10 10 10 10 10
Frequency (Hz)
Figure 5.13: The frequency response of LVTA when RF is changed
152 −5
C = 1pF C = 2pF −10 C = 3pF C = 4pF
−15 C = 8pF
−20
Gain (dB) −25
−30
−35
−40 3 4 5 6 7 10 10 10 10 10
Frequency (Hz)
Figure 5.14: The frequency response of LVTA when CF is changed
values at a fixed RF and Ri , thus verifying the utility of the LVTA in realizing a lossy integrator.
The LVTA was used to design Tow-Thomas filter shown in Figure 5.8 and cut-off frequency was varied by adjusting value of resistor in the Tow-Thomas filter. Figure
5.15 shows the simulated result of the Tow-Thomas filter.
Figure 5.16 shows the spectral response of a two tone test for RF = 56 kΩ and
Ri = 56 kΩ. The two tone frequencies chosen were 50 KHz and 52 KHz at a Vp-p
= 200mV. The third order intermodulation components at 48 KHz and 54 KHz are found to be 40dB below the fundamental. Simulations indicate the THD distortion for a 1KHz signal to be less than 0.1%.
In order to investigate the lower limit of supply voltage, measurements described above were repeated at a supply of 1.5V. The frequency response of the circuit with
153 10
0
−10
−20
−30
−40
−50
−60
−70 3 4 5 6 10 10 10 10
Figure 5.15: The frequency response of LVTA based Tow-Thomas filter
Figure 5.16: The spectral response of a two tone test
154 0
Ri = 56K −5 Ri = 82K −10 Ri = 120K
−15
−20
Gain (dB) −25
−30
−35
−40
−45 3 4 5 6 7 10 10 10 10 10
Frequency (Hz)
Figure 5.17: The frequency response of LVTA with 1.5V supply
a fixed RF = 56 k and different Ri values is shown in Figue 5.17. The bandwidth of the circuit is seen to reduce to 1.4 MHz. It must be noted that the circuit failed process and temperature corner simulations at a supply of 1.5 V while showing robust performance at the corners for a supply of 1.8 V. Figure 5.18 shows a microphotograph of the R-2R based VGA. A 5-bit implementation of the R-2R ladder (R = 7.5 kΩ,RF
= 56 Ω) with a potential gain range of 32dB was used. The measured frequency
response for a few of the 32 possible digital settings is shown in Figure 5.19. For the
digital bit combinations applied, the VGA gain was measured from -9 dB to 15 dB.
By applying digital control bits as described in [32], an exponential gain control can
be realized. Table 5.1 summarizes salient measured performance specifications of the
VGA.
155 Figure 5.18: The microphotograph of the R-2R based VGA
Figure 5.19: The Frequency response of R-2R based VGA
156 Parameter Measured Value Technology 0.5 µm Supply Voltage 1.8V 3dB bandwidth@ CL =5pF,RF = 82kΩ 1.6 MHz IM3 at Vpp =200mV -40 dBc Power dissipation 2.5mW Variable gain range -9 dB to 15 dB
Table 5.1: Measured Performance
A novel low voltage transresistance amplifier circuit was developed and experimen- tally verified in a monolithic implementation. The circuit uses shunt-shunt feedback to achieve low voltage operation. The LVTA was shown to work at supply voltages as low as 1.5V in a 5V CMOS technology. A novel implementation of a variable gain amplifier using an R-2R ladder was demonstrated. The circuit enjoys a good gain control range, capability to be directly interfaced with a DSP and a closed loop gain independent of the bandwidth. A Tow-Thomas biquad implemented using the
LVTA , shows independent gain, frequency, and Q factor control. An R-2R ladder can be used for digitally tuning the filter parameters. The LVTA can thus serve as a useful active component in building analog blocks for low voltage applications.
Future directions of research would include converting the single ended realization to a fully differential implementation. This would improve the linearity as well as the noise suppression capability of the circuit. A fully differential realization of the
Tow-Thomas filter would also eliminate the requirement of the inverting amplifier, enabling a biquad to be realized using two differential LVTAs.
157 CHAPTER 6
CONCLUSIONS
This dissertation concentrates on the design and implementation of analog base- band filter and VGA for wireless communication systems. Although the integration of analog baseband filter is feasible, there are still many obstacles for the realization of highly linear wideband analog filters. Since analog filters are sensitive to process and temperature variations, these variations could increase the non-ideal effects of analog filters. In addition the requirement of high dc gain and wide gain bandwidth amplifier becomes main factor of the increase of power consumption. Moreover, since integrated noise is increased as bandwidth increases, to maintain or increase dynamic range, the active amplifier used in the filter must produce lower noise than the am- plifier in the narrow band filter. To reduce the noise, bias current should be reduced, but this could affect the linearity of the filter. So careful design strategy is necessary to reduce the noise without damaging linearity of the filter.
In this dissertation, five filters and VGAs for different applications were intro- duced. For the background of the filter design, chapter 2 briefly introduced ad- vantages and disadvantages of active RC, MOSET-C, and OTA-C filters. Also the relationship between channel selection filters and ADC dynamic range was discussed to demonstrate proper selection of channel selection filters.
158 In chapter 3, three different filter and VGA for WLAN application were intro- duced. First, WLAN filter and VGA was designed based on feed forward compensa- tion technique. To achieve high gain and wide bandwidth, feed forward compensation technique was applied to two stage amplifier. With the compensation technique, the amplifier could achieve 63 dB gain, phase margin of 88 degree, and 220 MHz gain bandwidth with 5 pF output load. Based on the amplifier, Tow-Thomas active RC
filter and VGA were designed in 0.5 µm technology. According to the measurement result, the filter’s 3 dB corner frequency was able to cover 10 MHz and 20 MHz.
Also frequency and Q factor could be tuned independently. Since the gain and gain bandwidth of the amplifier were high enough, non ideal effects due to the limited performance of amplifier were negligible. Switched resistor based attenuator was combined with transconductor and it provided gain range of 36 dB in 3 dB steps.
Second, fully differential buffer based filter and VGA were presented. The filter and VGA were designed in 0.18 µm technology and the supply voltage was 1.8 V. The
VGA provided 36 dB gain range and the low pass filter could switch the 3 dB corner frequency from 5 MHz to 10 MHz and 20 MHZ. Since the fully differential buffer does not require common mode feedback circuitry, power consumption is decreased and negative feedback stability is not a concern. Both the filter and VGA use an identical buffer to save design and optimization time. With programmable switches, multi-standard capability was obtained.
Third, WLAN filter and VGA that used the DDA and the folded cascode amplifier as active elements were presented. The DDA was used to obtain a fully differential buffer for the implementation of the Sallen-key filter. For the fully differential buffer realization, two positive inputs of the DDA were used as input node and other two
159 negative input nodes were used for feedback connection. For the VGA, folded cascode amplifier with negative feedback was applied. Test results of the filter and VGA showed that filter’s 3 dB corner frequency was 10 MHz and it could be varied. VGA demonstrated gain range of 36 dB. Both the filter and VGA were designed in 0.5 µm technology and supply voltage was 3 V.
In chapter 4, filters and VGAs for base station receiver were designed. Since base station requires strong linearity and power compression behavior, the filter and VGA must demonstrate wide gain range and high linearity. To increase the linearity, the use of MOS transistor except for the amplifier was minimized. Also current consumption was highly increased to increase linearity. In this chapter, the relationship between power consumption and dynamic range was investigated and different types of filter and VGA combination were introduced to study advantages and disadvantages of each combination. Both filter and VGA were designed in 0.5 µm technology and supply voltage was 3.3 V. Total power consumption was 250 mW. Measurement results showed that the IMFDR3 was more than 55 dBc when the gain was set to maximum mode.
Chapter 5 introduced low voltage transresistance amplifier. The amplifier op- erates with 1.8 supply voltage in 0.5 µm technology. The optimum voltage of 0.5
µm technology is 5V. There were two main reasons how the presented amplifier was able to work with low supply voltage. Since the amplifier received input signal as current, input dc bias voltage could be much lower than the mid-rail of supply volt- age. Also, high output impedance was not required to realize shunt-shunt feedback scheme. Therefore, stacking of output devices to achieve high output impedance could be avoided. Measurement results showed that the bandwidth of transresistance
160 amplifier did not depend on the value of input resistor, so variable gain function with constant bandwidth could be achieved. Also, the amplifier worked well with 1.5 V supply. The LVTA was adopted to design a 2nd order Tow-Thomas filter and R2R ladder based VGA. Test results showed that both filter and VGA worked as expected.
In conclusion, main contributions of this dissertation are as follows:
1. Feed forward compensation technique was introduced to realize wide band active
RC filter. Even though feed forward compensation is already a known technique,
this technique has not been adopted for design of filter. Since the feed forward
compensation technique was effective to achieve high gain bandwidth and stable
phase margin, wide band active RC filter was easily realized and tunability of
the filter was excellent.
2. Highly linear band pass filter and VGA for base station receiver was presented.
For the realization of highly linear filter and VGA, trade-off between dynamic
range and power consumption was investigated and new baseband chain to
achieve both high linearity and wide dynamic range was presented.
3. Low voltage transresistance amplifier was presented and implemented for the
design of filter and VGA. The amplifier worked properly even with a 1.5 V
supply voltage in 5V CMOS technology.
For future contribution, several extensions to the work presented are possible.
The feed forward compensated amplifier can be redesigned with 0.18 µm technology to increase gain bandwidth and decrease power consumption. With increase of gain bandwidth, the feed forward compensated amplifier can be applied to many different
161 circuits such as high frequency filter or ADC, etc. In the case of low voltage transre- sistance amplifier, the application of the amplifier to different circuits such as data converter or band gap reference circuit could be investigated. Since the amplifier utilizes the current as an input signal, merged structure of filter and mixer circuit can be investigated with the amplifier.
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