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Loop Stability Compensation Technique for Continuous-Time Common-Mode Feedback Circuits

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Loop Stability Compensation Technique for Continuous-Time Common-Mode Feedback Circuits Loop Stability Compensation Technique for Continuous-Time Common-Mode Feedback Circuits Young-Kyun Cho and Bong Hyuk Park Mobile RF Research Section, Advanced Mobile Communications Research Department Electronics and Telecommunications Research Institute (ETRI) Daejeon, Korea Email: [email protected] Abstract—A loop stability compensation technique for continuous-time common-mode feedback (CMFB) circuits is presented. A Miller capacitor and nulling resistor in the compensation network provide a reliable and stable operation of the fully-differential operational amplifier without any performance degradation. The amplifier is designed in a 130 nm CMOS technology, achieves simulated performance of 57 dB open loop DC gain, 1.3-GHz unity-gain frequency and 65° phase margin. Also, the loop gain, bandwidth and phase margin of the CMFB are 51 dB, 27 MHz, and 76°, respectively. Keywords-common-mode feedback, loop stability compensation, continuous-time system, Miller compensation. Fig. 1. Loop stability compensation technique for CMFB circuit. I. INTRODUCTION common-mode signal to the opamp. In Fig. 1, two poles are The differential output amplifiers usually contain common- newly generated from the CMFB loop. A dominant pole is mode feedback (CMFB) circuitry [1, 2]. A CMFB circuit is a introduced at the opamp output and the second pole is located network sensing the common-mode voltage, comparing it with at the VCMFB node. Typically, the location of these poles are a proper reference, and feeding back the correct common-mode very close which deteriorates the loop phase margin (PM) and signal with the purpose to cancel the output common-mode makes the closed loop system unstable. In order to achieve the current component, and to fix the DC outputs to the desired separation of poles for the loop stability compensation, two level. Continuous-time CMFB techniques [3] and switched main approaches are usually used. First, an addition of a mode CMFB techniques [4] have been reported to realize the capacitive load on the opamp outputs can decrease the CMFB circuits. In these CMFB circuits, there are some issues dominant pole frequency, but may decrease the opamp to be fulfilled when designing a good CMFB circuit. First, a bandwidth. Second, a reduction of an output impedance of the unity gain-bandwidth of the common-mode loop should be DDA can increase the second pole frequency, but may worsen higher than an input signal to prevent the decrease of an the CMFB loop gain. Thus, it is difficult to compensate the operation speed. Second, a common-mode loop compensation loop stability in general methods without the performance is necessary to ensure common-mode stability. Third, a degradation of the opamp and CMFB loop. common-mode detector should have a linear characteristic. To cope with these problem, we propose a new Finally, the performance of the fully differential amplifier compensation network, which is composed of a series- needs to be maintained when the CMFB circuit is connected. connected Miller capacitor (CA) and nulling resistor (RA) In this paper, we propose a novel loop stability located between opamp output and DDA output. This compensation technique for the CMFB circuits. The proposed compensation technique is similar to the Miller compensation method is used in a feedforward-compensated operational scheme in the two-stage opamps. CA performs loop stability amplifier (FC opamp) in 130 nm CMOS technology. compensation such as a Miller capacitor, which moves the dominant pole at a lower frequency and migrates the second pole at a higher frequency. Using RA in series with CA, II. PROPOSED COMPENSATION TECHNIQUE additional zero is included in the high frequency, resulting in Figure 1 shows the block diagram of an opamp and CMFB improvement of loop PM. Moreover, this series resistor circuit with a proposed loop stability compensation technique. improves the frequency response of the opamp, thus recovering The main components of the CMFB circuit are a common- the unity gain bandwidth (UGBW) of the open loop system. mode detector (CMD), a differential-difference amplifier Note that with a simple connection of CA and RA, CMFB loop (DDA), and a compensation network (CA and RA). The CMD can achieve a high loop gain and PM without affecting the senses the common-mode voltage and DDA feeds the desired performance of the opamp. This work was supported by the IT R&D program of MSIP/IITP. [R- 20150224-000291, Development on Semi-conductor based Smart Antenna for Future Mobile Communications] -page number- ISOCC 2015 TABLE I. PERFORMANCE OF THE OPAMP AND CMFB CIRCUITS WITH RESPECT TO THE LOOP STABILITY COMPENSATION CMFB only w/ CA w/ CA & RA gain (dB) 57 57 57 UGBW (GHz) 1.3 1 1.3 OPA PM (°) 61 49 65 gain (dB) 49 49 51 BW (MHz) 167 27 27 Loop Loop CMFB PM (°) -14 70 76 TABLE II. CIRCUIT PERFORMANCES WITH PVT VARIATION Fig. 2. Feedforward-compensated opamp with CMFB circuit. Corner Condition FF TT SS 80 200 VDD (V) 1.3 1.2 1.1 ) 60 160 o Temp. (°C) 0 27 85 40 5 120 OPA gain/PM (dB/°) 57/68 57/67 57/65 0 20 80 Loop gain/PM (dB/°) 46/75 49/76 49/78 -5 OTA GainOTA (dB) 1G 1.2G 1.4G 1.6G 1.8G 2G 0 40 ( PM OPA Frequency (Hz) Total current (mA) 1.9 2.0 2.1 OPA Gain (dB) Gain OPA -20 0 80 200 CMFB only ) 60 CMFB + C 160 o 1st pole A 40 CMFB + CA/RA 120 zero 20 80 2nd pole 0 40 Loop PM ( Loop Gain (dB) Gain Loop -20 0 10k 100k 1M 10M 100M 1G 10G Frequency (Hz) Fig. 4. (a) Chip photo of the opamp and CMFB. (b) Measured FFT of DSM. Fig. 3. Simulation results of proposed scheme. III. SIMULATION RESULTS IV. CONCLUSIONS A FC opamp is designed to confirm the effectiveness of the A loop stability compensation technique has been proposed proposed scheme as shown in Fig. 2. The bias voltage of M12 for a continuous-time CMFB. With a simple connection of a is controlled by a CMFB circuit and the loop stability is capacitor and resistor, the CMFB loop can achieve a high gain adjusted by a compensation network. Figure 3 shows the and phase margin without affecting the performance of the simulation results for the schematic in Fig. 2. First, the CMFB opamp. The simulation results show that this technique is circuit is connected to the opamp without loop compensation, effective in reducing common-mode errors caused by process the dominant and second pole are placed at 4.5 MHz and 40 and environmental variations. MHz, respectively. Because the two pole are very close to each other, the CMFB loop shows negative PM, resulting unstable REFERENCES operation of the closed-loop. Second, CA is connected between [1] J. Ramirez-Angulo and A. Nargis, “CMOS Operational Amplifiers with OUT and VCMFB, the dominant and second pole are shifted to Continuous-time Capacitive Common Mode Feedback,” in Proc. IEEE 100 kHz and 100 MHz, respectively. Although CA can allow a ISCAS, 2010, pp. 1280-1283. sufficient loop PM through the pole split, the UGBW of the [2] J. Torfifard and A.K.B. A’ain, “A Power-Efficient CMOS Adaptive opamp is significantly reduced by the capacitive load. However, Biasing Operational Transconductance Amplifier,” ETRI Journal, Vol. by virtue of RA, an additional zero is located in the high 35, No. 2, pp. 226-233, 2013. frequency, resulting in an improvement of the operating speed [3] J. Zhang et. al., “A 0.6-V 82-dB 28.6-μW Continuous-Time Audio of the amplifier. Detailed simulation results are summarized in Delta-Sigma Modulator,” IEEE J. Solid-State Circuits, vol. 46, no. 10, Table I and II. Table I presents the effectiveness of the pp. 2326-2335, 2011. compensation network and Table II shows the circuit [4] P.Gray, P.J. Hurst, S.H. Lewis, R.G. Meyer, Analysis and Design of Analog Integrated Circuits,Wiley, New York, 2009, section 12.5. performance against the variation of process-voltage- [5] Y.-K. Cho and B. H. Park, “Single op-amp second-order loop filter for temperature. Designed opamp is used in the 15-MHz continuous-time delta–sigma modulators,” Electronics Letters, vol. 51, bandwidth 780 MS/s continuous-time delta-sigma modulator no. 8, pp. 619-621, 2015. (DSM) [5, 6]. Figure 4 shows the chip photograph of the [6] Y. Seo et. al., “3-Level Envelope Delta-Sigma Modulation RF Signal opamp and measured output spectrum of the DSM. The Generator for High-Efficiency Transmitters,” ETRI Journal, Vol. 36, No. modulator achieves a peak SNDR of 60.2 dB at -2 dBFS input. 6, pp. 924-930, 2014. -page number- ISOCC 2015 .
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