Chemical Vapor Deposition of Tungsten Silicide (Wsi ) for High Aspect Ratio Applications
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Thin Solid Films 443 (2003) 97–107 ( ) Chemical vapor deposition of tungsten silicide WSix for high aspect ratio applications B.Sella *,, A.Sanger¨ ,abac G.Schulze-Icking , K.Pomplun , W.Krautschneider aInfineon Technologies, Konigsbrucker¨¨ Strasse 180, 01099 Dresden, Germany bInfineon Technologies AG, Balanstrasse 73, 81541 Munich, Germany cTU Hamburg-Harburg, Techn. Electronics, Eissendorfer Strasse 38, 21071 Hamburg, Germany Received 15 January 2003; received in revised form 24 May 2003; accepted 13 June 2003 Abstract Chemical vapor deposition of tungsten silicide into high aspect ratio trenches has been investigated using a commercial 8-inch Applied Materials Centura single wafer deposition tool.For an in-depth study of both step coverage and stoichiometry, a ( ) combined chemistryytopography simulator has been developed.Dichlorosilane reduction of tungsten hexafluoride WF6 has been ( ) identified as a suitable chemistry to fill deep trenches with tungsten disilicide, while for WF64 reduction with silane SiH or ( ) disilane Si26 H fundamental drawbacks have been identified for extreme aspect ratios.In the process range under study, good agreement is observed between the simulated step coverages and those obtained from scanning electron microscope images.The simulations predict a deposition regime in which both good step coverage and a suitable stoichiometry are achieved inside deep trenches. ᮊ 2003 Elsevier B.V. All rights reserved. Keywords: Chemical vapor deposition; Deposition process; Nanostructures; Tungsten 1. Introduction decreases, while at the same time their length increases. To still maintain sufficient current into and out of With continuously decreasing groundrules in modern DRAM capacitors, low resistivity plugsyvias are indis- ULSI manufacturing, there exists a strong demand for pensable for future DRAM generations. partially replacing doped polysilicon with metals or Refractory metal silicides exhibit properties that make other low resistivity materials.Refractory metal silicides, them prime candidates for replacing doped polysilicon for instance, are widely used as part of the gate stack where low resistivity is required.Given the right stoi- in dynamic random access memory (DRAM) manufac- chiometry, they are stable up to high temperatures, show turing.Another possible application for low resistivity good adhesion and also a good dry etchability w1x. materials is in the capacitor of deep trench-DRAM or Silicides can be prepared in two different ways.Pure in vias of stacked DRAM cells.Both products suffer metal can either be deposited on silicon and transformed from the fact that the serial resistance of the inner into a silicide via thermal annealing or metal and silicon ( ) ( electrode plug, deep trench-DRAM or vias stacked- can be co-deposited, which immediately leads to a ) DRAM increases with the square of the inverse ground silicide layer.The latter process is generally preferred rule.This effect is further enhanced since the require- since it leads to lower mechanical stress and a smoother ment of a constant capacitance of 25 fF leads to deeper silicide–silicon interface w2x. trenches (or higher stacks, respectively) in future In this paper, we discuss the chemical vapor deposi- DRAMs.Thus, for shrinking the ground rule, the cross- tion (CVD) of low resistivity tungsten silicide (WSi ) section of the plugs (deep trench) or vias (stacked) x into features with large aspect ratios.While we focus *Corresponding author.Tel.: q1-971-2148-783. on deep trench plugs of trench DRAMs (as manufac- E-mail address: ben.sell@t-online.de (B.Sell ). tured by Infineon Technologies), all results presented in 0040-6090/03/$ - see front matter ᮊ 2003 Elsevier B.V. All rights reserved. doi:10.1016/S0040-6090(03)00922-2 98 B. Sell et al. / Thin Solid Films 443 (2003) 97–107 this paper also apply to vias of stacked DRAMs with condition is referred to as the ‘reaction-limited’ process only minor modifications. regime.On the other hand, at high process temperatures Key requirements for a WSix -plug are thermal stability the surface reactions can be so fast that the transport of in contact with polysilicon up to frontend processing precursors to the surface is the deposition rate-limiting temperatures (Tf1400 K), good step coverage in step.This regime is generally referred to as ‘diffusion- trenches with aspect ratios 050:1 and sufficiently uni- limited’ (or equivalently ‘transport-limited’).This latter form stoichiometry along the depth of the deep trench. regime is usually employed for deposition on planar The only thermodynamically stable phase in contact wafers, since under these conditions the process temper- ( with silicon is WSi2 .While silicon-rich WSix -films x) ature has only minor impact on the deposition rate, and 2.3) exhibit smooth film-to-substrate interface w3x, they also because the throughput is maximized.However, for are thermally unstable and segregate the excess silicon wafers with high aspect ratio structures (such as deep as silicon crystallites or increase the thickness of the trenches), rapid surface reactions lead to precursor underlying polysilicon w4x.Tungsten-rich films (x-2.0), depletion inside deep trenches and, therefore, to a poor on the other hand, are also thermally unstable and lead step coverage.A simplified way to look at surface to the consumption of the underlying polysilicon layer reactions is assuming first-order reactions only.In this during anneal steps later in the process w5x.Thus, the case the surface reaction rate can be expressed by the composition of tungsten silicide layers in frontend pro- sticking probability h for particle–surface collision.A cesses should always be larger than 2 and ideally large sticking probability (hsl) means that precursor approximately 2.3 w6x.Note that slightly less stringent molecules stick to the surface after the first collision.If, limitations apply to vias in stacked-DRAM since those on the other hand, h is very small, it takes an average are not subject to high temperature anneals. of 1yh collisions before precursor molecules stick to In this paper, we demonstrate a procedure to choose the surface.Since particles can only reach the bottom appropriate precursors and process conditions for tung- of a deep trench after many collisions with the sidewalls, sten silicide CVD into structures with extreme aspect it is evident that a good step coverage is only achieved ratios.An optimized process with both good step cov- if h is very small.This is equivalent to the extreme erage and suitable stoichiometry for frontend applica- reaction-limited process regime. tions will be proposed. In a gas the mean free path length l is given by ls This paper is organized as follows: Section 2 describes kTy(62sp), with k being the Boltzmann constant, T the the general requirements on growth kinetics to achieve gas temperature, s the collision cross-section of the good step coverage in high AR structures.Selected molecules and p the total pressure.Inside a deep trench, precursors currently available for WSix -CVD are briefly on the other hand, the mean path length between discussed in Section 3 and evaluated in terms of the collisions is approximated well by the trench diameter, proposed application.Experimental results of the inves- provided the latter is smaller than l. In this so-called tigated deposition process are presented in Section 4 ‘Knudsen regime’ the step coverage of a process has and compared to chemistryytopography simulations on been calculated analytically w8x: the feature scale in Section 5.Experimental and simu- lation results are discussed in Section 6, followed by a t 1 L 3h summary and a conclusion in Section 7. B s with fs (1) tWfW y 2 S cosh fq sinh f 2. Growth kinetics 2L Generally, CVD can be divided into four steps: gas phase reactions of precursors in the deposition chamber (A), adsorption of reactive molecules at the surface (B), surface diffusion of adsorbed species (C) and finally the surface reaction leading to bulk deposition (D). While each of these steps can be present in a CVD process, it has been shown that surface diffusion (step C) is negligible for tungsten deposition w7x.Furthermore, in the remainder of this section we concentrate on feature scale aspects, assuming that step A has already taken place. Under the above assumptions, steps BqD determine the (local) deposition rate and thus the step coverage of the process.At low temperatures, the deposition rate is Fig.1.Schematic of a layer deposited into a trench and definition of generally limited by the surface reaction rate.This the variables in Eq. (1). B. Sell et al. / Thin Solid Films 443 (2003) 97–107 99 tion has been published, let alone a production-worthy process.Mixed-phased layers are generally deposited ( ) using tungsten hexafluoride WF6 or tungsten carbonyl ( ( ))w x W CO 6 11–13 .In this paper we will only discuss WF6 since it is the most commonly used tungsten precursor in the semiconductor industry.As silicon ( ) ( ) containing precursors, silane SiH426, disilane Si H ( ) and dichlorosilane H22 SiCl , DCS are all commonly used and are, therefore, considered in the following text. For the CVD process using WF6 and silane or disilane, it has been shown that the deposition rate crucially depends on the occurrence of a radical chain reaction in the gas phase w14x.With a process tempera- ( ) ture above the so-called ‘extinction temperature’ Tex , the radical chain reaction rapidly saturates, and the concentration of reactive gas phase precursors does not Fig.2.Sticking probability h required to achieve a specific step cov- erage for a given aspect ratio as calculated using Eq. (1). depend on T.If, on the other hand, the reactor temper- ature is below Tex, the chain reaction ceases and the deposition rate drops to 0 due to lack of reactive where h is the sticking coefficient and the other quan- precursors w9x.It has been shown, however, that even tities are as explained in Fig.1.