Pulsed Power Engineering Basic Topologies

January 12-16, 2009

Craig Burkhart, PhD Power Conversion Department SLAC National Accelerator Laboratory Basic Topologies • Basic circuits • Hard tube •Line-type – Transmission line – Blumlein – Pulse forming network • Charging circuits • Controls

January 12-16, 2009 USPAS Pulsed Power Engineering C Burkhart 2 Basic Circuits: RC • Capacitor charge • Capacitor discharge • Passive integration – low-pass filter – τ << RC: integrates signal,

VOUT = (1/RC) ∫ VIN dt – τ >> RC: low pass,

VOUT = VIN • Passive differentiation – high-pass filter – τ >> RC: differentiates signal,

VOUT = (RC) dVIN /dt – τ << RC: high pass,

VOUT = VIN • Resistive charging of capacitors

January 12-16, 2009 USPAS Pulsed Power Engineering C Burkhart 3 RC Charge

January 12-16, 2009 USPAS Pulsed Power Engineering TTU-PPSC 4 RC Discharge

January 12-16, 2009 USPAS Pulsed Power Engineering TTU-PPSC 5 Resistive Charging of a Capacitor

It is resistive charging if charging current, IC= ΔVR/R, through full charging cycle

January 12-16, 2009 USPAS Pulsed Power Engineering TTU/Burkhart 6 Resistive Charging of a Capacitor

In resistive charging a minimum of 50% of the energy is dissipated in the charging resistor

January 12-16, 2009 USPAS Pulsed Power Engineering TTU/Burkhart 7 LR Circuit: Inductive Risetime Limit • At t=0, close switch and apply V=1 to LR circuit • Inductance limits dI/dt • Reach 90% of equilibrium current, V/R, in ~2.2 L/R

January 12-16, 2009 USPAS Pulsed Power Engineering C Burkhart 8 LR Circuit: Decay of Inductive Current • At t=0, current I=1 flowing in LR circuit • Fall to 10% of initial current in ~2.2 L/R

January 12-16, 2009 USPAS Pulsed Power Engineering C Burkhart 9 LRC Circuit • Generally applicable to a wide number of circuits and sub-circuits found in pulsed power systems • Presented in the more general form of CLRC (after NSRC formulary)

– Limit C1 → ∞, reduces to familiar LRC with power supply

– Limit C2 → ∞ (short), reduces to familiar LRC – Limit R → 0, reduces to ideal CLC energy transfer – Limit L → 0, reduces to RC

January 12-16, 2009 USPAS Pulsed Power Engineering C Burkhart 10 CLRC Circuit

Where: Switch L L R τ = R C C 1 2 + Ceq = C C 2 C1 + C2 1 i(t) 1 ωo = LCeq ⎛ ⎛ 1 ⎞ 2⎞ 2 ⎜ 2 ⎟ ω = ABS⎜ ωo − ⎜ ⎟ ⎟ ⎝ ⎝ 2τ ⎠ ⎠ L Z0 = Ceq Z Q = 0 = (Circuit Quality Factor) R

V0 = initial charg e voltage on C1

0 = initial charg e voltage on C2

January 12-16, 2009 USPAS Pulsed Power Engineering E Cook 11 Underdamped CLRC

Switch L R For underdamped case: R < 2Zo − t V + o 2τ C C i(t) = e sin ωt 1 i(t) 2 ωL V C ⎡ − t ⎛ 1 ⎞ ⎤ V ()t = 0 1 ⎢1 − e2τ sinωt − cosωt ⎥ C2 ⎜ ⎟ C1 + C2 ⎣⎢ ⎝ 2ωτ ⎠ ⎥⎦ 1 i @ t = tan−1()2ωτ peak 1 ω

−t1 −t1 V0 2τ V0 2τ V0 ipeak = e = e ≅ L Z0 Z0 + 0.8R

Ceq π it()= 0;VC ()t = peak @ t0 = 2 ω V C ⎛ −π ⎞ V t = 0 1 ⎜ 1+ e2ωτ ⎟ C2 ()peak ⎜ ⎟ C1 + C2 ⎝ ⎠

January 12-16, 2009 USPAS Pulsed Power Engineering E Cook 12 Highly Underdamped: Energy Transfer Stage

When R << Z (almost always the Switch L o R preferred situation in pulse circuits)

+ C C2 V0 1 i(t) ipeak = Z0 π ipeak @ t = = π LCeq ω0

V0C1 VC2 ()t = ()1 − cos()ω0t C1 + C2 2π

VC2 ()peak @ t = = 2π LCeq ω0 2V C V ()peak = 0 1 C2 C1 + C2

January 12-16, 2009 USPAS Pulsed Power Engineering E Cook 13 Highly Underdamped: Energy Transfer Stage (cont.) • Peak energy transfer efficiency

achieved with C1= C2

2

• If C1>> C2, the voltage on C2 will 1.5 go to twice the voltage on C1

Vri 1 Voltage Ratio

0.5

0 0246810

Cri Capacitance Ratio

January 12-16, 2009 USPAS Pulsed Power Engineering C Burkhart 14 Overdamped CLRC

Switch L Overdamped case R > 2Zo R

+ C C 1 i(t) 2 t − V e 2τ it()= 0 eωt − e−ωt 2ωL [] ⎡ ⎛ ⎞ ⎤ t V ⎢ 2ω − ⎜ e−ωt eωt ⎟ ⎥ 0 ⎢ 2τ ⎜ ⎟ ⎥ VC ()t = − e + 2 2ωLC ⎢ ω2 ⎜ 1 1 ⎟ ⎥ 2 ⎢ o ⎜ +ω −ω ⎟ ⎥ ⎣ ⎝ 2τ 2τ ⎠ ⎦

January 12-16, 2009 USPAS Pulsed Power Engineering E Cook 15 General LRC Solution • General solution from TTU Pulsed Power Short Course – Level of damping defined by β • β > 0: underdamped • β = 0: critically damped • β < 0: overdamped

January 12-16, 2009 USPAS Pulsed Power Engineering TTU-PPSC 16 General LRC Solution (cont.)

January 12-16, 2009 USPAS Pulsed Power Engineering TTU-PPSC 17 General LRC Solution (cont.)

January 12-16, 2009 USPAS Pulsed Power Engineering TTU-PPSC 18 Hard Tube Modulators • Pulsers in which only a portion of the stored electrical energy is delivered to the load. Requires a switch that can open while conducting full load current. – Switch must open/close with required load voltage and current – Voltage regulation limited by capacitor voltage droop – Flat output pulse → large capacitor/large stored energy •Cost • Faults • Name refers to “hard” vacuum tubes historically used as switch • Today’s fast solid-state devices are being incorporated into designs previously incorporating vacuum tubes

Rchg C + Echg + - C Z load R load Rg Vg - E + b

January 12-16, 2009 USPAS Pulsed Power Engineering Cook/Burkhart 19 Hard Tube: Topology Options • Capacitor bank with series high voltage switch - gives pulse width agility but requires high voltage switch

Total Loop High Voltage Gate Drive Circuits and Controls Inductance Switch

#1 #2 #n Large Capacitor + Load Load Bank Impedance Storage Impedance - DC Capacitor Power Supply

• Variations – Add series inductance: zero current turn on of switch – Series switches: reduces voltage requirements for individual switches • Issues: – Switches must have very low time jitter during turn-on and turn-off – Voltage grading of series connected switches, especially during switching – Isolated triggers and auxiliary electronics (e.g. power, diagnostics) – Switch protection circuits (load and output faults) – Load protection circuits

January 12-16, 2009 USPAS Pulsed Power Engineering Cook/Burkhart 20 Commercial Series Stack Modulator

.

January 12-16, 2009 USPAS Pulsed Power Engineering E Cook 21 Hard Tube: Topology Options • Grounded switch – simplifies switch control

Rchg C + Echg -

R load Rg Vg - E + b

• Issues: – Only works for one polarity (usually negative) – HVPS must be isolated from energy storage cap during pulse – Loose benefit with series switch array

January 12-16, 2009 USPAS Pulsed Power Engineering C Burkhart 22 Hard Tube: Topology Options • Pulse Transformer - reduces the high voltage requirements on switch

1:N Pulse Large Transformer Capacitor Bank - +

Load High Voltage Impedance Switch

• Issues:

– Very high primary current (N*Iload) and large di/dt for fast rise times – Requires very low primary loop inductance and very low leakage inductance: exacerbated by high turns ratio; L, C, Z scale with N2 – Fast opening switch required capable of interrupting primary current – Distortion of waveform by non-ideal transformer behavior

January 12-16, 2009 USPAS Pulsed Power Engineering Cook/Burkhart 23 Hard Tube: Topology Options • Bouncer modulator – compensates energy storage capacitor droop – Initially, SW2 is closed, voltage on C3 is transferred to C2 – Then SW1 is closed, applying output pulse to load – Energy transferred from C3 to C2, during linear portion of waveform, compensates for voltage droop of C1 – After output pulse is finished, energy from C2 rings back to C3, low loss • Used for XFEL and ILC (baseline) klystron modulators • Issues: – Extra components – Timing synchronization – Bouncer frequency low → large L and C’s

January 12-16, 2009 USPAS Pulsed Power Engineering C Burkhart 24 Line-Type Modulators • Based on the properties of transmission lines as pulse generating devices • Advantages – Minimum stored energy, 100% → load (neglecting losses) • Voltage fed, capacitive storage (E-field), closing switch • Current fed, inductive storage (B-field), opening switch – Fault (short circuit) current ≤ twice operating current (matched load) – Relatively simple to design and fabricate, inexpensive – Switch action is closing OR opening, but not both • Disadvantages – Fixed (and limited range) output pulse length – Fixed (and limited range) output pulse impedance • Output pulse shape dependent on relative modulator/load impedance

•Zload< Zpulser → voltage reversal, may damage switch or other components – Switch operates at twice the voltage (or current) delivered to load – Must be fully recharged between pulses: may be difficult at high PRF

January 12-16, 2009 USPAS Pulsed Power Engineering C Burkhart 25 Transmission Line Modulator

• Square output pulse is intrinsic • Pulse length is twice the single transit time of line: τ = 2ℓ/(cε½) – Vacuum: 2 ns/ft – Poly & oil: 3 ns/ft – Water: 18 ns/ft • Impedance of HV transmission lines limited: –~2 Ω≤Z ≤ ~200 Ω – ~30 Ω≤Z ≤ ~100 Ω for commercial coax – However, impedance can be rescaled using a pulse transformer • Energy density of coaxial cable is low (vs. capacitors) → large modulator • Fast transients (faster than dielectric relaxation times) stress solid dielectrics – Finite switching time and other parasitic elements introduce transient mismatches – Modulator/load impedance mismatches produce post-pulses

January 12-16, 2009 USPAS Pulsed Power Engineering C Burkhart 26 10 Ω, 40 ns TL Modulator: Load Matching

January 12-16, 2009 USPAS Pulsed Power Engineering C Burkhart 27 Blumlein Modulator • Major limitation of TL modulator: switch voltage twice load voltage • Blumlein Line – Requires Two Transmission Lines – Load voltage equals charge voltage

– Switch must handle current of Vo/Zo, twice the load current

Zo , τ V line t=0 Z Zo , τ Vline o , τ R=2Zo R=2Zo Vload t=0 Zo , τ Vline Vload Circuit on left - unfolded

Vload

Vline

time τ 2τ 0 Voltage across load (R)

January 12-16, 2009 USPAS Pulsed Power Engineering E Cook 28 Blumlein “Wave Model” • Initial conditions – 2 TL with a common electrode

– TLs charged to Vo

– TL Impedance: Zo

– Load impedance: R = 2 Zo • Switch closes at t = 0 – Wave that hits short, reflects with inverted polarity

– Voltage of Vo/2 on both ends of load, no load current – Wave in upper TL unchanged •t = T – Inverted wave reaches load

– Load voltage: Vo/2 - (-Vo/2) = Vo

– Load current: Vo/R – Load matched, no reflected wave in either TL • t = 3T: energy depleted

January 12-16, 2009 USPAS Pulsed Power Engineering C Burkhart 29 Blumlein Modulator

January 12-16, 2009 USPAS Pulsed Power Engineering J Mankowski 30 Blumlein in Comparison to Transmission Line •Switching – Blumlein charge (switch) voltage equals load voltage – Blumlein switch current is half of load current – Peak switch power is half of peak load power for both topologies – However, it is generally easier to get switches that handle high current than high voltage • Blumlein is more complicated – Either nested transmission lines or exposed electrode → half load voltage during pulse – More sensitive to parasitic distortion (e.g. switch inductance) • Both are important modulator topologies

January 12-16, 2009 USPAS Pulsed Power Engineering C Burkhart 31 Blumlein Modulator

Outer Housing - Ground

Dielectric Liquid High Voltage Insulator Load

Line 2

Line 1

Switch Charged Conductor Corona Ring to Reduce Electric Field Enhancement Large Radius to Reduce Electric Field Enhancement

Coaxial Blumlein Configuration

January 12-16, 2009 USPAS Pulsed Power Engineering E Cook 32 Advanced Test Accelerator Blumlein Modulator

January 12-16, 2009 USPAS Pulsed Power Engineering C Burkhart 33 Pulse Forming Networks (PFNs) • The maximum pulse duration of transmission line pulsers is limited by the physical length of the line, at 3 ns/ft, a 1 μs TL would be 330’ long • Transmission line can be approximated by an LC array – Higher energy density in capacitors – Higher energy density in solenoidal inductors – PFNs can produce long duration pulses in a compact package • Design equations –Z = (L/C)0.5 – τ = 2N(LC)0.5 (output pulse length) – For N-stages of inductance, L, and capacitance, C • However, the discrete element model of the TL is only accurate as the number of stages, N →∞ •Example –N = 7 –Z = 10Ω – Τ = 1 μs • C = 7.14 nF • L = 0.714 μH

January 12-16, 2009 USPAS Pulsed Power Engineering C Burkhart 34 Example PFN Output Into Matched Load

January 12-16, 2009 USPAS Pulsed Power Engineering C Burkhart 35 The Trouble with Pulse Forming Networks • Attempting to reproduce a rectangular pulse, which is non-causal

– ωmax = ∞, therefore, N must →∞ – PFNs constructed with finite N • Fourier series expansion of a rectangular pulse (period 0 to τ) ∞ – I (t) = (2 I /π ) ∑ b sin (nπt/τ) peak n=1 n

•bn= (1/n) (1 – cos (nπ)) = 0 for even n, 2 for odd n ∞ – I (t) = (4 I /π ) ∑ (1/n) sin (nπt/τ) over only odd terms, n = 1,3,5,... peak n=1 • Magnitude of the nth term α 1/n, sets convergence rate for a rectangular pulse

January 12-16, 2009 USPAS Pulsed Power Engineering C Burkhart 36 Fourier Components for a Rectangular Pulse (Peak amplitude and duration normalized to unity)

1.4

1.2

I1() t 1

I2() t 0.8 I3() t 0.6 I4() t 0.4 I5() t

I6() t 0.2

I7() t 0

0.2

0.4

0.6 0 0.2 0.4 0.6 0.8 t

January 12-16, 2009 USPAS Pulsed Power Engineering C Burkhart 37 Fourier Approximation to a Rectangular Pulse

1.4

1.2 I1s() t

I2s() t 1

I3s() t

I4s() t 0.8

I5s() t 0.6 I6s() t

I7s() t 0.4

0.2

0 0 0.2 0.4 0.6 0.8 t

January 12-16, 2009 USPAS Pulsed Power Engineering C Burkhart 38 Guillemin Networks: The Solution to “The Trouble with PFNs”

• E.A. Guillemin recognized that the discontinuities due to – Zero rise/fall time, and – Corners at the start/stop of the rise and fall are the source of the high frequency components that challenge PFN design. “Communication Networks,” 1935 • Further, since such a perfect waveform cannot be generated by this method, that better results can be obtained by intentionally design for finite rise/fall times (i.e. trapezoidal pulse) and by rounding the corners (i.e. parabolic rise/fall pulse) • Fourier decomposition of these waveforms shows faster convergence – Trapezoidal: nth term α 1/n2 – Parabolic: nth term α 1/n3

January 12-16, 2009 USPAS Pulsed Power Engineering C Burkhart 39 PFN Design

Instead of infinitely fast rise and fall-times, the desired pulse shape should have a reasonable (finite) rise and fall time. A design procedure then assume a repetition of pulses as shown below so that a Fourier analysis can be performed.

The Fourier expansion of the current required to generate a waveform of Switch this shape into a constant resistive Vn t load consists of only sine terms. i(t)n = sin( ) Ln LnCn Each sinusoid in the series: Ln ∞ nπt C Vn n i(t) = Ipk ∑ bn sin n=1, 3,5 ,... τ i(t) Vn n C may be produced by the adjacent n it()n = sinωot Z circuit: n

January 12-16, 2009 USPAS Pulsed Power Engineering E Cook 40 PFN Design Comparing the amplitude and frequency terms for the Fourier coefficients and the LC loop:

nπt Vn t I pkbn sin = sin( ) τ Ln LnCn

Cn

Vn nπ 1 I pkbn = and = Ln τ LnCn

Cn

Solving for Ln and Cn :

Znτ Vn Ln = where Zn = nπb n I pk

τbn Cn = nπZn

January 12-16, 2009 USPAS Pulsed Power Engineering E Cook 41 Fourier Coefficients for Trapezoidal Waveform

Fourier Coefficients for Risetime = 8%

1.4 I pk 1.2

1 1st Harmonic 3rd Harmonic 5th Harmonic 0.8 7th Harmonic aτ aτ 9th Harmonic 0.6 0 11th Harmonic

Time 0.4

τ 0.2

0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 -0.2

-0.4

For the trapezoidal waveform shown -0.6 above the series expansion is: Time

∞ nπt i(t) = Ipk ∑ bn sin n=1, 3,5,... τ

4 sin nπa b = n nπ nπa where n = 1,3,5,... And a = risetime as % of pulsewidth τ

January 12-16, 2009 USPAS Pulsed Power Engineering E Cook 42 Example Sum 1-6 Fourier Coefficients - for 8% Risetime

1.4

1.2

1

0.8 1st Harmonic 1+3 0.6 1+3+5 1+3+5+7 1+3+5+7+9 0.4 1+3+5+7+9+11

0.2

0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

-0.2 Time

January 12-16, 2009 USPAS Pulsed Power Engineering E Cook 43 Example -

Sum 1-6 Fourier Coefficients - for 5% Risetime

1.4

1.2

1

0.8 1st Harmonic 1+3 0.6 1+3+5 1+3+5+7 1+3+5+7+9 0.4 1+3+5+7+9+11

0.2

0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

-0.2 Time

January 12-16, 2009 USPAS Pulsed Power Engineering E Cook 44 Trapezoidal and Parabolic Waveshapes Ipk Ipk

aτ aτ aτ aτ 0 0 Time Time τ τ

Trapezoidal Waveshape Waveshape with Parabolic Rise and Fall Time

Values of bv, Ln, and Cn for this circuit topology;

L1 L3 L5 LM-2 LM Waveform bn Ln Cn

C1 C3 C5 CM-2 CM 4 Z τ 4τ N Rectangular 2 2 nπ 4 n π ZN 4 ⎛ sinnπa⎞ Z t 4τ ⎛ sin nπa⎞ ⎜ ⎟ N ⎜ ⎟ nπ ⎝ nπa ⎠ ⎛ sin nπa⎞ n 2 p2 Z ⎝ nπa ⎠ Trapezoidal 4⎜ ⎟ N ⎝ nπa ⎠ 2 2 ⎛ 1 ⎞ ⎛ 1 ⎞ Flat top and 4 sin 2 nπa ZNτ 4τ sin 2 nπa ⎜ ⎟ 2 ⎜ ⎟ ⎜ 1 ⎟ 1 2 2 ⎜ 1 ⎟ nπ ⎝ 2 nπa ⎠ ⎛ sin nπa⎞ n π ZN ⎝ 2 nπa ⎠ parabolic rise 4⎜ 2 ⎟ ⎜ 1 nπa ⎟ and fall ⎝ 2 ⎠

January 12-16, 2009 USPAS Pulsed Power Engineering E Cook 45 Fourier Coefficients for Other Waveshapes

Values of Inductances and Capacitances for Five-Section Pulse-Forming Network

Multiply the inductances by and the capacitances by /Z . The inductances are given in ZNτ τ N henrys and the capacitances in farads if the pulse duration is expressed in seconds and the network impedance is in ohms. a is fractional risetime of pulse.

∞ ∞ VN nπt nπt i(t) = ∑ bn sin = I pk ∑ bn sin ZN n=1,3 ,5,... τ n =1,3, 5,... τ

January 12-16, 2009 USPAS Pulsed Power Engineering E Cook 46 PFN Design

The network required to produce all the Fourier components and therefore L1 L3 L5 LM-2 LM reproduce the pulse waveshape is:

C1 C3 C5 CM-2 CM

The problem with this circuit network is that physical inductors have stray shunt capacitance which distort the waveshape and the required values of capacitors have a wide range of values which increases costs.

The mathematical approach is to use the impedance function of the above circuit and derive networks having other topologies but the same impedance function. Six basic circuit topologies have been derived (including the above circuit).

January 12-16, 2009 USPAS Pulsed Power Engineering E Cook 47 Synthesis of Alternate LC Networks

L1 L3 L5 LM-2 LM

C1 C3 C5 CM-2 CM

The admittance function for the above circuit has the form:

C1s C3s Ys()= 2 + 2 +..... L1C1s +1 L3C3s +1 1 Zs()= Ys() Zs() in turn can be expanded about its poles to yield equivalent networks have other circuit topologies

January 12-16, 2009 USPAS Pulsed Power Engineering E Cook 48 Equivalent Guillemin Networks • Type A: – Capacitances vary – Little used • Type B: – Capacitances vary – Similar in layout to Type E • Type C: – Capacitances vary – Straightforward design – Often used (SLAC 6575) • Type D – Fixed capacitance – Negative inductances – Basis for Type E • Type F – Capacitances vary

January 12-16, 2009 USPAS Pulsed Power Engineering C Burkhart 49 PFN - Type E

=~

The negative inductance that are seen in the Type D PFN represent the mutual inductance between adjacent inductors and may be realized in physical form by winding coils on a single tubular form (solenoid) and attaching the capacitors to the inductor at appropriate points on the inductor.

The quality of the output pulse is dependent on the number of sections used. For a waveform having a desired risetime/falltime of ~ 8% of the total pulsewidth, five sections (each consisting of one inductor and one capacitor) prove to be adequate to produce the desired waveshape. A sixth section provided only slight improvement. This corresponds to the relative magnitude of the Fourier-series components for the corresponding steady-state alternating current wave. The relative amplitude of the fifth to the first Fourier coefficient is ~4% while the sixth to the first is ~ 2%.

Note: If faster risetimes/falltimes are required, the number of sections needed to satisfy that risetime increases.

January 12-16, 2009 USPAS Pulsed Power Engineering Cook/Burkhart 50 Type E PFN- Practical Design Parameters •For : LN – PFN Characteristic Impedance = Zo Zo = CN – PFN Output Pulse Width = 2τ •whereLN = total PFN inductance and τ = LNCN CN = total PFN capacitance – The total PFN inductance (including mutual inductances) and capacitance is divided equally between the number of sections. – Empirical data have shown that the best waveshape can be achieved when the end inductors should have ~20-30% more self inductance. The mutual inductance should be approximately 15% of the self inductances. • Bottom line: don’t bust your pick designing a “perfect” PFN – Capacitance values vary from can-to-can and with time – Inductor values are never quite as designed – Strays; inductance, capacitance, resistance, distort the waveform – and should you somehow overcome all of the foregoing, you can be certain that the technicians will “tune” the PFN and your “perfect” waveform will be but a memory

January 12-16, 2009 USPAS Pulsed Power Engineering Cook/Burkhart 51 PFN Design for Time Varying Load • Within a limited range, the impedance of individual PFN sections may be adjusted to match an impedance change in the load. – For example: Each section of a 5 section roughly drives 20% of the load pulse duration. If the load impedance is 10% lower for the first 20% of pulse, designing the first section of the PFN (section closest to the load) to be 10% lower than rest of the PFN will make a better match and generate a flatter pulse. – This approach works only if the load impedance is repeatable on a pulse- to-pulse basis

January 12-16, 2009 USPAS Pulsed Power Engineering E Cook 52 PFN: Practical Issues • Switch: In addition to voltage and peak current requirements, must also be able to handle peak dI/dt (highest frequency components will be smaller magnitude and may be difficult to observe) – SLC modifications to 6575 doubled dI/dt – Even with 2 thyratrons, short tube life – Solved by adding “anode reactor” (magnetic switch in series with tube)

• Positive mismatch, Zload > ZPFN – “Prevents” voltage reversal (may still get transient reversals), improves lifetime • Switch • Capacitors •Cables – Incorporate End Of Line (EOL) clipper to absorb mismatch energy • Inductors – Must not deform under magnetic forces –Tuneable • Movable tap point • Flux exclusion lug • PFN impedance range is limited (just like PFLs), as is maximum switch voltage – Transformers can be used to match to klystron load – SLAC 6575 modulators are matched to 5045 klystrons with a 1:15 transformer

January 12-16, 2009 USPAS Pulsed Power Engineering C Burkhart 53 Charge Circuits - Basics

High Voltage C Switch load - +

Charge Circuit Power Charge Circuit + Load Power Load Impedance Supply Impedance Supply- Cload High Voltage Switch

Where Cload represents the capacitance of a transmission line, PFN, energy storage for a hard-tube circuit, etc.

The charge circuit is the interface between the power source and the pulse generating circuit and may satisfy the following functions:

Ensures that Cload is charged to appropriate voltage within the allowable time period. Provides isolation between the power source and the pulse circuit: Limit the peak current from the source. Prevent the HV switch from latching into an on state and shorting the power source. Isolate the power source from voltage/current transients generated by pulse circuit.

January 12-16, 2009 USPAS Pulsed Power Engineering E Cook 54 AC Power Rectification

January 12-16, 2009 USPAS Pulsed Power Engineering TTU-PPSC 55 AC Power Rectification

January 12-16, 2009 USPAS Pulsed Power Engineering TTU-PPSC 56 AC Power Rectification

January 12-16, 2009 USPAS Pulsed Power Engineering TTU-PPSC 57 AC Power Rectification

January 12-16, 2009 USPAS Pulsed Power Engineering TTU-PPSC 58 AC Power Rectification

January 12-16, 2009 USPAS Pulsed Power Engineering TTU-PPSC 59 AC Power Rectification

January 12-16, 2009 USPAS Pulsed Power Engineering TTU-PPSC 60 AC Power Rectification

January 12-16, 2009 USPAS Pulsed Power Engineering TTU-PPSC 61 AC Power Rectification

January 12-16, 2009 USPAS Pulsed Power Engineering TTU-PPSC 62 AC Power Rectification

January 12-16, 2009 USPAS Pulsed Power Engineering TTU-PPSC 63 AC Power Rectification

January 12-16, 2009 USPAS Pulsed Power Engineering TTU-PPSC 64 AC Power Rectification

January 12-16, 2009 USPAS Pulsed Power Engineering TTU-PPSC 65 AC Power Rectification

January 12-16, 2009 USPAS Pulsed Power Engineering TTU-PPSC 66 AC Power Rectification

January 12-16, 2009 USPAS Pulsed Power Engineering TTU-PPSC 67 AC Power Rectification

January 12-16, 2009 USPAS Pulsed Power Engineering TTU-PPSC 68 AC Power Rectification

January 12-16, 2009 USPAS Pulsed Power Engineering TTU-PPSC 69 AC Power Rectification

January 12-16, 2009 USPAS Pulsed Power Engineering TTU-PPSC 70 AC Power Rectification

January 12-16, 2009 USPAS Pulsed Power Engineering TTU-PPSC 71 AC Power Rectification

January 12-16, 2009 USPAS Pulsed Power Engineering TTU-PPSC 72 AC Power Rectification

January 12-16, 2009 USPAS Pulsed Power Engineering TTU-PPSC 73 Charging Topologies • Resistive charging • Constant current resistive charging • Capacitor charging power supplies • Inductive charging – DC resonant charge – AC resonant charge – CLC resonant charge •De-Qing

January 12-16, 2009 USPAS Pulsed Power Engineering C Burkhart 74 Resistance Charging

High Voltage R Switch chg

+ t=0 + V V (0) = 0 o i(t) - c Cload

−t Charge Circuit V R C it()= o e c hg Load Rchg ⎛ −t ⎞ R C V ()t = V ⎜ 1 − e c hg Load ⎟ CLoad o ⎜ ⎟ ⎝ ⎠ 1 Energy ≈ C V 2, t > 4R C Load 2 Load o chg Load ∞ ∞ ⎛ ⎞ 2 −2t V R C Energy = i2 t R dt = R ⎜ o ⎟ e chg Load dt Lost ∫ () chg c ∫⎜ ⎟ 0 0 ⎝ Rc ⎠ −2t 2 ⎛ R C ⎞ ∞ Maximum charging efficiency is 50% Vo chg Load Rchg CLoad 1 2 = ⎜ − ⎟ e = CLoadVo 0 (independent of the value of Rchg) Rchg ⎝ 2 ⎠ 2

January 12-16, 2009 USPAS Pulsed Power Engineering E Cook 75 Resistance Charging • Advantages – Inexpensive – Simple – Allows use of low average power, power supply – May eliminate the need for a high voltage switch – Provides excellent isolation – Stable and repeatable – Charge accuracy is determined by regulation of power supply • Disadvantages – Inefficient – Slow for high energy transfers – Requires resistor rated for full charge voltage and, depending on the charge time and energy transferred, a high joule/pulse or average power rating

January 12-16, 2009 USPAS Pulsed Power Engineering E Cook 76 Constant Current Resistance Charging High Voltage R Switch chg

+ t=0 + V V (0) = 0 o I=constant - c Cload

Charge Circuit Q IT V = = where T = time for V to approach V CLoad C Load o CLoad CLoad T E = I 2 R dt = I 2 R T Lost ∫ chg chg 0 2 1 2 ()IT EStored = CLoadVC = 2 Load 2C Load Efficiency approaches 100% as EStored T Efficiency = = T>>2RchgCLoad EStored + ELost T + 2RchgCLoad Efficiency = 71% for

T =5RchgCLoad

January 12-16, 2009 USPAS Pulsed Power Engineering Cook/Burkhart 77 Constant Current Charge • Advantages – Efficient – Power and voltage rating on charge resistor is low – Can still provide excellent isolation • Disadvantages – Expensive: requires constant current power supply or controllable voltage source – Maximum burst rep-rate determined by charge rate

January 12-16, 2009 USPAS Pulsed Power Engineering E Cook 78 Charging Efficiency is Waveform Sensitive

January 12-16, 2009 USPAS Pulsed Power Engineering E Cook 79 Capacitor Charging Power Supplies Constant current power supply • Positive attributes – Efficient (>85%) – Low stored energy – Stable and accurate (linear to ~1% and with 1% accuracy) – Can be operated from DC output to kHz repetition rates – Compact (high energy density) – Good repeatability (available to <0.1% at rep rates) – Output voltage ranges up to 10’s of kV and controllable from 0-100% at rated output voltage – Charge rate usually specified at Joules/sec – Internally protected against open circuits, short circuits, overloads and arcs – Locally or Remotely controllable

January 12-16, 2009 USPAS Pulsed Power Engineering E Cook 80 Capacitor Charging Power Supplies • Issues – Cost (usually > $1/watt) – External protection must usually be provided for voltage reversals at load

Rt terminates the output cable and prevents the voltage reversal from the

closing of switch S1 from appearing across D1. Ro is the internal resistance of the power supply and is usually on

the order of a few ohms. Co is the internal power supplies internal capacitance and may only be a few hundred pF.

Generalized HV Supply Load Connection

January 12-16, 2009 USPAS Pulsed Power Engineering E Cook 81 Capacitor Charging Power Supplies

Voltage Reversal Protection Circuit

The protection diode needs to have: a reverse voltage rating that is higher than the circuit operating voltage and the supply operating voltage (with a safety factor); a rms current rating higher HV Supply output diode under voltage than seen in the circuit; and a forward voltage drop reversal conditions during conduction that is less than the voltage drop in the power supplies’ diodes (if Rt’ is not used). If used, Rt’ should be selected to limit the current to the supply rated output current or less.

January 12-16, 2009 USPAS Pulsed Power Engineering E Cook 82 Capacitor Charging Power Supplies • Useful relationships: – Charge time

1 CLoadVchgVrated Tchg = 2 Ppeak – Peak power rating

1 CLoadVchgVrated Ppeak = 2 Tchg – Average power rating 1 P = C V V PRF avg 2 Load chg rated

– Maximum repetition rate Where: 1 Pavg Tc is the load charge time in seconds PRFmax = 2 CLoadVchgVrated Ppeak is the unit peak power rating C is the load capacitance in Farads – Output current load V is the load charge voltage in volts 2P chg peak Vrated is the power supply rating in volts Ioutput = Vrated

January 12-16, 2009 USPAS Pulsed Power Engineering E Cook 83 Capacitor Charging Power Supplies

• Switch-mode power supplies • Constant current on recharge time scales, but little output filtering so high frequency structure of the converter is on the output current – May result in increased losses in charge circuit components (e.g. diodes)

January 12-16, 2009 USPAS Pulsed Power Engineering C Burkhart 84 Inductor Charging - DC Resonant Charge High Voltage L Switch Chg Diode

+ t=0 + V o i(t) - Cload Vc(0) = 0

Charge Circuit ⎛ ⎞ (Assume R=O) Vo ⎜ t ⎟ Vo it()= sin⎜ ⎟ = sinω ot Lchg ⎝ LchgCLoad ⎠ Zo

CLoad 1 t V t = itdt c() ∫ () CLoad 0 t =−Vo cosωot 0

= Vo()1− cosωot

Maximum value of Vc at t=π/ωo

January 12-16, 2009 USPAS Pulsed Power Engineering E Cook 85 DC Resonant Charge • Advantages – Efficient - approaches 100% – Due to voltage gain, PS can be ~ 1/2 of desired load voltage – Easily capable of high repetition-rate operation – Practical and easy to implement – Low di/dt requirements for the high voltage switch • Disadvantages – Requires isolation diode (unless load is discharged at the peak of charging) – May require a high voltage switch (command resonant charge) – Inductor must be designed for high voltage operation – Power supply must be capable of providing the peak current

January 12-16, 2009 USPAS Pulsed Power Engineering E Cook 86 DC Resonant Charge with Resistive Losses High Voltage L Switch Chg R Diode

+ t=0 + V o i(t) - Vc(0) = 0 Cload

Charge Circuit − t

Vo 2 Lchg / R 2 R it()= e sinωt where ω = ωo − Zo 2Lchg ⎡ −t ⎛ ⎞ ⎤ ⎢ 2 Lchg / R ⎜ R ⎟ ⎥ VC ()t = Vo 1 − e cosωt + sinωt Load ⎢ ⎜ ⎟ ⎥ ⎣ ⎝ 2ωLchg ⎠ ⎦

Total energy provided to circuit = IavgVoTchg where Tchg = charging period Q C V chg Load C Load Iavg = = Tchg Tchg

1 2 CLoadVC Load TchgVC Efficiency = 2 = Load IavgVoTchg 2Vo π ωL Efficiency ≈1 − where Q = chg and Q > 10 4Q R

January 12-16, 2009 USPAS Pulsed Power Engineering E Cook 87 AC Resonant Charge

High Voltage Switch LChg Diode

t=0 + V sinωt o i(t) - V (0) = 0 Cload c

1 =ω Choose Lchg and Cload such that: L C V chg Load it()= o t sinωt 2Lchg V ⎡ 1 ⎤ V = o ⎢ −t cosωt + sinωt ⎥ CLoad ⎣ ⎦ 2Zo ω 1 π for a cycle, t = π Lchg CLoad = 2 ω ⎛ π ⎞ π VC ⎜ ⎟ = Vo Load ⎝ ω⎠ 2

January 12-16, 2009 USPAS Pulsed Power Engineering E Cook 88 AC Resonant Charge • Advantages – High efficiency – Voltage gain reduces the source voltage requirement – Low di/dt requirements for high voltage switch – High voltage switch not needed if repetition rate is same as source frequency • Disadvantages – Requires high frequency ac source or very large inductor

– Diode must have large inverse voltage rating (πVo) – Peak repetition rate is limited by source frequency

January 12-16, 2009 USPAS Pulsed Power Engineering E Cook 89 DC Resonant Charge - Capacitor to Capacitor Charge Circuit Used when power supply can’t provide the peak charge current High Voltage Switch L Diode (e.g. high power systems) Chg t=0 + + V o - i(t) - Cload Co

Vc(0) = 0 Charge Circuit

⎛ ⎞ V t V C C it()= o sin⎜ ⎟ = o sinωt where C = o Load ⎜ ⎟ eq C + C Lchg ⎝ LchgCeq ⎠ Z o Load

Ceq ⎛ π ⎞ C At peak voltage ⎜ t = ⎟ : V = 2Vo eq ⎝ ⎠ CLoad C ω C Load 2V C For C 10C : V o o 1.82V o = Load CLoad = = o Co + CLoad

January 12-16, 2009 USPAS Pulsed Power Engineering E Cook 90 DC Resonant Charge - Capacitor to Capacitor • Advantages – Efficient – Voltage gain reduced the PS voltage requirement – Easily capable of high repetition rate operation – Can operate asynchronously – Power supply isn’t required to provide large charge current when system is operating at low duty factor – Low di/dt requirements on high voltage switch • Disadvantages – Requires a large DC capacitor bank – DC capacitor bank needs to be fully recharged between pulses to ensure voltage regulation at the load, unless alternative regulation techniques are employed

January 12-16, 2009 USPAS Pulsed Power Engineering E Cook 91 DC Resonant Charge with Resistor Charge

High Voltage Co recharged through R L R Switch Chg Diode after the Cload is inductively charged. + t=0 + + V C o o - i(t) - Cload

−t V (0) = V V0 − V1 RCo Co 1 iC ()t = e Charge Circuit 0 R ∞ 2 1 2 EnergyLoss = iC ()t Rdt = Co()V0 − V1 ∫ o 0 2

1 2 2 ΔEnergyStored = Co()V0 − V1 2 ⎛ ⎛ ⎞ 2 ⎞ ⎜ V1 ⎟ 1 − ⎜ ⎟ 1 ⎜ ⎝ V ⎠ ⎟ Efficiency = ⎜ 0 ⎟ 2 ⎜ ⎛ V ⎞ ⎟ 1 ⎜ 1 ⎟ ⎜ − ⎜ ⎟ ⎟ ⎝ ⎝ V0 ⎠ ⎠

For Co = 10CLoad : Efficiency = 90.9%

January 12-16, 2009 USPAS Pulsed Power Engineering E Cook 92 Effects of Stray Capacitance

Diode LChg

+ + V + V (0) = 0 o - C i(t) - c s Cload Co

After CLoad is charged : Charge Circuit V ≅ 2V and V ≅ V Cs = Stray Capacitance to ground CLoad o Cs o C o >> CLoad >> Cs

LChg

+ + V o i(t) 2Vo C - - s Cload Peak inverse diode voltage ~2Vo instead of Vo V V it()= o sin()ωt = o sinωt Lchg Z

Ceq C C 1 where C = s Load and ω = VCs = 2Vo − Vo cosωt eq Cs + CLoad LchgCeq

January 12-16, 2009 USPAS Pulsed Power Engineering E Cook 93 Effect of Stray Capacitance

L L Chg Diode s Cs - stray capacitance to ground Cd - stray capacitance across diode stack + C V + d Cload + o Cs (includes diode junction capacitance, - Co - capacitance between mounting connections, etc.) i(t) Ls- total series inductance between diode and ground Charge Circuit

L L Chg Cd s

Equivalent Circuit where: C >>C >>C ,C + o Load s d V + Cload + o Cs 2Vo 2V - o Co -

After CLoad is charged:

Cs will ring with Co and can create large inverse voltage across the diode stack CLoad will oscillate with Cd and Cs

Inductor Snubber and/or Diode Snubber may be required

January 12-16, 2009 USPAS Pulsed Power Engineering E Cook 94 Diode Snubber C C C DS RDS DS RDS DS RDS

RC RC RC L s

Rc is used for DC grading of diodes to force voltage sharing between diodes. Want the current V through R to be large compared to the maximum leakage current (I )through the diodes: Diode c r Rc ≈ 10Ir

CDS and RDS form the fast snubber where CDS is for voltage sharing and RDS is for damping. Energy is stored in CDS and dissipated in RDS.

Considerations for CDS : Considerations for R DS :

Charge stored @ ~ 0.7 volts ≥ 10 diode junction charge 2 Ls RDS > where N is the number of series diodes C N CDS DS >> the stray capacitance of the entire stack (N diodes) N N 1 dV C DS should be as small as possible for higher efficiency is small compared to maximum applied RDSCDS dt 2 Power Dissipation Rating ≥ 2(PRF)CDSVr where Vr is the maximum inverse voltage on the diode

January 12-16, 2009 USPAS Pulsed Power Engineering E Cook 95 Charge Inductor Snubber

Diode LChg

Co >> CLoad >> Cs

+ 1 + C ω = V C 2V load + 2V o o s o o LchgCs - - Co

L Chg Select CLS >Cs LChg

CLS R LS Considerations for RLS: R + LS 1 L C 2V chg s o ()1 : RLS < (critically damped) 2 Cs

Cs ()2 : Ensure power rating is adequate : 2 P ≥ 2(PRF)CLSV0 Equivalent circuit with ()3 : Adequate voltage rating (> V ) snubber across inductor o ()4 : Want RLSCLS >> charging period

January 12-16, 2009 USPAS Pulsed Power Engineering E Cook 96 Inductive Charging Voltage Regulation • For klystron phase stability, PFN charge voltage regulation may need to be ~10 ppm • High power supplies usually do not have precise regulation – Requires more complicated topologies (over simple rectifier/filter) – Increases cost • Common approach to regulate PFN charge voltage from unregulated source is de-Qing – Monitor PFN voltage during charge cycle – When PFN reaches final voltage, shunt energy remaining in charge inductor to dummy load

January 12-16, 2009 USPAS Pulsed Power Engineering C Burkhart 97 De-Qing

January 12-16, 2009 USPAS Pulsed Power Engineering C Burkhart 98 De-Qing Limitation • During the delay between the measurement of the PFN reaching the desired charge voltage and the termination of charging current (system delay), the PFN voltage continues to increase • When the unregulated source voltage is higher, charging current is increased and the PFN voltage increase during the system delay is increased (ΔVPFN) • This error must be corrected for precise PFN voltage regulation – Phase advance on voltage divider

• Measured signal, VM, actually higher than PFN voltage, VPFN

• Ratio of VM/VPFN is a function of PFN charge rate • Compensates delay • Used in SLAC 6575 – Feed forward control loop • Measure final PFN voltage • Adjust timing if voltage fluctuates •Used at PAL – Similar regulation accuracy

January 12-16, 2009 USPAS Pulsed Power Engineering C Burkhart 99 Control System Functions • Control output waveform – Voltage – Pulse shape – Timing • Protect system (MPS) – Over voltage – Over current – Heater time-outs –Etc. • Protect personnel (PPS) – PPS interlocks –Emergency Off – Access interlocks – Energy discharge • Bleeder resistors across capacitors • Engineered grounds

January 12-16, 2009 USPAS Pulsed Power Engineering C Burkhart 100 Control System Elements • Lab Scale: independent elements – Charging supply with integrated controls – Trigger generator – Diagnostics • Oscilloscope • Probes – Voltage divider – Current transformer • Installations – Control system interfaces to many operators/users and many other machines/systems: an integrated control system is required • Periodic evaluation • Configuration control – Control system may incorporate many components at varying levels • Integrated modulator control (modern trend) • System level (e.g. HLRF) • Facility level (e.g. accelerator)

January 12-16, 2009 USPAS Pulsed Power Engineering C Burkhart 101 Elements of the 6575 Modulator Control System

January 12-16, 2009 USPAS Pulsed Power Engineering C Burkhart 102 Integrated Control Elements • Programmable Logic Controller (PLC) – Replaces relay logic – Serial communication interface (can support EPICS communication) – Limitations •Slow • Loop timing not clocked • But, can be combined with additional circuits to expand capabilities – Sample-hold – Peak detect ILC-Marx PLC chassis – Various A-D and D-A • Programmable logic devices (CPLD, FPGA) – Fast, to >100 MHz clock – Powerful – Compact – Flexible – Communication options

– Inexpensive (after development costs) Control board for SLAC developed ILC-Marx

January 12-16, 2009 USPAS Pulsed Power Engineering C Burkhart 103