US 200400699.91A1 (19) United States (12) Patent Application Publication (10) Pub. No.: US 2004/0069991A1 Dunn et al. (43) Pub. Date: Apr. 15, 2004

(54) PEROVSKITE CUPRATE ELECTRONIC (52) U.S. Cl...... 257/75 DEVICE STRUCTURE AND PROCESS

(75) Inventors: Gregory Dunn, Arlington Heights, IL (57) ABSTRACT (US); Robert Croswell, Hanover Park, IL (US); Jeffrey Petsinger, Wayne, IL (US) High quality epitaxial layers of monocrystalline materials (26) can be grown overlying monocrystalline Substrates (22) Correspondence Address: Such as large Silicon wafers by forming a compliant Substrate OBLON SPIVAK MCCLELLAND MAIER & for growing the monocrystalline layers. An accommodating NEUSTADT buffer layer (24) comprises a layer of monocrystalline oxide 1755JEFFERSON DAVIS HIGHWAY Spaced apart from a Silicon wafer by an amorphous interface FOURTH FLOOR layer (28) of silicon oxide. The amorphous interface layer ARLINGTON, VA 2.2202 (US) dissipates Strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Any (73) Assignee: MOTOROLA, INC., Schaumburg, IL lattice mismatch between the accommodating buffer layer (21) Appl. No.: 10/267,692 and the underlying Silicon Substrate is taken care of by the amorphous interface layer. Some preferred electronic (22) Filed: Oct. 10, 2002 devices are described that use a layer or pattern of a perovskite cuprate (2125, 2305, 2310, 2315,2405) such as Publication Classification YBa-Cu-O, (YBCO) or Y, Pr, Ba-Cu-O, (YPBCO, 0strontium (51) Int. Cl...... H01L 29/04 aluminum tantalate (LSAT).

Patent Application Publication Apr. 15, 2004 Sheet 1 of 10 US 2004/0069991 A1

At A G 3 Patent Application Publication Apr. 15, 2004 Sheet 2 of 10 US 2004/0069991 A1

42

AfA.G.. 4

LATTICE MISMATCH

Patent Application Publication Apr. 15, 2004 Sheet 3 of 10 US 2004/0069991 A1

COUNTS/S 10000

1000 o STO(200) 100 STO(100) CoAs(200) A I Wy"My th s I | byl

Af7 G. 27 Patent Application Publication Apr. 15, 2004 Sheet 4 of 10 US 2004/0069991 A1

COUNTS/S

". t y"y Patent Application Publication Apr. 15, 2004 Sheet 5 of 10 US 2004/0069991 A1

AfZ G. Z3

At 7 G. 74 Patent Application Publication Apr. 15, 2004 Sheet 6 of 10 US 2004/0069991 A1

1022 1024 O26

( 108C ISF D El No. 1104 1106 1106 1104 110 9 AZG. Zaf

1022 1024 1026

2)122 124H 125 1114 K/2zz, N.NY H/ ?t / NY

logC III at\ El 1104 1106 1120 1102 1118 1106 1104 110 AZG. Zes 1026 1022 1024

132 124 —? 1EN

\'Til I is no is 1104 1106 112O 1102 1118 1106 1104

11O

Patent Application Publication Apr. 15, 2004 Sheet 7 of 10 US 2004/0069991 A1

144

148 1022 1O24 O26

132 F/ \- 146 1122 142 1122 124 — E/ENY 110 Odi / IWC is more 1104 1106 12 102 1118 1106 110 9 AZG. Zs

1022 1024 1026 1.

1104 1106 112O 1102 1118 1106 1104 110 Patent Application Publication Apr. 15, 2004 Sheet 8 of 10 US 2004/0069991 A1

22O N N N N Patent Application Publication Apr. 15, 2004 Sheet 9 of 10 US 2004/0069991 A1

221 O

- 2205 -2130 - 2125

-2110 2105

22OO AvAG 22

2305 2315 231 O

-2110 2105

23OO At ZG 2.3 Patent Application Publication Apr. 15, 2004 Sheet 10 of 10 US 2004/0069991 A1

US 2004/0069991 A1 Apr. 15, 2004

PEROWSKITE CUPRATE ELECTRONIC DEVICE and lattice-matched to Superconducting STRUCTURE AND PROCESS YBa-Cu-O,(YBCO) or Y, Pr, Ba-Cu-O, (YPBCO, 0single crystal substrate. A Mott insulator low cost monocrystalline Substrate, and for a proceSS for perovskite oxide such as the cuprates La CuO or Y making Such a structure. In other words, there is a need for x)Prs Ba-Cu-O,(YBCO) is used for p-type channel layers, providing the formation of a monocrystalline SubStrate that and the perovskite cuprate NdCuO is used for n-type is compliant with a high quality monocrystalline cuprate channel layers. A perovskite oxide Such as STO is used as layer So that true two-dimensional growth can be achieved the gate oxide. Under an applied gate field, the Mott insu for the formation of quality Semiconductor, Superconductor, lator becomes conducting. The Mott FET has a basic struc and metal-insulator transition Structures, devices and inte ture and function that is similar to a MOSFET, but the device grated circuits. dimensions are limited only by the methods available for patterning, and Scaling to below 30 nm is possible. BRIEF DESCRIPTION OF THE DRAWINGS 0003) The Mott FET faces two fundamental barriers to practical implementation. First, the use of very high cost 0007. The present invention is illustrated by way of STO substrates, which are available only in very small example and not limitation in the accompanying figures, in diameters (2 inches), imposes a severe limit on manufac which like references indicate Similar elements, and in turability and cost competitiveness. Second, the perfor which: mance of the Mott FET is strongly dependent on the 0008 FIGS. 1, 2, and 3 illustrate schematically, in cross epitaxial quality of the channel layer. The highest degree of Section, device Structures in accordance with various long range order and the lowest density of imperfections is embodiments of the invention; required. Lattice mismatch (>2.5%) when STO is used under 0009 FIG. 4 illustrates graphically the relationship a cuprate such as YBCO will result in strain in the YBCO between maximum attainable film thickneSS and lattice layer, causing defects to form and thus degrading device mismatch between a host crystal and a grown crystalline performance. overlayer; 0004 Planar microstrip high temperature Superconductor circuits Such as resonators, filters, and phase-shifting circuits 0010 FIG. 5 illustrates a high resolution Transmission are related to Mott transistors by benefiting from the use of Electron Micrograph of a structure including a monocrys a high quality epitaxial layer of a cuprate. Such planar talline accommodating buffer layer; microStrip high temperature Superconductor circuits are very 0011 FIG. 6 illustrates an X-ray diffraction spectrum of attractive for high performance, low noise, low insertion loSS a structure including a monocrystalline accommodating communication Systems, because they offer lower conductor buffer layer; losses compared to conventional conductors. Quality factors in the tens of thousands have been reported. Highly Selective 0012 FIG. 7 illustrates a high resolution Transmission bandpass filters with steep skirts, insertion loss under 0.3 dB, Electron Micrograph of a structure including an amorphous and 60 dB out of band rejection (at 5 MHz for a 1.8 GHz oxide layer; center frequency) have been demonstrated and are candidate 0013 FIG. 8 illustrates an X-ray diffraction spectrum of receive filters for base transceiver stations of future mobile a structure including an amorphous oxide layer; communication systems such as UMTS that will face strong interference problems. Combining high temperature Super 0014 FIGS. 9-12 illustrate schematically, in cross-sec conductors with tunable dielectrics (i.e., dielectrics with tion, the formation of a device Structure in accordance with field-dependent permittivity) Such as Strontium titanate another embodiment of the invention; (STO) or barium strontium titanate (BSTO) would allow 0.015 FIGS. 13 and 14 illustrate schematically, in cross high performance, tunable microwave devices. Section, device Structures that can be used in accordance 0005. A manufacturing challenge for high temperature with various embodiments of the invention; Superconductors is the need for an inexpensive, large format, 0016 FIGS. 15-19 include illustrations of cross-sectional Single crystal Substrate that is chemically compatible with Views of a portion of an integrated circuit that includes a US 2004/0069991 A1 Apr. 15, 2004 compound Semiconductor portion, a bipolar portion, and a and the growing accommodating buffer layer by the oxida MOS portion in accordance with what is shown herein; tion of substrate 22 during the growth of layer 24. The 0017 FIG. 20 shows a cross section diagram of the amorphous intermediate layer Serves to relieve Strain that structure of a Mott field effect transistor (FET), in accor might otherwise occur in the monocrystalline accommodat dance with one embodiment of the present invention. FIGS. ing buffer layer as a result of differences in the lattice 21-24 show examples of high temperature Superconducting constants of the substrate and the buffer layer. As used herein, lattice constant refers to the distance between atoms devices that benefit by the use of lanthanum strontium of a cell measured in the plane of the Surface. If Such Strain aluminum titanate under the YBCO or YPBCO layer, in is not relieved by the amorphous intermediate layer, the accordance with embodiments of the present invention. Strain may cause defects in the crystalline Structure of the 0.018 Skilled artisans will appreciate that elements in the accommodating buffer layer. Defects in the crystalline Struc figures are illustrated for simplicity and clarity and have not ture of the accommodating buffer layer, in turn, would make necessarily been drawn to Scale. For example, the dimen it difficult to achieve a high quality crystalline Structure in Sions of Some of the elements in the figures may be exag monocrystalline material layer 26 which may comprise a gerated relative to other elements to help to improve under Semiconductor material, a compound Semiconductor mate Standing of embodiments of the present invention. rial, or another type of material Such as a metal or a non-metal. DETAILED DESCRIPTION OF THE DRAWINGS 0022. Accommodating buffer layer 24 is preferably a 0.019 FIG. 1 illustrates schematically, in cross section, a monocrystalline oxide or nitride material Selected for its portion of a Semiconductor Structure 20 in accordance with crystalline compatibility with the underlying Substrate and an embodiment of the invention. Semiconductor structure 20 with the Overlying material layer. For example, the material includes a monocrystalline Substrate 22, accommodating could be an oxide or nitride having a lattice Structure closely buffer layer 24 comprising a monocrystalline material, and matched to the Substrate and to the Subsequently applied a monocrystalline material layer 26. In this context, the term monocrystalline material layer. Materials that are Suitable "monocrystalline' shall have the meaning commonly used for the accommodating buffer layer include metal oxides within the semiconductor industry. The term shall refer to Such as the alkaline earth metal titanates, alkaline earth materials that are a Single crystal or that are Substantially a metal Zirconates, alkaline earth metal hafnates, alkaline Single crystal and shall include those materials having a earth metal tantalates, alkaline earth metal ruthenates, alka relatively Small number of defects Such as dislocations and line earth metal niobates, alkaline earth metal Vanadates, the like as are commonly found in Substrates of Silicon or alkaline earth metal tin-based perovskites, lanthanum alu germanium or mixtures of Silicon and germanium and minate, lanthanum Scandium oxide, and other perovskite epitaxial layers of Such materials commonly found in the oxide materials, and gadolinium oxide. Additionally, various Semiconductor industry. nitrides Such as gallium nitride, aluminum nitride, and boron nitride may also be used for the accommodating buffer layer. 0020. In accordance with one embodiment of the inven Most of these materials are insulators, although Strontium tion, Structure 20 also includes an amorphous intermediate ruthenate, for example, is a conductor. Generally, these layer 28 positioned between Substrate 22 and accommodat ing buffer layer 24. Structure 20 may also include a template materials are metal oxides or metal nitrides, and more layer 30 between the accommodating buffer layer and particularly, these metal oxides or nitrides typically include monocrystalline material layer 26. AS will be explained at least two different metallic elements. In Some specific more fully below, the template layer helps to initiate the applications, the metal oxides or nitrides may include three growth of the monocrystalline material layer on the accom or more different metallic elements. modating buffer layer. The amorphous intermediate layer 0023. Amorphous interface layer 28 is preferably an helps to relieve the Strain in the accommodating buffer layer oxide formed by the oxidation of the surface of Substrate 22, and by doing So, aids in the growth of a high crystalline and more preferably is composed of a Silicon oxide. The quality accommodating buffer layer. thickness of layer 28 is sufficient to relieve strain attributed to mismatches between the lattice constants of Substrate 22 0021. Substrate 22, in accordance with an embodiment of and accommodating buffer layer 24. Typically, layer 28 has the invention, is a monocrystalline Semiconductor or com pound Semiconductor wafer, preferably of large diameter. a thickneSS in the range of approximately 0.5-5 nm. The wafer can be of, for example, a material from Group IV 0024. The material for monocrystalline material layer 26 of the periodic table. Examples of Group IV semiconductor can be selected, as desired, for a particular structure or materials include Silicon, germanium, mixed Silicon and application. For example, the monocrystalline material of germanium, mixed Silicon and carbon, mixed Silicon, ger layer 26 may comprise a compound Semiconductor which manium and carbon, and the like. Preferably substrate 22 is can be Selected, as needed for a particular Semiconductor a wafer containing Silicon or germanium, and most prefer structure, from any of the Group IIIA and VA elements ably is a high quality monocrystalline Silicon wafer as used (III-V semiconductor compounds), mixed III-V compounds, in the Semiconductor industry. Substrate 22 may also be, for Group II (A or B) and VIA elements (II-VI semiconductor example, Silicon-oninsulator (SOI), where a thin layer of compounds), mixed II-VI compounds, Group IV and VI Silicon is on top of an insulating material Such as Silicon elements (IV-VI semiconductor compounds), mixed IV-VI oxide or glass. Accommodating buffer layer 24 is preferably compounds, Group IV elements (Group IV Semiconductors), a monocrystalline oxide or nitride material epitaxially grown and mixed Group IV compounds. Examples include gallium on the underlying Substrate. In accordance with one embodi arsenide (GaAs), gallium indium arsenide (Ganas), gal ment of the invention, amorphous intermediate layer 28 is lium aluminum arsenide (GaAlAS), indium phosphide (InP), grown on Substrate 22 at the interface between Substrate 22 cadmium sulfide (CdS), cadmium mercury telluride (CdH US 2004/0069991 A1 Apr. 15, 2004 gTe), Zinc Selenide (ZnSe), Zinc sulfur Selenide (ZnSSe), phous oxide layer, may be better for growing monocrystal lead selenide (PbSe), lead telluride (PbTe), lead sulfide line material layers because it allows any Strain in layer 26 selenide (PbSSe), silicon (Si), germanium (Ge), silicon to relax. germanium (SiGe), Silicon germanium carbide (SiGeC), and 0030 Additional monocrystalline layer 38 may include the like. However, monocrystalline material layer 26 may any of the materials described throughout this application in also comprise other Semiconductor materials, metals, or connection with either of monocrystalline material layer 26 non-metal materials which are used in the formation of or additional buffer layer 32. For example, when monocrys Semiconductor Structures, devices and/or integrated circuits. talline material layer 26 comprises a Semiconductor or 0.025 Appropriate materials for template 30 are dis compound Semiconductor material, layer 38 may include cussed below. Suitable template materials chemically bond monocrystalline Group IV, monocrystalline compound to the Surface of the accommodating buffer layer 24 at Semiconductor materials, or other monocrystalline materials Selected Sites and provide Sites for the nucleation of the including oxides and nitrides. epitaxial growth of monocrystalline material layer 26. When 0031. In accordance with one embodiment of the present used, template layer 30 has a thickness ranging from about invention, additional monocrystalline layer 38 serves as an 1 to about 10 monolayers. anneal cap during layer 36 formation and as a template for 0.026 FIG. 2 illustrates, in cross section, a portion of a Subsequent monocrystalline layer 26 formation. Accord semiconductor structure 40 in accordance with a further ingly, layer 38 is preferably thick enough to provide a embodiment of the invention. Structure 40 is similar to the Suitable template for layer 26 growth (at least one mono previously described Semiconductor Structure 20, except that layer) and thin enough to allow layer 38 to form as a an additional buffer layer 32 is positioned between accom Substantially defect free monocrystalline material. modating buffer layer 24 and monocrystalline material layer 26. Specifically, the additional buffer layer 32 is positioned 0032. In accordance with another embodiment of the between template layer 30 and the overlying layer of monoc invention, additional monocrystalline layer 38 comprises rystalline material. The additional buffer layer, formed of a monocrystalline material (e.g., a material discussed above in Semiconductor or compound Semiconductor material when connection with monocrystalline layer 26) that is thick the monocrystalline material layer 26 comprises a Semicon enough to form devices within layer 38. In this case, a ductor or compound Semiconductor material, Serves to pro Semiconductor Structure in accordance with the present vide a lattice compensation when the lattice constant of the invention does not include monocrystalline material layer accommodating buffer layer cannot be adequately matched 26. In other words, the Semiconductor Structure in accor to the overlying monocrystalline Semiconductor or com dance with this embodiment only includes one monocrys pound Semiconductor material layer. talline layer disposed above amorphous oxide layer 36. 0.027 FIG. 3 schematically illustrates, in cross section, a 0033. The following non-limiting, illustrative examples portion of a Semiconductor Structure 34 in accordance with illustrate various combinations of materials useful in Struc another exemplary embodiment of the invention. Structure tures 20, 40, and 34 in accordance with various alternative 34 is similar to structure 20, except that structure 34 includes embodiments of the invention. These examples are merely an amorphous layer 36, rather than accommodating buffer illustrative, and it is not intended that the invention be layer 24 and amorphous interface layer 28, and an additional limited to these illustrative examples. monocrystalline layer 38. EXAMPLE 1. 0028 AS explained in greater detail below, amorphous layer 36 may be formed by first forming an accommodating 0034. In accordance with one embodiment of the inven buffer layer and an amorphous interface layer in a similar tion, monocrystalline Substrate 22 is a Silicon Substrate manner to that described above. Monocrystalline layer 38 is typically (100) oriented. The silicon Substrate can be, for then formed (by epitaxial growth) overlying the monocrys example, a Silicon Substrate as is commonly used in making talline accommodating buffer layer. The accommodating complementary metal oxide semiconductor (CMOS) inte buffer layer may then be optionally exposed to an anneal grated circuits having a diameter of about 200-300 mm. In process to convert at least a portion of the monocrystalline accordance with this embodiment of the invention, accom accommodating buffer layer to an amorphous layer. Amor modating buffer layer 24 is a monocrystalline layer of phous layer 36 formed in this manner comprises materials Sr BaTiO, where Z ranges from 0 to 1 and the amorphous from both the accommodating buffer and interface layers, intermediate layer is a layer of Silicon oxide (SiO) formed which amorphous layerS may or may not amalgamate. Thus, at the interface between the Silicon Substrate and the accom layer 36 may comprise one or two amorphous layers. modating buffer layer. The value of Z is selected to obtain Formation of amorphous layer 36 between substrate 22 and one or more lattice constants closely matched to correspond additional monocrystalline layer 26 (Subsequent to layer 38 ing lattice constants of the Subsequently formed layer 26. formation) relieves stresses between layers 22 and 38 and The lattice structure of the resulting crystalline oxide exhib provides Strain relief for Subsequent processing-e.g., its a Substantially 45 degree rotation with respect to the monocrystalline material layer 26 formation. Substrate Silicon lattice Structure. The accommodating buffer layer can have a thickness of about 2 to about 100 nanom 0029. The processes previously described above in con eters (nm) and preferably has a thickness of about 5 nm. In nection with FIGS. 1 and 2 are adequate for growing general, it is desired to have an accommodating buffer layer monocrystalline material layers over a monocrystalline Sub thick enough to isolate the monocrystalline material layer 26 Strate. However, the process described in connection with from the Substrate to obtain the desired electrical and optical FIG. 3, which includes transforming at least a portion of a properties. Layers thicker than 100 nm usually provide little monocrystalline accommodating buffer layer to an amor additional benefit while increasing cost unnecessarily; how US 2004/0069991 A1 Apr. 15, 2004

ever, thicker layers may be fabricated if needed. The amor a combination of gallium, aluminum or indium, Zirconium phous intermediate layer of Silicon oxide can have a thick arsenic (Zr-AS), Zirconium-phosphorus (Zr-P), hafnium ness of about 0.5-5 nm, and preferably a thickness of about arsenic (Hf As), hafnium-phosphorus (Hf P), strontium 1 to 2 nm. OXygen-arsenic (Sr-O-As), Strontium-oxygen 0035) In accordance with this embodiment of the inven phosphorus (Sr-O-P), barium-oxygen-arsenic (Ba-O- tion, monocrystalline material layer 26 is a compound AS), indium-strontium-oxygen (In-Sr-O), or barium Semiconductor layer of gallium arsenide (GaAs) or alumi oxygen-phosphorus (Ba-O-P), and preferably 0.5-2 num gallium arsenide (AlGaAs) having a thickness of about monolayers of one of these materials. By way of an example, 1 nm to about 100 micrometers (um) and preferably a for a barium Zirconate accommodating buffer layer, the thickness of about 0.5 um to 10 um. The thickness generally surface is terminated with 0.5-2 monolayers of zirconium depends on the application for which the layer is being followed by deposition of 0.5-2 monolayers of arsenic to prepared. To facilitate the epitaxial growth of the gallium form a Zr-AS template. A monocrystalline layer of the arsenide or aluminum gallium arsenide on the monocrystal compound Semiconductor material from the indium phos line oxide, a template layer is formed by depositing a phide System is then grown on the template layer. The Surfactant layer comprising one element of the compound resulting lattice Structure of the compound Semiconductor Semiconductor layer to react with the Surface of the oxide material exhibits a substantially 45 degree rotation with layer that has been previously capped. The capping layer is respect to the accommodating buffer layer lattice Structure preferably up to 3 monolayers of Sr-O, Ti-O, strontium and a lattice mismatch between the buffer layer and (100) or titanium. The template layer is preferably of Sr-Ga, oriented InP of less than 2.5%, and preferably less than Ti-Ga, Ti-AS, TI-O-AS, TI-O-Ga, Sr-O-AS, about 1.0%. Sr-Ga-O, Sr-Al-O, or Sr-Al. The thickness of the template layer is preferably about 0.5 to about 10 monolay EXAMPLE 3 ers, and preferably about 0.5-3 monolayers. By way of a 0039. In accordance with a further embodiment of the preferred example 0.5-3 monolayers of Ga deposited on a invention, a structure is provided that is Suitable for the capped Sr-O terminated surface have been illustrated to growth of an epitaxial film of a monocrystalline material Successfully grow GaAS layers. The resulting lattice Struc comprising a II-VI material overlying a Silicon Substrate. ture of the compound Semiconductor material exhibits a The substrate is preferably a silicon wafer as described Substantially 45 degree rotation with respect to the accom above. A Suitable accommodating buffer layer material is modating buffer layer lattice Structure. Sr BaTiO, where X ranges from 0 to 1, having a thick ness of about 2-100 nm and preferably a thickness of about EXAMPLE 2 3-10 nm. The lattice structure of the resulting crystalline 0036). In accordance with a further embodiment of the oxide exhibits a Substantially 45 degree rotation with respect invention, monocrystalline Substrate 22 is a Silicon Substrate to the Substrate silicon lattice structure. Where the monoc as described above. The accommodating buffer layer is a rystalline layer comprises a compound Semiconductor mate monocrystalline oxide of Strontium or barium Zirconate or rial, the II-VI compound Semiconductor material can be, for hafnate in a cubic or orthorhombic phase with an amorphous example, Zinc Selenide (ZnSe) or Zinc Sulfur Selenide intermediate layer of Silicon oxide formed at the interface (ZnSSe). A suitable template for this material system between the Silicon Substrate and the accommodating buffer includes 0.5-10 monolayers of zinc-oxygen (Zn-O) fol layer. The accommodating buffer layer can have a thickneSS lowed by 0.5-2 monolayers of an excess of zinc followed by of about 2-100 nm and preferably has a thickness of at least the Selenidation of Zinc on the Surface. Alternatively, a 4 nm to ensure adequate crystalline and Surface quality and template can be, for example, 0.5-10 monolayers of Stron is formed of monocrystalline SrZrO, BaZrO, SrHfO, tiumsulfur (Sr-S) followed by the ZnSSe. BaSnO, or BaFIfOs. For example, a monocrystalline oxide layer of BaZrO can grow at a temperature of about 700 EXAMPLE 4 degrees C. The lattice Structure of the resulting crystalline oxide exhibits a Substantially 45 degree rotation with respect 0040. This embodiment of the invention is an example of to the Substrate Silicon lattice Structure. structure 40 illustrated in FIG. 2. Substrate 22, accommo dating buffer layer 24, and monocrystalline material layer 26 0037. An accommodating buffer layer formed of these can be similar to those described in example 1. In addition, Zirconate or hafnate materials is Suitable for the growth of a an additional buffer layer 32 serves to alleviate any strains monocrystalline material layer which comprises compound that might result from a mismatch of the crystal lattice of the Semiconductor materials in an indium phosphide (InP) sys accommodating buffer layer and the lattice of the monoc tem. In this System, the compound Semiconductor material rystalline material. Buffer layer 32 can be a layer of germa can be, for example, indium phosphide (InP), indium gal nium or a GaAs, an aluminum gallium arsenide (AlGaAs), lium arsenide (InCaAS), aluminum indium arsenide, (All an indium gallium phosphide (InCaP), an aluminum gallium nAS), or aluminum gallium indium arsenic phosphide phosphide (AlGaP), an indium gallium arsenide (InGaAs), (AlGainASP), having a thickness of about 1.0 nm to 10 um. an aluminum indium phosphide (AlInP), a gallium arsenide A suitable template for this structure is about 0.5-10 mono phosphide (GaASP), or an indium gallium phosphide layers of one of a material M-N and a material M-O-N, (InGaP) Strain compensated Superlattice. In accordance with wherein M is selected from at least one of Zr, Hf, Ti, Sr., and one aspect of this embodiment, buffer layer 32 includes a Ba; and N is selected from at least one of AS, P. Ga, Al, and GaAsP, Superlattice, wherein the value of X ranges from In. 0 to 1. In accordance with another aspect, buffer layer 32 0.038 Alternatively, the template may comprise 0.5-10 includes an InGai-P Superlattice, wherein the value of y monolayers of gallium (Ga), aluminum (Al), indium (In), or ranges from 0 to 1. By varying the value of X or y, as the case US 2004/0069991 A1 Apr. 15, 2004

may be, the lattice constant is varied from bottom to top described above) and accommodating buffer layer materials across the Superlattice to create a Substantial (i.e., effective) (e.g., layer 24 materials as described above). For example, match between lattice constants of the underlying oxide and amorphous layer 36 may include a combination of SiO, and the overlying monocrystalline material which in this Sr BaTiO (where Z ranges from 0 to 1), which combine example is a compound Semiconductor material. The com or mix, at least partially, during an anneal process to form positions of other compound Semiconductor materials, Such amorphous oxide layer 36. as those listed above, may also be similarly varied to manipulate the lattice constant of layer 32 in a like manner. 0044) The thickness of amorphous layer 36 may vary The Superlattice can have a thickness of about 50-500 nm from application to application and may depend on Such and preferably has a thickness of about 100-200 nm. The factors as desired insulating properties of layer 36, type of Superlattice period can have a thickness of about 2-15 nm, monocrystalline material comprising layer 26, and the like. preferably 2-10 nm. The template for this structure can be In accordance with one exemplary aspect of the present the same as that described in example 1. Alternatively, buffer embodiment, layer 36 thickness is about 1 nm to about 100 layer 32 can be a layer of monocrystalline germanium nm, preferably about 1-10 nm, and more preferably about having a thickness of 1-50 nm and preferably having a 3-5 nm. thickness of about 2-20 nm. In using a germanium buffer 0045 Layer 38 comprises a monocrystalline material that layer, a template layer of either germanium-strontium (Ge can be grown epitaxially over a monocrystalline oxide Sr) or germanium-titanium (Ge-T) having a thickness of material Such as material used to form accommodating about 0.5-2 monolayers can be used as a nucleating Site for buffer layer 24. In accordance with one embodiment of the the Subsequent growth of the monocrystalline material layer invention, layer 38 includes the same materials as those which in this example is a compound Semiconductor mate comprising layer 26. For example, if layer 26 includes rial. The formation of the oxide layer is capped with either GaAS, layer 38 also includes GaAS. However, in accordance a 0.5-2 monolayer of strontium or a 0.5-2 monolayer of with other embodiments of the present invention, layer 38 titanium to act as a nucleating site for the Subsequent may include materials different from those used to form deposition of the monocrystalline germanium. The layer of layer 26. In accordance with one exemplary embodiment of Strontium or titanium provides a nucleating Site to which the the invention, layer 38 is about 1 nm to about 500 nm thick. first monolayer of germanium can bond. 0046 Referring again to FIGS. 1-3, Substrate 22 is a monocrystalline Substrate Such as a monocrystalline Silicon EXAMPLE 5 or gallium arsenide Substrate. The crystalline Structure of the 0041. This example also illustrates materials useful in a monocrystalline Substrate is characterized by a lattice con structure 40 as illustrated in FIG. 2. Substrate material 22, Stant and by a lattice orientation; In Similar manner, accom accommodating buffer layer 24, monocrystalline material modating buffer layer 24 is also a monocrystalline material layer 26 and template layer 30 can be the same as those and the lattice of that monocrystalline material is character described above in example 2. In addition, additional buffer ized by a lattice constant and a crystal orientation. The lattice layer 32 is inserted between the accommodating buffer layer constants of the accommodating buffer layer and the monoc and the overlying monocrystalline material layer. The buffer rystalline Substrate must be closely matched or, alterna layer, a further monocrystalline material which in this tively, must be Such that upon rotation of one crystal instance comprises a Semiconductor material, can be, for orientation with respect to the other crystal orientation, a example, a graded layer of indium gallium arsenide Substantial match in lattice constants is achieved. In this (InGaAs) or indium aluminum arsenide (InAlAS). In accor context the terms “substantially equal” and “substantially dance with one aspect of this embodiment, additional buffer matched” mean that there is sufficient similarity between the layer 32 includes InGaAS, in which the indium composition lattice constants to permit the growth of a high quality varies from 0% at the monocrystalline material layer 26 to crystalline layer on the underlying layer. about 50% at the accommodating buffer layer 24. The additional buffer layer 32 preferably has a thickness of about 0047 FIG. 4 illustrates graphically the relationship of the 10-30 nm. Varying the composition of the buffer layer from achievable thickness of a grown crystal layer of high crys GaAS to InCaAS serves to provide an effective (i.e. Substan talline quality as a function of the mismatch between the tial) lattice match between the underlying monocrystalline lattice constants of the host crystal and the grown crystal. oxide material and the overlying layer of monocrystalline Curve 42 illustrates the boundary of high crystalline quality material which in this example is a compound Semiconduc material. The area to the right of curve 42 represents layers tor material. Such a buffer layer is especially advantageous that have a large number of defects. With no lattice mis if there is a lattice mismatch between accommodating buffer match, it is theoretically possible to grow an infinitely thick, layer 24 and monocrystalline material layer 26. high quality epitaxial layer on the host crystal. AS the mismatch in lattice constants increases, the thickness of achievable, high quality crystalline layer decreaseS rapidly. EXAMPLE 6 AS a reference point, for example, if the lattice constants 0042. This example provides exemplary materials useful between the host crystal and the grown layer are mismatched in structure 34, as illustrated in FIG. 3. Substrate material by more than about 2%, monocrystalline epitaxial layers in 22, template layer 30, and monocrystalline material layer 26 excess of about 20 nm cannot be achieved. may be the same as those described above in connection 0048. In accordance with one embodiment of the inven with example 1. tion, Substrate 22 is typically a (100) oriented monocrystal 0.043 Amorphous layer 36 is an amorphous oxide layer line Silicon wafer and accommodating buffer layer 24 is a which is suitably formed of a combination of amorphous layer of strontium barium titanate. Substantial (i.e., effec intermediate layer materials (e.g., layer 28 materials as tive) matching of lattice constants between these two mate US 2004/0069991 A1 Apr. 15, 2004

rials is achieved by rotating the crystal orientation of the highly reactive and readily forms a native oxide. The term titanate material by approximately 45 with respect to the "bare’ is intended to encompass Such a native oxide. A thin crystal orientation of the silicon Substrate wafer. The inclu Silicon oxide may also be intentionally grown on the Semi Sion in the Structure of amorphous interface layer 28, a conductor Substrate, although Such a grown oxide is not Silicon oxide layer in this example, if it is of Sufficient essential to the proceSS in accordance with the invention. In thickness, Serves to reduce Strain in the titanate monocryS order to epitaxially grow a monocrystalline oxide layer talline layer that might result from any mismatch in the overlying the monocrystalline Substrate, the native oxide lattice constants of the host Silicon wafer and the grown layer must first be removed to expose the crystalline Struc titanate layer. As a result, in accordance with an embodiment ture of the underlying Substrate. The following proceSS is of the invention, a high quality, thick, monocrystalline preferably carried out by molecular beam epitaxy (MBE), titanate layer is achievable. although other epitaxial processes may also be used in 0049 Still referring to FIGS. 1-3, layer 26 is a layer of accordance with the present invention. The native oxide can epitaxially grown monocrystalline material and that crystal be removed by first thermally depositing a thin layer (pref line material is also characterized by a crystal lattice con erably 1-3 monolayers) of Strontium, barium, a combination Stant and a crystal orientation. In accordance with one of Strontium and barium, or other alkaline earth metals or embodiment of the invention, the lattice constant of layer 26 combinations of alkaline earth metals in an MBE apparatus. differs from the lattice constant of Substrate 22. To achieve In the case where Strontium is used, the Substrate is then high crystalline quality in this epitaxially grown monocryS heated to a temperature above 720° C. as measured by an talline layer, the accommodating buffer layer must be of high optical pyrometer to cause the Strontium to react with the crystalline quality. In addition, in order to achieve high native Silicon oxide layer. The Strontium Serves to reduce the crystalline quality in layer 26, Substantial matching between Silicon oxide to leave a Silicon oxide-free Surface. The the crystal lattice constant of the host crystal, in this case, the resultant Surface may exhibit an ordered (2x1) structure. If monocrystalline accommodating buffer layer, and the grown an ordered (2x1) structure has not been achieved at this stage crystal is desired. With properly selected materials this of the process, the Structure may be exposed to additional Substantial matching of lattice constants is achieved as a strontium until an ordered (2x1) structure is obtained. The result of rotation of the crystal orientation of the grown ordered (2x1) structure forms a template for the ordered crystal with respect to the orientation of the host crystal. For growth of an overlying layer of a monocrystalline oxide. The example, if the grown crystal is gallium arsenide, aluminum template provides the necessary chemical and physical prop gallium arsenide, Zinc Selenide, or Zinc Sulfur Selenide and erties to nucleate the crystalline growth of an overlying the accommodating buffer layer is monocrystalline Sr Bal layer. xTiO, Substantial matching of crystal lattice constants of the 0051. It is understood that precise measurement of actual two materials is achieved, wherein the crystal orientation of temperatures in MBE equipment, as well as other processing the grown layer is rotated by substantially 45 with respect equipment, is difficult, and is commonly accomplished by to the orientation of the host monocrystalline oxide. Simi the use of a pyrometer or by means of a thermocouple placed larly, if the host material is a strontium or barium Zirconate in close proximity to the Substrate. Calibrations can be or a strontium or barium hafnate or barium tin oxide and the performed to correlate the pyrometer temperature reading to compound Semiconductor layer is indium phosphide or that of the thermocouple. However, neither temperature gallium indium arsenide or aluminum indium arsenide, reading is necessarily a precise indication of actual Substrate Substantial matching of crystal lattice constants can be temperature. Furthermore, variations may exist when mea achieved by rotating the orientation of the grown crystal Suring temperatures from one MBE system to another MBE layer by Substantially 45 with respect to the host oxide System. For the purpose of this description, typical pyrom crystal. In Some instances, a crystalline Semiconductor eter temperatures will be used, and it should be understood buffer layer 32 between the host oxide and the grown that variations may exist in practice due to these measure monocrystalline material layer 26 can be used to reduce ment difficulties. Strain in the grown monocrystalline material layer that might result from Small differences in lattice constants. Better 0052. In accordance with an alternate embodiment of the crystalline quality in the grown monocrystalline material invention, the native Silicon oxide can be converted and the layer can thereby be achieved. Substrate Surface can be prepared for the growth of a monocrystalline oxide layer by depositing an alkaline earth 0050. The following example illustrates a process, in metal oxide, Such as Strontium oxide, Strontium barium accordance with one embodiment of the invention, for oxide, or barium oxide, onto the Substrate surface by MBE fabricating a Semiconductor Structure Such as the Structures at a low temperature and by Subsequently heating the depicted in FIGS. 1-3. The process starts by providing a structure to a temperature of above 720° C. At this tempera monocrystalline Semiconductor Substrate comprising Silicon ture a Solid State reaction takes place between the Strontium or germanium. In accordance with a preferred embodiment oxide and the native Silicon oxide causing the reduction of of the invention, the Semiconductor Substrate is a Silicon the native silicon oxide and leaving an ordered (2x1) struc wafer having a (100) orientation. The substrate is oriented ture on the Substrate Surface. If an ordered (2x1) structure on axis or, at most, about 6 off axis, and preferably has not been achieved at this stage of the process, the misoriented 1-3 off axis toward the 110 direction. At least Structure may be exposed to additional Strontium until an a portion of the Semiconductor Substrate has a bare Surface, ordered (2x1) structure is obtained. Again, this forms a although other portions of the Substrate, as described below, template for the Subsequent growth of an ordered monoc may encompass other Structures. The term "bare’ in this rystalline oxide layer. context means that the Surface in the portion of the Substrate has been cleaned to remove any oxides, contaminants, or 0053. Following the removal of the silicon oxide from the other foreign material. AS is well known, bare Silicon is Surface of the Substrate, in accordance with one embodiment US 2004/0069991 A1 Apr. 15, 2004

of the invention, the Substrate is cooled to a temperature in accommodating buffer layer 24. The peaks in the Spectrum the range of about 200-600° C., preferably 350°-550° C., indicate that both the accommodating buffer layer 24 and and a layer of Strontium titanate is grown on the template GaAS compound Semiconductor layer 26 are Single crystal layer by molecular beam epitaxy. The MBE process is and (100) oriented. initiated by opening Shutters in the MBE apparatus to expose Strontium, titanium and oxygen Sources. The ratio of Stron 0057 The structure illustrated in FIG. 2 can be formed tium and titanium is approximately 1:1. The partial pressure by the process discussed above with the addition of an of oxygen is initially Set at a minimum value to grow additional buffer layer deposition step. The additional buffer Stoichiometric Strontium titanate at a growth rate of about layer 32 is formed overlying the template layer 30 before the 0.1-0.8 nm per minute, preferably 0.3-0.5 nm per minute. deposition of the monocrystalline material layer 26. If the After initiating growth of the Strontium titanate, the partial additional buffer layer 32 is a monocrystalline material preSSure of oxygen is increased above the initial minimum comprising a compound Semiconductor Superlattice, Such a value. The stoichiometry of the titanium can be controlled Superlattice can be deposited, by MBE for example, on the during growth by monitoring RHEED patterns and adjusting template 30 described above. If instead, the additional buffer the titanium flux. The overpreSSure of oxygen causes the layer is a monocrystalline material layer comprising a layer growth of an amorphous Silicon oxide layer at the interface of germanium, the process above is modified to cap the first between the underlying Substrate and the Strontium titanate buffer layer of strontium titanate with a final template layer layer. This step may be applied either during or after the of either Strontium or titanium and then by depositing growth of the strontium titanate layer. The growth of the germanium to react with the Strontium or titanium. The amorphous Silicon oxide layer results from the diffusion of germanium buffer layer can then be deposited directly on oxygen through the Strontium titanate layer to the interface this template. where the oxygen reacts with Silicon at the Surface of the 0.058 Structure 34, illustrated in FIG. 3, may be formed underlying Substrate. The Strontium titanate grows as an by growing an accommodating buffer layer 24, forming an ordered (100) monocrystal with the (100) crystalline orien amorphous oxide layer 28 over Substrate 22, and growing tation rotated by 45 with respect to the underlying substrate. semiconductor layer 38 over the accommodating buffer Strain that otherwise might exist in the Strontium titanate layer, as described above. The accommodating buffer layer layer because of the Small mismatch in lattice constant 24 and the amorphous oxide layer 28 are then exposed to a between the Silicon Substrate and the growing crystal is higher temperature anneal proceSS Sufficient to change the relieved in the amorphous Silicon oxide intermediate layer. crystalline Structure of the accommodating buffer layer from 0054. After the strontium titanate layer has been grown to monocrystalline to amorphous, thereby forming an amor the desired thickness, the monocrystalline Strontium titanate phous layer Such that the combination of the amorphous is capped by a template layer that is conducive to the oxide layer and the now amorphous accommodating buffer Subsequent growth of an epitaxial layer of a desired monoc layer form a single amorphous oxide layer 36. Layer 26 is rystalline material. For example, for the Subsequent growth then Subsequently grown over layer 38. Alternatively, the of a monocrystalline compound Semiconductor material anneal proceSS may be carried out Subsequent to growth of layer of gallium arsenide, the MBE growth of the strontium layer 26. titanate monocrystalline layer can be capped by terminating 0059. In accordance with one aspect of this embodiment, the growth with up to 2 monolayers of titanium, up to 2 layer 36 is formed by exposing SubStrate 22, the accommo monolayers of Strontium, up to 2 monolayers of titanium dating buffer layer 24, the amorphous oxide layer 28, and oxygen or with up to 2 monolayers of Strontium-oxygen. monocrystalline layer 38 to a rapid thermal anneal process Following the formation of this capping layer, arsenic is with a peak temperature of about 700° C. to about 1000° C. deposited to form a T-AS bond, a Ti-O-As bond or a (actual temperature) and a process time of about 5 Seconds Sr-O-AS bond. Any of these form an appropriate tem to about 20 minutes. However, other suitable anneal pro plate for deposition and formation of a gallium arsenide ceSSes may be employed to convert the accommodating monocrystalline layer. Following the formation of the tem buffer layer to an amorphous layer in accordance with the plate, gallium is Subsequently introduced to the reaction present invention. For example, laser annealing, electron with the arsenic and gallium arsenide forms. Alternatively, beam annealing, or “conventional’ thermal annealing pro 0.5-3 monolayers of gallium can be deposited on the capping cesses (in the proper environment) may be used to form layer to form a Sr-O-Gabond, or a Ti-O-Gabond, and layer 36. When conventional thermal annealing is employed arsenic is Subsequently introduced with the gallium to form to form layer 36, an overpreSSure of one or more constituents the GaAs. of layer 38 may be required to prevent degradation of layer 0055 FIG. 5 is a high resolution Transmission Electron 38 during the anneal process. For example, when layer 38 Micrograph (TEM) of semiconductor material manufactured includes GaAS, the anneal environment preferably includes in accordance with one embodiment of the present inven an overpreSSure of arsenic to mitigate degradation of layer tion. Single crystal SrTiO accommodating buffer layer 24 38. Alternately, an appropriate anneal cap, Such as Silicon was grown epitaxially on Silicon Substrate 22. During this nitride, may be utilized to prevent the degradation of layer growth process, amorphous interfacial layer 28 is formed, 38 during the anneal process with the anneal cap being which relieves Strain due to lattice mismatch. GaAS com removed after the annealing process. pound Semiconductor layer 26 was then grown epitaxially using template layer 30. 0060. As noted above, layer 38 of structure 34 may include any materials suitable for either of layers 32 or 26. 0056 FIG. 6 illustrates an X-ray diffraction spectrum Accordingly, any deposition or growth methods described in taken on a structure including GaAS monocrystalline layer connection with either layer 32 or 26 may be employed to 26 comprising GaAS grown on Silicon Substrate 22 using deposit layer 38. US 2004/0069991 A1 Apr. 15, 2004

0061 FIG. 7 is a high resolution TEM of semiconductor to form a template for the deposition of a monocrystalline material manufactured in accordance with the embodiment material layer comprising compound SemiconductorS Such of the invention illustrated in FIG. 3. In accordance with this as indium gallium arsenide, indium aluminum arsenide, or embodiment, a single crystal SrTiO accommodating buffer indium phosphide. layer was grown epitaxially on Silicon SubStrate 22. During this growth process, an amorphous interfacial layer forms as 0065 Single crystal silicon has 4-fold symmetry. That is, described above. Next, additional monocrystalline layer 38 its structure is essentially the same as it is rotated in 90 comprising a compound Semiconductor layer of GaAS is degree steps in the plane of the (100) Surface. Likewise, formed above the accommodating buffer layer and the Strontium titanate and many other oxides have a 4-fold accommodating buffer layer is exposed to an anneal proceSS Symmetry. On the other hand, GaAS and related compound to form amorphous oxide layer 36. Semiconductors have a 2-fold Symmetry. The 0 degree and 0.062 FIG. 8 illustrates an X-ray diffraction spectrum 180 degree rotations of the 2-foldsymmetry are not the same taken on a structure including additional monocrystalline as the 90 degree and 270 degree rotations of the 4-fold layer 38 comprising a GaAS compound Semiconductor layer Symmetry. If GaAS is nucleated upon Strontium titanate at and amorphous oxide layer 36 formed on Silicon Substrate multiple locations on the Surface, two different phases are 22. The peaks in the Spectrum indicate that GaAS compound produced. AS the material continues to grow, the two phases semiconductor layer 38 is single crystal and (100) oriented meet and form anti-phase domains. These anti-phase and the lack of peaks around 40 to 50 degrees indicates that domains can have an adverse effect upon certain types of layer 36 is amorphous. devices, particularly minority carrier devices like lasers and light emitting diodes. 0.063. The process described above illustrates a process for forming a Semiconductor Structure including a Silicon 0066. In accordance with one embodiment of the present Substrate, an overlying oxide layer, and a monocrystalline invention, in order to provide for the formation of high material layer comprising a gallium arsenide compound quality monocrystalline compound Semiconductor material, Semiconductor layer by the process of molecular beam the Starting Substrate is off-cut or misoriented from the ideal epitaxy. The proceSS can also be carried out by the proceSS (100) orientation by 0.5 to 6 degrees in any direction, and of chemical vapor deposition (CVD), metal organic chemi preferably 1 to 2 degrees toward the 110 direction. This cal vapor deposition (MOCVD), migration enhanced epit offcut provides for StepS or terraces on the Silicon Surface axy (MEE), atomic layer epitaxy (ALE), physical vapor and it is believed that these substantially reduce the number deposition (PVD), chemical solution deposition (CSD), of anti-phase domains in the compound Semiconductor pulsed laser deposition (PLD), or the like. Further, by a material, in comparison to a substrate having an offcut near Similar process, other monocrystalline accommodating 0 degrees or off cuts larger than 6 degrees. The greater the buffer layerS Such as alkaline earth metal titanates, Zircon amount of off-cut, the closer the StepS and the Smaller the ates, hafnates, tantalates, Vanadates, ruthenates, niobates, terrace widths become. At very Small angles, nucleation alkaline earth metal tin-based perovskites, lanthanum alu occurs at other than the Step edges, decreasing the size of minate, lanthanum Scandium oxide, and gadolinium oxide Single phase domains. At high angles, Smaller terraces can also be grown. Further, by a similar process Such as decrease the size of Single phase domains. Growing a high MBE, other monocrystalline material layers comprising quality oxide, Such as Strontium titanate, upon a Silicon other III-V, II-VI, and IV-VI monocrystalline compound Surface causes Surface features to be replicated on the Semiconductors, Semiconductors, metals and non-metals can Surface of the oxide. The Step and terrace Surface features are be deposited overlying the monocrystalline oxide accom replicated on the Surface of the oxide, thus preserving modating buffer layer. directional cues for Subsequent growth of compound Semi conductor material. Because the formation of the amorphous 0064. Each of the variations of monocrystalline material interface layer occurs after the nucleation of the oxide has layer and monocrystalline oxide accommodating buffer begun, the formation of the amorphous interface layer does layer uses an appropriate template for initiating the growth of the monocrystalline material layer. For example, if the not disturb the step structure of the oxide. accommodating buffer layer is an alkaline earth metal Zir 0067. After the growth of an appropriate accommodating conate, the oxide can be capped by a thin layer of Zirconium. buffer layer, Such as Strontium titanate or other materials as The deposition of zirconium can be followed by the depo described earlier, a template layer is used to promote the Sition of arsenic or phosphorus to react with the Zirconium proper nucleation of compound Semiconductor material. In as a precursor to depositing indium gallium arsenide, indium accordance with one embodiment, the Strontium titanate is aluminum arsenide, or indium phosphide, respectively. capped with up to 2 monolayers of SrO. The template layer Similarly, if the monocrystalline oxide accommodating 30 for the nucleation of GaAs is formed by raising the buffer layer is an alkaline earth metal hafnate, the oxide layer substrate to a temperature in the range of 540 to 630 degrees can be capped by a thin layer of hafnium. The deposition of and exposing the Surface to gallium. The amount of gallium hafnium is followed by the deposition of arsenic or phos exposure is preferably in the range of 0.5 to 5 monolayers. phorous to react with the hafnium as a precursor to the It is understood that the exposure to gallium does not imply growth of an indium gallium arsenide, indium aluminum that all of the material will actually adhere to the surface. arsenide, or indium phosphide layer, respectively. In a Not wishing to be bound by theory, it is believed that the Similar manner, Strontium titanate can be capped with a layer gallium atoms adhere more readily at the exposed Step edges of Strontium or Strontium and oxygen, and barium titanate of the oxide Surface. Thus, Subsequent growth of gallium can be capped with a layer of barium or barium and oxygen. arsenide preferentially forms along the Step edges and prefer Each of these depositions can be followed by the deposition an initial alignment in a direction parallel to the Step edge, of arsenic or phosphorus to react with the capping material thus forming predominantly Single domain material. Other US 2004/0069991 A1 Apr. 15, 2004

materials besides gallium may also be utilized in a similar ment of the invention is illustrated in cross-section. This fashion, Such as aluminum and indium or a combination embodiment utilizes the formation of a compliant Substrate thereof. which relies on the epitaxial growth of Single crystal oxides 0068. After the deposition of the template, a compound on Silicon followed by the epitaxial growth of Single crystal Semiconductor material Such as gallium arsenide may be Silicon onto the oxide. deposited. The arsenic Source Shutter is preferably opened 0072 An accommodating buffer layer 74 such as a prior to opening the Shutter of the gallium Source. Small monocrystalline oxide layer is first grown on a Substrate amounts of other elements may also be deposited Simulta layer 72, Such as Silicon, with an amorphous interface layer neously to aid nucleation of the compound Semiconductor 78 as illustrated in FIG. 9. Monocrystalline oxide layer 74 material layer. For example, aluminum may be deposited to may be comprised of any of those materials previously form AlGaAs. As noted above, layer 38, illustrated in FIG. discussed with reference to layer 24 in FIGS. 1 and 2, while 3, comprises a monocrystalline material that can be grown amorphous interface layer 78 is preferably comprised of any epitaxially over a monocrystalline oxide material, Such as of those materials previously described with reference to the material used to form accommodating buffer layer 24. In layer 28 illustrated in FIGS. 1 and 2. Substrate 72, although accordance with one embodiment of the invention, layer 38 preferably Silicon, may also comprise any of those materials includes materials different from those used to form layer previously described with reference to substrate 22 in FIGS. 26. For example, in a preferred embodiment, layer 38 1-3. includes AlGaAS, which is deposited as a nucleation layer at a relatively slow growth rate. For example, the growth rate 0073. Next, a silicon layer 81 is deposited over monoc of layer 38 of AlGaAs can be approximately 0.10-0.5 tim/hr. rystalline oxide layer 74 via MBE, CVD, MOCVD, MEE, In this case, growth can be initiated by first depositing AS on ALE, PVD, CSD, PLD, or the like as illustrated in FIG. 10 template layer 30, followed by deposition of aluminum and with a thickness of a few tens of nanometers but preferably gallium. Deposition of the nucleation layer generally is with a thickness of about 5 nm. Monocrystalline oxide layer accomplished at about 300-600 C., and preferably 400 74 preferably has a thickness of about 2 to 10 nm. 500 C. In accordance with one exemplary embodiment of 0074 Rapid thermal annealing is then conducted in the the invention, the nucleation layer is about 1 nm to about 500 presence of a carbon Source Such as acetylene or methane, nm thick, and preferably 5 nm to about 50 nm. In this case, for example at a temperature within a range of about 800° C. the aluminum Source Shutter is preferably opened prior to to 1000 C. to form capping layer 82 and silicate amorphous opening the gallium Source Shutter. The amount of alumi layer 86. However, other suitable carbon sources may be num is preferably in the range from 0 to 50% (expressed as used as long as the rapid thermal annealing step functions to a percentage of the aluminum content in the AlGaAs layer), amorphize the monocrystalline oxide layer 74 into a Silicate and is most preferably about 15-25%. Other materials, such amorphous layer 86 and carbonize the top silicon layer 81 to as InGaAS, could also be used in a similar fashion. Once the form capping layer 82 which in this example would be a growth of compound Semiconductor material is initiated, silicon carbide (SiC) layer as illustrated in FIG. 11. The other mixtures of compound Semiconductor materials can be formation of amorphous layer 86 is similar to the formation grown with various compositions and various thicknesses as of layer 36 illustrated in FIG. 3 and may comprise any of required for various applications. For example, a thicker those materials described with reference to layer 36 in FIG. layer of GaAS may be grown on top of the AlGaAS layer to 3 but the preferable material will be dependent upon the provide a Semi-insulating buffer layer prior to the formation capping layer 82 used for silicon layer 81. of device layers. 0075 Finally, as shown in FIG. 12, a compound semi 0069. The quality of the compound semiconductor mate conductor layer 96, Such as gallium nitride (GaN), is grown rial can be improved by including one or more in-Situ over the SiC surface by way of MBE, CVD, MOCVD, MEE, anneals at various points during the growth. The growth is ALE, PVD, CSD, PLD, or the like to form a high quality interrupted, and the Substrate is raised to a temperature of compound Semiconductor material for device formation. between 500-650° C., and preferably about 550°-600° C. More specifically, the deposition of GaN and GaN based The anneal time depends on the temperature Selected, but for systems such as GalnN and AlGaN will result in the for an anneal of about 550° C., the length of time is preferably mation of dislocation nets confined at the Silicon/amorphous about 15 minutes. The anneal can be performed at any point region. The resulting nitride containing compound Semicon during the deposition of the compound Semiconductor mate ductor material may comprise elements from groups III, IV rial, but preferably is performed when there is 50 nm to 500 and V of the periodic table and is defect free. nm of compound Semiconductor material deposited. Addi 0076 Although GaN has been grown on SiC substrate in tional anneals may also be done, depending on the total the past, this embodiment of the invention possesses a one thickness of material being deposited. Step formation of the compliant Substrate containing a SiC 0070. In accordance with one embodiment, monocrystal top Surface and an amorphous layer on a Si Surface. More line material layer 26 is GaAS. Layer 26 may be deposited Specifically, this embodiment of the invention uses an inter on layer 24 at various rates, which may vary from applica mediate Single crystal oxide layer that is amorphized to form tion to application; however in a preferred embodiment, the a Silicate layer which adsorbs the Strain between the layers. growth rate of layer 26 is about 0.2 to 1.0 lim/hr. The Moreover, unlike past use of a SiC Substrate, this embodi temperature at which layer 26 is grown may also vary, but ment of the invention is not limited by wafer size which is in one embodiment, layer 26 is grown at a temperature of usually less than 50 mm in diameter for prior art SiC about 300-600° C. and preferably about 350°-500° C. Substrates. 0071 Turning now to FIGS. 9-12, the formation of a 0077. The monolithic integration of nitride containing device Structure in accordance with Still another embodi Semiconductor compounds containing group III-V nitrides US 2004/0069991 A1 Apr. 15, 2004 and Silicon devices can be used for high temperature and two regions, 53 and 57. A Semiconductor component gen high power RF applications and optoelectronics. GaN SyS erally indicated by the dashed line 56 is formed, at least tems have particular use in the photonic industry for the partially, in region 53. Semiconductor component 56 can be blue/green and UV light Sources and detection. High bright a resistor, a capacitor, an active electrical component Such as neSS light emitting diodes (LEDs) and lasers may also be a diode or a transistor, an optoelectric component Such as a formed within the GaN system. photo detector, or an integrated circuit Such as a CMOS integrated circuit. For example, Semiconductor component 0078 Clearly, those embodiments specifically describing 56 can be a CMOS integrated circuit configured to perform Structures having compound Semiconductor portions and digital signal processing or another function for which Group IV Semiconductor portions are meant to illustrate Silicon integrated circuits are well Suited. The electrical embodiments of the present invention and not limit the Semiconductor component in region 53 can be formed by present invention. There are a multiplicity of other combi conventional Semiconductor processing as well known and nations and other embodiments of the present invention. For widely practiced in the Semiconductor industry. A layer of example, the present invention includes Structures and meth insulating material 59 such as a layer of silicon dioxide or ods for fabricating material layers which form Semiconduc the like may overlie Semiconductor component 56. tor Structures, devices and integrated circuits including other layerS Such as metal and non-metal layers. More Specifically, 0082 Insulating material 59 and any other layers that the invention includes Structures and methods for forming a may have been formed or deposited during the processing of compliant substrate which is used in the fabrication of semiconductor component 56 in region 53 are removed from Semiconductor Structures, devices and integrated circuits the surface of region 57 to provide a bare silicon surface in and the material layerS Suitable for fabricating those Struc that region. AS is well known, bare Silicon Surfaces are tures, devices, and integrated circuits. By using embodi highly reactive and a native Silicon oxide layer can quickly ments of the present invention, it is now Simpler to integrate form on the bare surface. A layer (preferably 1-3 monolay devices that include monocrystalline layers comprising ers) of strontium or strontium and oxygen is deposited onto Semiconductor and compound Semiconductor materials, as the native oxide layer on the surface of region 57 and is well as other material layers that are used to form those reacted with the oxidized Surface to form a first template devices, with other components that work better or are easily layer (not shown). In accordance with one embodiment, a and/or inexpensively formed within Semiconductor or com monocrystalline oxide layer is formed overlying the tem pound Semiconductor materials. This allows a device to be plate layer by a process of molecular beam epitaxy. Reac shrunk, the manufacturing costs to decrease, and yield and tants including Strontium, titanium and oxygen are deposited reliability to increase. onto the template layer to form the monocrystalline oxide layer. Initially during the deposition the partial pressure of 0079. In accordance with one embodiment of this inven oxygen is kept near the minimum necessary to fully react tion, a monocrystalline Semiconductor or compound Semi with the Strontium and titanium to form a monocrystalline conductor wafer can be used in forming monocrystalline Strontium titanate layer. The partial pressure of oxygen is material layers over the wafer. In this manner, the wafer is then increased to provide an overpreSSure of oxygen and to essentially a “handle' wafer used during the fabrication of allow oxygen to diffuse through the growing monocrystal Semiconductor electrical components within a monocrystal line oxide layer. The oxygen diffusing through the Strontium line layer overlying the wafer. Therefore, electrical compo titanate reacts with silicon at the surface of region 57 to form nents can be formed within Semiconductor materials over a an amorphous layer of Silicon oxide 62 on Second region 57 wafer of at least approximately 200 millimeters in diameter and at the interface between silicon Substrate 52 and the and possibly at least approximately 300 millimeters. monocrystalline oxide layer 65. Layers 65 and 62 may be 0080. By the use of this type of substrate, the relatively Subject to an annealing process as described above in inexpensive “handle' wafer overcomes the fragile nature of connection with FIG. 3 to form a single amorphous accom waferS fabricated of monocrystalline compound Semicon modating layer. ductor or other monocrystalline material by placing the 0083. In accordance with an embodiment, the step of materials over a relatively more durable and easy to fabri depositing the monocrystalline oxide layer 65 is terminated cate base Substrate. Therefore, an integrated circuit can be by depositing a capping layer 64, which can be up to 3 formed Such that all electrical components, and particularly monolayers of titanium, Strontium, Strontium and oxygen, or all active electronic devices, can be formed within or using titanium and oxygen. A layer 66 of a monocrystalline the monocrystalline material layer even though the Substrate compound Semiconductor material is then deposited over itself may include a different monocrystalline Semiconduc lying capping layer 64 by a process of molecular beam tor material. Fabrication costs for compound Semiconductor epitaxy. The deposition of layer 66 is initiated by depositing devices and other devices employing non-Silicon monocryS a layer of gallium onto capping layer 64. This initial Step is talline materials should decrease because larger Substrates followed by depositing arsenic and gallium to form monoc can be processed more economically and more readily rystalline gallium arsenide 66. Alternatively, barium or a compared to the relatively Smaller and more fragile Sub mix of barium and strontium can be Substituted for strontium Strates (e.g., conventional compound semiconductor in the above example. wafers). 0084. In accordance with a further embodiment, a semi 0.081 FIG. 13 illustrates schematically, in cross section, conductor component, generally indicated by a dashed line a device structure 50 in accordance with a further embodi 68 is formed in compound semiconductor layer 66. Semi ment. Device structure 50 includes a monocrystalline semi conductor component 68 can be formed by processing Steps conductor Substrate 52, preferably a monocrystalline Silicon conventionally used in the fabrication of gallium arsenide or wafer. Monocrystalline semiconductor substrate 52 includes other III-V compound Semiconductor material devices. US 2004/0069991 A1 Apr. 15, 2004

Semiconductor component 68 can be any active or passive structures or composite integrated circuits like 50 or 71. In component, and preferably is a Semiconductor laser, light particular, the illustrative composite Semiconductor Struc emitting diode, photodetector, heterojunction bipolar tran ture or integrated circuit 103 shown in FIGS. 15-19 includes sistor (HBT), high frequency MESFET, pseudomorphic a compound Semiconductor portion 1022, a bipolar portion high electron mobility transistor (PHEMT), or other com 1024, and a MOS portion 1026. In FIG. 15, a p-type doped, ponent that utilizes and takes advantage of the physical monocrystalline silicon Substrate 110 is provided having a properties of compound Semiconductor materials. A metallic compound Semiconductor portion 1022, a bipolar portion conductor schematically indicated by the line 70 can be 1024, and a MOS portion 1026. Within bipolar portion 1024, formed to electrically couple device 68 and device 56, thus the monocrystalline silicon substrate 110 is doped to form an implementing an integrated device that includes at least one N' buried region 1102. A lightly p-type doped epitaxial component formed in Silicon Substrate 52 and one device monocrystalline silicon layer 1104 is then formed over the formed in monocrystalline compound Semiconductor mate buried region 1102 and the substrate 110. A doping step is rial layer 66. Although illustrative structure 50 has been then performed to create a lightly n-type doped drift region described as a structure formed on a Silicon Substrate 52 and 1117 above the N' buried region 1102. The doping step having a strontium (or barium) titanate layer 65 and a converts the dopant type of the lightly p-type epitaxial layer gallium arsenide layer 66, Similar devices can be fabricated within a section of the bipolar region 1024 to a lightly n-type using other Substrates, monocrystalline oxide layers and monocrystalline Silicon region. A field isolation region 1106 other compound Semiconductor layerS as described else is then formed between and around the bipolar portion 1024 where in this disclosure. and the MOS portion 1026. A gate dielectric layer 1110 is 0085 FIG. 14 illustrates a semiconductor structure 71 in formed over a portion of the epitaxial layer 1104 within accordance with a further embodiment. Structure 71 MOS portion 1026, and the gate electrode 1112 is then includes a monocrystalline Semiconductor Substrate 73 Such formed over the gate dielectric layer 1110. Sidewall spacers as a monocrystalline Silicon wafer that includes a region 75 1115 are formed along vertical sides of the gate electrode and a region 76. A Semiconductor component Schematically 1112 and gate dielectric layer 1110. illustrated by the dashed line 79 is formed in region 75 using 0088 A p-type dopant is introduced into the drift region conventional Silicon device processing techniques com 1117 to form an active or intrinsic base region 1114. An monly used in the Semiconductor industry. Using proceSS n-type, deep collector region 1108 is then formed within the StepS Similar to those described above, a monocrystalline bipolar portion 1024 to allow electrical connection to the oxide layer 80 and an intermediate amorphous silicon oxide buried region 1102. Selective n-type doping is performed to layer 83 are formed overlying region 76 of substrate 73. A form N' doped regions 1116 and the emitter region 1120. N* template layer 84 and Subsequently a monocrystalline Semi doped regions 1116 are formed within layer 1104 along conductor layer 87 are formed overlying monocrystalline adjacent Sides of the gate electrode 1112 and are Source, oxide layer 80. In accordance with a further embodiment, an drain, or source/drain regions for the MOS transistor. The N' additional monocrystalline oxide layer 88 is formed over doped regions 1116 and emitter region 1120 have a doping lying layer 87 by process steps similar to those used to form concentration of at least 1E19 atoms per cubic centimeter to layer 80, and an additional monocrystalline Semiconductor allow ohmic contacts to be formed. A p-type doped region layer 90 is formed overlying monocrystalline oxide layer 88 is formed to create the inactive or extrinsic base region 1118 by process steps similar to those used to form layer 87. In which is a P" doped region (doping concentration of at least accordance with one embodiment, at least one of layers 87 1E19 atoms per cubic centimeter). and 90 is formed from a compound semiconductor material. LayerS 80 and 83 may be Subject to an annealing proceSS as 0089. In the embodiment described, several processing steps have been performed but are not illustrated or further described above in connection with FIG. 3 to form a single described, Such as the formation of well regions, threshold amorphous accommodating layer. adjusting implants, channel punchthrough prevention 0.086 A semiconductor component generally indicated implants, field punchthrough prevention implants, as well as by a dashed line 92 is formed at least partially in monoc a variety of masking layers. The formation of the device up rystalline semiconductor layer 87. In accordance with one to this point in the proceSS is performed using conventional embodiment, Semiconductor component 92 may include a steps. As illustrated, a standard N-channel MOS transistor field effect transistor having a gate dielectric formed, in part, has been formed within the MOS region 1026, and a vertical by monocrystalline oxide layer 88. In addition, monocrys NPN bipolar transistor has been formed within the bipolar talline semiconductor layer 90 can be used to implement the portion 1024. Although illustrated with a NPN bipolar gate electrode of that field effect transistor. In accordance transistor and an N-channel MOS transistor, device struc with one embodiment, monocrystalline Semiconductor layer tures and circuits in accordance with various embodiments 87 is formed from a group III-V compound and semicon may additionally or alternatively include other electronic ductor component 92 is a radio frequency amplifier that devices formed using the Silicon Substrate. As of this point, takes advantage of the high mobility characteristic of group no circuitry has been formed within the compound Semi III-V component materials. In accordance with yet a further conductor portion 1022. embodiment, an electrical interconnection Schematically 0090. After the silicon devices are formed in regions illustrated by the line 94 electrically interconnects compo 1024 and 1026, a protective layer 1122 is formed overlying nent 79 and component 92. Structure 71 thus integrates devices in regions 1024 and 1026 to protect devices in components that take advantage of the unique properties of regions 1024 and 1026 from potential damage resulting from the two monocrystalline Semiconductor materials. device formation in region 1022. Layer 1122 may be formed 0.087 Attention is now directed to a method for forming of, for example, an insulating material Such as Silicon oxide exemplary portions of illustrative composite Semiconductor or Silicon nitride. US 2004/0069991 A1 Apr. 15, 2004

0.091 All of the layers that have been formed during the 0094. After at least a portion of layer 132 is formed in processing of the bipolar and MOS portions of the integrated region 1022, layers 122 and 124 may be subject to an circuit, except for epitaxial layer 1104 but including protec annealing process as described above in connection with tive layer 1122, are now removed from the surface of FIG. 3 to form a single amorphous accommodating layer. If compound Semiconductor portion 1022. A bare Silicon Sur only a portion of layer 132 is formed prior to the anneal face is thus provided in the manner set forth above for the process, the remaining portion may be deposited onto Struc Subsequent processing of this portion, for example in the ture 103 prior to further processing. manner set forth below. 0095 At this point in time, sections of the compound Semiconductor layer 132 and the accommodating buffer 0092 An accommodating buffer layer 124 is then formed layer 124 (or of the amorphous accommodating layer if the over the Substrate 110 as illustrated in FIG. 16. The accom annealing process described above has been carried out) are modating buffer layer will form as a monocrystalline layer removed from portions overlying the bipolar portion 1024 over the properly prepared (i.e., having the appropriate and the MOS portion 1026 as shown in FIG. 18. After the template layer) bare silicon Surface in portion 1022. The Section of the compound Semiconductor layer and the portion of layer 124 that forms over portions 1024 and 1026, accommodating buffer layer 124 are removed, an insulating however, may be polycrystalline or amorphous because it is layer 142 is formed over protective layer 1122. The insu formed over a material that is not monocrystalline, and lating layer 142 can include a number of materials Such as therefore, does not nucleate monocrystalline growth. The oxides, nitrides, oxynitrides, low-k dielectrics, or the like. accommodating buffer layer 124 typically is a monocrystal AS used herein, low-k is a material having a dielectric line metal oxide or nitride layer and typically has a thickneSS constant no higher than approximately 3.5. After the insu in a range of approximately 2-100 nanometers. In one lating layer 142 has been deposited, it is then polished or particular embodiment, the accommodating buffer layer is etched to remove portions of the insulating layer 142 that approximately 3-10 nm thick. During the formation of the overlie monocrystalline compound Semiconductor layer accommodating buffer layer, an amorphous intermediate 132. layer 122 is formed along the uppermost Silicon Surfaces of 0096. A transistor 144 is then formed within the monoc the integrated circuit 103. This amorphous intermediate rystalline compound Semiconductor portion 1022. A gate layer 122 typically includes an oxide of Silicon and has a electrode 148 is then formed on the monocrystalline com thickneSS and range of approximately 0.5-5 nm. In one pound Semiconductor layer 132. Doped regions 146 are then particular embodiment, the thickneSS is 1-2 nm. Following formed within the monocrystalline compound Semiconduc the formation of the accommodating buffer layer 124 and the tor layer 132. In this embodiment, the transistor 144 is a amorphous intermediate layer 122, a capping layer of up to metal-semiconductor field-effect transistor (MESFET). If 3 monolayers of titanium, Strontium, titanium oxygen, or the MESFET is an n-type MESFET, the doped regions 146 strontium oxygen is formed. Template layer 125 is then and at least a portion of monocrystalline compound Semi formed by depositing 0.5-10 monolayers of gallium, indium, conductor layer 132 are also n-type doped. If a p-type aluminum, or a combination thereof and has a thickneSS in MESFET were to be formed, then the doped regions 146 and a range of approximately one half to ten monolayers. In one at least a portion of monocrystalline compound Semicon particular embodiment, the template includes gallium, tita ductor layer 132 would have just the opposite doping type. nium-arsenic, titanium-oxygen-arsenic, Strontium-oxygen The heavier doped (N) regions 146 allow ohmic contacts to arsenic, or other Similar materials as previously described be made to the monocrystalline compound Semiconductor with respect to FIGS. 1-5. A monocrystalline compound layer 132. At this point in time, the active devices within the Semiconductor layer 132 is then epitaxially grown overlying integrated circuit have been formed. Although not illustrated the monocrystalline portion of accommodating buffer layer in the drawing figures, additional processing StepS. Such as 124 as shown in FIG. 17. The portion of layer 132 that is formation of well regions, threshold adjusting implants, grown over portions of layer 124 that are not monocrystal channel punchthrough prevention implants, field punch line may be polycrystalline or amorphous. The compound through prevention implants, and the like may be performed Semiconductor layer can be formed by a number of methods in accordance with the present invention. This particular and typically includes a material Such as gallium arsenide, embodiment includes an n-type MESFET, a vertical NPN aluminum gallium arsenide, indium phosphide, or other bipolar transistor, and a planar n-channel MOS transistor. compound Semiconductor materials as previously men Many other types of transistors, including P-channel MOS tioned. The thickness of the layer is in a range of approxi transistors, p-type Vertical bipolar transistors, p-type MES mately 1-5,000 nm, and more preferably 100-2000 nm. FETs, and combinations of Vertical and planar transistors, Furthermore, additional monocrystalline layerS may be can be used. Also, other electrical components, Such as formed above layer 132. resistors, capacitors, diodes, and the like, may be formed in 0093. In the particular embodiment of FIG. 17, each of one or more of the portions 1022, 1024, and 1026. the elements within the template layer are also present in the 0097 Processing continues to form a substantially com accommodating buffer layer 124, the monocrystalline com pleted integrated circuit 103 as illustrated in FIG. 19. An pound semiconductor material 132, or both. Therefore, the insulating layer 152 is formed over the substrate 110. The delineation between the template layer 125 and its two insulating layer 152 may include an etch-Stop or polish-stop immediately adjacent layerS disappears during processing. region that is not illustrated in FIG. 19. A second insulating Therefore, when a transmission electron microscopy (TEM) layer 154 is then formed over the first insulating layer 152. photograph is taken, an interface between the accommodat Portions of layers 154, 152, 142,124, and 1122 are removed ing buffer layer 124 and the monocrystalline compound to define contact openings where the devices are to be Semiconductor layer 132 is seen. interconnected. Interconnect trenches are formed within US 2004/0069991 A1 Apr. 15, 2004

insulating layer 154 to provide the lateral connections trode 208. Because of the nature of the Mott metal-insulator between the contacts. As illustrated in FIG. 19, interconnect transition, the channel is generally formed along the top 1562 connects a source or drain region of the n-type MES interface of MIT channel layer 214 (i.e., the interface FET within portion 1022 to the deep collector region 1108 between layerS 214 and 212). Generally, the carrier concen of the NPN transistor within the bipolar portion 1024. The tration and mobility of MIT channel layer 214 is modulated emitter region 1120 of the NPN transistor is connected to by application of a gate bias. Carriers are drawn into the one of the doped regions 1116 of the n-channel MOS channel electroStatically from the Source and drain elec transistor within the MOS portion 1026. The other doped trodes by application of gate bias, forming a thin conductive region 1116 is electrically connected to other portions of the sheet at the interface between the channel material and the integrated circuit that are not shown. Similar electrical gate oxide. That is, a metal-insulator transition is not connections are also formed to couple regions 1118 and 1112 induced chemically (by introduction of dopants); rather, an to other regions of the integrated circuit. insulating material is provided and carriers required to make the material conducting are introduced through application 0098. A passivation layer 156 is formed over the inter connects 1562, 1564, and 1566 and insulating layer 154. of a gate bias. As a result, this class of devices does not have Other electrical connections are made to the transistors as an intrinsic Scaling limit and can therefore operate at illustrated as well as to other electrical or electronic com extremely short (e.g., about 10 nm) channel lengths. ponents within the integrated circuit 103 but are not illus 0102 Processing starts with preparation of Substrate 202. trated in the figures. Further, additional insulating layerS and AS mentioned above, Substrate 202 is a monocrystalline interconnects may be formed as necessary to form the proper Semiconductor or compound Semiconductor wafer, prefer interconnections between the various components within the ably of large diameter. The wafer may comprise, for integrated circuit 103. example, a material from Group IV of the periodic table, and preferably a material from Group IVB. Examples of Group 0099 AS can be seen from the previous embodiment, IV Semiconductor materials include Silicon, germanium, active devices for both compound Semiconductor and Group mixed Silicon and germanium, mixed Silicon and carbon, IV Semiconductor materials can be integrated into a single mixed Silicon, germanium and carbon, and the like. Prefer integrated circuit. Because there is Some difficulty in incor ably Substrate 22 is a wafer containing Silicon or germanium, porating both bipolar transistors and MOS transistors within and most preferably is a high quality monocrystalline (100) a same integrated circuit, it may be possible to move Some Silicon wafer as traditionally used in the Semiconductor of the components within bipolar portion 1024 into the industry. compound semiconductor portion 1022 or the MOS portion 1026. Therefore, the requirement of special fabricating steps 0103). After preparation of substrate 202, amorphous Solely used for making a bipolar transistor can be eliminated. interface layer 204 is suitably formed as described above in Therefore, there would only be a compound Semiconductor conjunction with FIGS. 1-3. In accordance with one embodi portion and a MOS portion to the integrated circuit. ment of the invention, amorphous interface layer 204 is grown on Substrate 202 at the interface between substrate 0100 For devices that benefit from the use of perovskite 202 and the growing accommodating buffer layer 206 by the cuprates such as YBa-Cu-O,(YBCO) and Y oxidation of substrate 202 during the growth of layer 206. As x)Prs Ba-Cu-O,(YPBCO)-for example, Mott transistors described in detail above, the amorphous interface layer 204 and planar microStrip high temperature Superconductor cir Serves to relieve Strain that might otherwise occur in the cuits-a unique combination of material layerS fabricated monocrystalline accommodating buffer layer 206 as a result using the methods described above provides exceptional of differences in the lattice constants of the Substrate 202 and performance. In particular, lanthanum Strontium aluminum the buffer layer 206. tantalate (LSAT), which is a solid solution of 30 mole % LaAIO, and 70 mole % SrAITaO, is closely lattice matched 0104 Meanwhile, accommodating buffer layer 206 is to YBCO, YPBCO, and silicon, and therefore is an excellent Suitably formed on amorphous interface layer 204 using any material to use between a Silicon Substrate and a layer of of the methods described in detail above. In accordance with YBCO or YPBCO. Referring to FIG. 20, a cross section one embodiment, accommodating buffer layer 206 com diagram of the structure of a Mott field effect transistor prises lanthanum Strontium aluminum tantalate (LSAT), (FET) is shown in accordance with one embodiment of the which is a solid solution of 30 mole % La AlO and 70 mole present invention. In the illustrated embodiment, the FET % SrAlTaC). Accommodation layer 206 can be formed by 200 comprises a metal-insulator transition (MIT) channel a variety of growth techniques such as MBE, PLD, CSD, layer 214 provided between a source electrode 210 and a CVD, PVD and the like, or a combination of these deposi drain electrode 208, all of which are formed on a stack tion methods, can also be used In an alternative embodi comprising accommodating buffer layer 206, amorphous ment, accommodating buffer layer 206 comprises two lay interface layer 204, and monocrystalline substrate 202. A ers; a layer of strontium titanate (STO) or barium strontium gate electrode 220 is provided on gate insulator 212, and titanate (BSTO) grown on the substrate 202 and a layer of Suitable Source and drain contacts 216 and 218 are formed LSAT grown on the layer of STO or BSTO. to provide electrical connections to Source electrode 210 and drain electrode 208 respectively. 0105. After accommodating buffer layer 206 is formed, Source and drain electrodes 210 and 208 as well as MIT 0101. In general, FET 200 operates similar to conven channel layer 214 are formed using any convenient method. tional FETs. When a suitable gate bias is applied to gate In one embodiment, the conductive material for Source and electrode 220 (e.g., above a characteristic threshold voltage), drain electrodes 210 and 208 is deposited on accommodat a channel is formed within MIT channel layer 214, allowing ing buffer layer 206, followed by patterning of the metalli current flow between Source electrode 210 and drain elec zation and then deposition of MIT channel layer 214 on the US 2004/0069991 A1 Apr. 15, 2004

exposed surface 215. Alternatively, MIT channel layer 214 is shown, in accordance with one embodiment of the present may be deposited first, followed by patterning of this layer invention. A layer of LSAT 2120 is grown over a monoc and deposition of the conductive material for Source elec rystalline silicon Substrate 2105, with an amorphous layer trode 210 and drain electrode 208. 2110 grown between the silicon substrate 2105 and the LSAT layer 2120, or between the silicon Substrate 2105 and 0106 Electrodes 210 and 208 may be manufactured an optional layer of STO or BSTO 2115 in the manner using a variety of conductive materials. Suitable conductors described above for the Mott transistor 200. A layer of include, for example, metals (platinum, aluminum, gold, YBCO or YPBCO is grown on the LSAT layer 2120, etc.), polysilicon, and conductive oxides. In one embodi providing a Superconducting ground plane 2125. A Second ment, electrodes 210 and 208 comprise platinum. layer of LSAT 2130 is grown over the Superconducting 0107 MIT channel layer 214 comprises, in general, any ground plane 2125, and a second layer of YBCO or YPBCO material that undergoes a Mott metal/insulator transition at is grown on the second layer of LSAT 2130 in a desired room temperature in response to an electric field. In accor transmission line pattern. Because the lattice of the YBCO dance with one embodiment, MIT channel layer 214 com or YPBCO layers 2125,2135 is very closely matched to the prises a perovskite oxide which undergoes a Mott MIT adjacent LSAT layers 2120 and 2130, a high quality monoc transition, for example, various cuprates Such as rystalline form of the YBCO or YPBCO is provided that has YBa-Cu-O, (YBCO), Y, Pr, Ba-Cu-O, (YPBCO, the benefits cited above, for the reasons given. 0melting point 0115 Referring to FIG. 23, a cross section diagram of a and therefore does not twin, and it offers much closer lattice Superconducting coplanar waveguide Structure 2300 is match (0.3%) for YBCO, thereby avoiding significant stress shown, in accordance with one embodiment of the present and allowing Superior crystal quality. Moreover, LSAT's invention. The layer 2110, optional layer 2115, and layer effective lattice mismatching at a 45 degree rotation with 2120 are grown in the same manner as for the Supercon reference to a 001 silicon Substrate is only 0.5%. Finally, ducting microstrip transmission line structure 2100. Strips of LSAT has only 1% lattice mismatching to STO or BSTO. YBCO or YPBCO material that form ground lines 2305, This excellent lattice matching prevents dislocations and 2310 and a strip of YBCO or YPBCO that forms a center provides a very high quality monocrystalline Structure of the conductor 2315 are grown over the LSAT layer 2120 in a YBCO or YPBCO. suitable pattern, or the YBCO or YPBCO is grown as a 0111. After MIT channel layer 214 and electrodes 210, continuous layer and then patterned by a known technique, 208 have been formed, gate insulator 212 is deposited. In Such as etching, resulting in a functional Superconducting one embodiment, gate insulator 212 comprises a high-k coplanar waveguide device having very high quality crys dielectric material Such as BSTO, BTO, or STO formed talline YBCO or YPBCO for the reasons given above. under growth conditions similar to those described above in connection layer 206. The thickness of gate insulator 212 0116 Referring to FIG. 24, a cross section diagram of a may be Selected in accordance with design parameters. In Josephson junction Structure 2400 is shown, in accordance one embodiment, gate insulator 212 is approximately with one embodiment of the present invention. The layer 20-400 nm in thickness. After the preceding Steps, gate 2110, optional layer 2115, and layer 2120 are grown in the insulator 212 is patterned and etched to form vias in which Same manner as for the Superconducting microStrip trans Source contact 216 and drain contact 218 are formed. After mission line structure 2100. Two patterned layers of YBCO or YPBCO material 2405,2415 are formed with a layer of a Suitable planarization Step, gate electrode 220 is formed on LSAT material 2410 between them, forming a Josephson gate insulator 212. Gate electrode 220 is preferably formed junction. Suitable other aspects of a functional electronic above and aligned with MIT channel layer 214. Structure are formed, Such as electrodes, resulting in a 0112 FIGS. 21-24 show examples of high temperature Josephson junction device having very high quality crystal Superconducting devices that benefit by the use of LSAT line YBCO or YPBCO for the reasons given above. under the YBCO or YPBCO layer. 0.117) It will be appreciated that by using the techniques 0113 Referring to FIG. 21, a cross section diagram of a described herein with reference to FIGS. 1-19, a pattern of Superconducting microStrip transmission line Structure 2100 compound Semiconductor material can be grown co-later US 2004/0069991 A1 Apr. 15, 2004 ally with a pattern of YBCO or YPBCO to form a patterned 6. The perovskite cuprate electronic device Structure layer from which an integrated circuit that includes any according to claim 1, wherein the buffer layer further combination of the electronic devices described with refer comprises a layer of one of Strontium titanate or barium ence to FIGS. 15-24. Alternatively, compound semiconduc Strontium titanate formed between the monocrystalline sili tor materials can be grown on LSAT and STO layers that are con substrate and the layer of monocrystalline LSAT. grown over patterned YBCO and/or YPBCO layers, thereby 7. The perovskite cuprate electronic device Structure forming an integrated circuit Structure that can include any according to claim 1, further comprising a monocrystalline compound Semiconductor layer formed on one of the buffer combination of electronic devices described herein. Such layer and the monocrystalline perovskite cuprate layer. integrated circuit Structures can be advantageously used in a 8. The perovskite cuprate electronic device Structure wide variety of electronic equipment where high perfor according to claim 1, comprising at least one of a Mott mance electronic devices are needed. transistor, a Superconducting microStrip transmission line, a 0118. In the foregoing specification, the invention has tunable Superconducting microStrip transmission line, a been described with reference to specific embodiments. Superconducting coplanar waveguide, and a Josephsonjunc However, one of ordinary skill in the art appreciates that tion. various modifications and changes can be made without 9. An integrated circuit comprising the electronic device departing from the Scope of the present invention as Set forth Structure according to claim 1. in the claims below. Accordingly, the Specification and 10. An electronic equipment comprising the integrated figures are to be regarded in an illustrative rather than a circuit according to claim 9. restrictive Sense, and all Such modifications are intended to 11. A process for fabricating a perovskite cuprate elec be included within the Scope of present invention. tronic device Structure comprising: depositing a buffer layer comprising monocrystalline lan 0119 Benefits, other advantages, and solutions to prob thanum strontium aluminum tantalate (LSAT) overly lems have been described above with regard to specific ing a monocrystalline Silicon Substrate; embodiments. However, the benefits, advantages, Solutions to problems, and any element(s) that may cause any benefit, forming an amorphous oxide interface layer containing at advantage, or Solution to occur or become more pronounced least Silicon and oxygen at an interface between the are not to be construed as a critical, required, or essential buffer layer and the monocrystalline Silicon Substrate; features or elements of any or all the claims. AS used herein, and the terms “comprises,”“comprising,” or any other variation epitaxially forming a layer of monocrystalline perovskite thereof, are intended to cover a non-exclusive inclusion, cuprate on the monocrystalline LSAT. Such that a process, method, article, or apparatus that com 12. The process for fabricating a perovskite cuprate prises a list of elements does not include only those elements electronic device Structure according to claim 11, wherein but may include other elements not expressly listed or the monocrystalline LSAT is a solid solution of 30 mole % inherent to Such process, method, article, or apparatus. LaAlO and 70 mole % SrAlTaC). 13. The process for fabricating a perovskite cuprate What is claimed is electronic device Structure according to claim 11, wherein 1. A perovskite cuprate electronic device Structure, com the monocrystalline perovskite cuprate is one of prising: YBa-Cu-O, (YBCO) and Y, Pr, Ba-Cu-O, (YPBCO, 0