High Performance Cnt Based Nanoelectronic Circuits An

International Journal of Advanced Research in Engineering and Technology (IJARET) Volume 11, Issue 8, August 2020, pp. 110-121, Article ID: IJARET_11_08_012 Available online at http://iaeme.com/Home/issue/IJARET?Volume=11&Issue=8 ISSN Print: 0976-6480 and ISSN Online: 0976-6499 DOI: 10.34218/IJARET.11.8.2020.012

HIGH PERFORMANCE CNT BASED NANOELECTRONIC CIRCUITS: AN ANALYSIS

S. Bashiruddin Horned Coot Research in Aesthetic Decors Pvt Ltd, New Delhi, India

ABSTRACT Carbon Nano Tubes (CNTs) with their unique electronic and geometric features have emerged as candidates in next generation high-performance nano-electronics application. CNTs have played a significant role in overcoming the challenges of scaling process of traditional silicon/conventional MOS based devices and therefore, carbon nanotube field effect transistor (CNTFET) based circuit development has been boosted in recent years. The present review encompasses inquisitive assessment of CNTs and its application in designing of CNTFET based circuits in nano-electronics. Recently reported CNTFET based nanoelectronic circuits like three stage operational amplifiers (OP AMP), novel operational trans-conductance amplifier (OTA), universal logic circuits, tristate buffer, Cascode Operational Transconductance Amplifiers (COTA), folded cascode operational transconductance amplifiers (FC- OTAs), Ternary Full Adder Cell and pure CNT based multistage operational amplifier, as well as improvement in their performance parameters (DC gain, output resistance, slew rate, average power, speed and power consumption) as compared to respective MOS based circuits have been extensively reviewed. In order to harness the high quality intrinsic features of CNTs further investigations of nanotube-based- electronics are anticipated and considered as future perspective beyond silicon-based- electronics. Key words: CNTFET, CNT, OTA, OP AMP, CMOS. Cite this Article: S. Bashiruddin, High Performance CNT based Nanoelectronic Circuits: An Analysis, International Journal of Advanced Research in Engineering and Technology, 11(8), 2020, pp. 110-121. http://iaeme.com/Home/issue/IJARET?Volume=11&Issue=8

1. INTRODUCTION In recent years, MOS technology has withered from several microns to nanometer scale following the scaling trend demonstrated by Moore’s law [1, 2]. In the discipline of Nano electronics, with decrease in channel length of device at level of sub-10 nm era, short channel effects, and direct tunnelling between source and drain pose various challenges which deteriorate the device reliability [3]. As the MOSFET scaling looming its supreme limit hence there is an immediate quest for highly efficient devices and materials to outperform Silicon MOS in order to keep the miniaturization enhancement in trend [4]. Recently, the researchers

http://iaeme.com/Home/journal/IJARET 110 [email protected] High Performance CNT based Nanoelectronic Circuits: An Analysis interest is to cease the opportunity of superior properties of CNT based FETs to replace Silicon FETs, much progress has been made in recent years showing that CNT FETs can outperform silicon MOSFETs in many ways. CNTFETs have the potential to spur all the limits of silicon FETs such as exponential rise of leakage currents in scaled devices [5]. CNTFETs and MOSFETs are different at the level of channel material, In CNTFETs formation of channel is realized by using semiconducting SWCNT whereas in MOSFETS silicon is used as channel material between the drain and source [6, 7]. The schematic view of CNTFET is shown in (Fig. 1). The source and drain are the heavily doped regions while CNT channel is undoped. The number of CNTs in the channel is an important parameter, as it has a significant impact on the overall performance of the device, particularly on the drive current. The working of a CNTFET is similar to the conventional MOSFET. The gate voltage turns the device ON and OFF and is capacitive coupled with the channel. The CV/I performance of an intrinsic CNTFET was noticed to be 13 times better as compared to conventional MOSFET [8]. CNTFET which uses CNT as a channel material enables high mobility, large transconductance and very low power consumption due to the presence of 1D ballistic electron transport i.e. no electron scattering in CNTs [8, 9]. Precisely, even at very high frequencies good operation can be obtained with CNTs [10, 11].

Figure 1 Schematic of a CNTFET

2. ASSESSMENT OF CNTS Carbon Nano Tubes (CNTs) a fascinating new class of materials was first observed by Endo in (1975) and later discovered by Sumio Iijima of NEC, Japan in 1991 [12]. CNTs can be visualized as Graphene sheet rolled up in the shape of a cylinder of few nanometre in diameter [12, 13]. Diameters of CNTs typically ranges from 1 to 100 nm and lengths can be of millimetres, or even centimetres range [13, 14]. Graphene is a single atomic layer of hexagonal arrangement of carbon atoms, known as honeycomb lattice [15]. CNTs are categorized in two types: Single-walled carbon nanotubes (SWCNTs) and Multiple-walled carbon nanotubes (MWCNTs). SWCNT - Structure and morphology: The SWCNTs are generally narrower than the multi- walled tubes, with diameters typically in the range 1-2 nm, and tend to be curved rather than straight (Fig. 2). SWCNTs usually contain only 10 atoms around the circumference and the thickness of the tube is only one-atom thick [16]. In general, SWCNTs electronic properties vary from metallic to semiconducting [16, 17] while MWCNTs are observed as metallic [15].

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Figure 2 Single Wall CNT MWCNT- Structure and morphology: MWCNT is restricted to nanostructures with outer diameter of less than 15 nm [16]. In MWCNT, many tubes are arranged in a coaxial fashion to form concentric cylinders (Fig. 3) [18]. Each nanotube is a single molecule composed of millions of atoms and the length of this molecule can be tens of micrometres long with diameters as small as 0.7 nm [16, 19].

Figure 3 Multi wall CNT A substantial amount of work has been done in the past decade to unravel the electrical, mechanical and chemical properties of CNTs. Usually Nanotubes have huge aspect ratio (length-to-diameter ratio) of about 1000, subsequently considered as nearly one-dimensional configuration [20, 21]. The electrical properties of CNTs depend on their geometrical structure which is determined by chiral vector [22, 23]. CNTs may behave as metallic or semi-conducting depending on their indices (n, m) and bandgaps that scale inversely with their diameter [15, 16]. Based on chirality vector and chiral angle (θ), SWCNTs can be of 3 types, i.e. arm chair type if (n = m, φ = 0°), zig zag type if (n, m = 0, φ = 30°), and chiral type if (n ≠ m ≠0 and θ lies between 0o and 30o) [24, 25]. particularly, Armchair (n=m) are always metallic whereas zigzag and chiral can be either metallic or semiconducting depends on value of n, m if n = m or n – m = 3i (where i is an integer), the nanotube shows metallic behaviour otherwise semiconducting [6, 23]. It has been shown experimentally that CNT conducts with no electron scattering also there is no heat dissipation owing to their ballistic electron transport and Quasi 1-D nature [15, 26]. The inimitable characteristics of CNTs

http://iaeme.com/Home/journal/IJARET 112 [email protected] High Performance CNT based Nanoelectronic Circuits: An Analysis keep attracting the researches to explore and use them in the field of electronics, biomedical, materials science, energy management and many other fields [15, 23]. Semiconducting CNTs find their use in the formation of CNTFET [9], transistors [23, 27, 28], sensors [29], diodes [30, 31]

3. CNT-BASED INVESTIGATION COMPENDIA A simulation and designed study was undertaken by Loan et al in order to propose a CNT based novel operational trans-conductance amplifier (OTA) which encashes the advantages associated with CNTFET. In this investigation multifactorial performance of two types of newly designed CNT based OTAs were compared with that of CMOS based OTA. N CNT- PMOS-OTA and P CNT-NMOS-OTA transistors were used to realise the OTA. CNT based OTAs were observed to be with augmented performance as compared to conventional CMOS-OTA. Increase in DC gain by 44.4% and 69.3 % while decrease in average power by 24.18 % and 14.98 % in PCNT-NMOS OTA and NCNT-PMOS OTA respectively as compared to those in CMOS-OTA in this investigation. The circuit diagram of proposed PMOS NCNT OTA is shown in (Fig. 4) [32].

Figure 4 PMOS-NCNT-OTA [32] A simulation and designed study was accomplished by Shakir et al in order to propose a CNTFET based tristate buffer (Fig.5a) and a 2X1 Multiplexer using the proposed tristate buffer. It was investigated that the edges of the waveform were sharper, also it contains less spikes and glitches (Fig. 5b). Thus, output was more similar to input wave form. The proposed tristate buffer was also found faster and less power consuming as compared to convention MOS tristate Buffer [33].

Figure 5a- CNTFET based Tristate Buffer (for active low)

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Figure 5b- CNTFET Based Tristate Buffer Output A simulation and designed study was demonstrated by Loan et al in order to propose a CNTFET based cascode operational transconductance amplifiers (COTAs). In this investigation of two types of newly designed CNT based COTAs multifactorial performance were compared with that of conventional CMOS OTA. NCNT-PMOS COTA and the other PCNT-NMOS COTA were designed based on 45 nm technology node using HSPICE. Considerable augmentation in parameters like DC gain, bandwidth, power reduction, output resistance is achieved in the proposed COTAs. Further, it has been found that optimizing the number of CNTs in the CNTFETs used for designing COTAs will further optimize the performance of COTAs. The circuit of PCNT-NMOS COTA is shown (in Fig. 6a) while the DC gain variation with number of PCNT-NMOS COTA is shown in (Fig. 6b) [24].

Figure 6a- PMOS-NCNT-COTA

Figure 6b- Variation of DC Gain with N

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A simulation and designed study was Carried out by Nizamuddin et al in order to propose a CNTFET based three stage operational amplifiers (OP AMP). The proposed hybrid structures use conventional MOSFETS and CNTFETs. The circuit diagram of NCNT-PMOS- OP-AMP based on CNTFET is shown in (Fig. 7). It has been observed that in the NCNT- PMOS OP AMP, DC gain has improved by 17 %, Output resistance reduced by 90 % and the power consumption is 40 % less as compared to the conventional CMOS-OP AMP [9].

Figure 7- 3 Stage NCNTFET - PMOS OP-AMP A Design and Comparative analysis was commenced by Loan et al in order to propose a high performance CNTFET based operational transconductance amplifiers (OTAs). In this investigation three types of CNT-based OTAs were designed, including a pure CNTFET- based OTA and two hybrid technology-based OTA. CNT-based OTAs, particularly pure CNT-OTA were observed to be with augmented performance as compared to CMOS-OTA. The circuit diagram of Pure CNTFET based OTA is shown in (Fig. 8a) while change in DC gain with number of CNTS is shown in (Fig. 8b). Significant increase in DC gain, Slew Rate and Output resistance but very small average power consumption in Pure CNT based OTA were reported in this investigation as compared to those in CMOS-OTAs. Moreover, with the improvement of CMRR and PSRR in pure CNTOTA. It was also noticed that pure CNT-OTA was highly stable, having largest gain and Phase margins [8].

Figure 8 a- Pure CNTFET OTA Figure 8b- Number of CNTs vs DC Gain

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A Simulation and design study was undertaken by Nizamuddin et al [34] in order to propose Ambipolar CNTFET based universal logic gates. MOS based NAND gate circuit is shown in (Fig. 9 a) while One of the Proposed CNTFET based NAND gate circuit diagram is shown in (Fig. 9b). Investigated results shows that ambipolar CNTFET based Devices uses less number of transistors to give the same results as compared to MOS based transistors. Hence same chip area may accommodate more number of logic gates which can be used to perform large number of functions on the same chip area. Therefore, overall system performance and speed get enhanced. These can be used as a control and measurement circuitry in various embedded systems [34].

Figure 9 a- MOS Based NAND Gate

Figure 9 b- Ambipolar Cntfet Based NAND Gate A Simulation and design study was demonstrated by Loan et al in order to propose Carbon Nanotube based Operational Transconductance Amplifier (OTA). Three OTAs have been designed and compared with conventional CMOS-OTA. Fig. 10 shows the DC gain plot of one of the proposed CNT based OTA called as PMOS-NCNT-OTA, where conventional PMOS used as source while N CNTFET used s as sinks. The study has revealed that the CNTs use in the conventional MOSFET will significantly improve the performance. There will be considerable decrease in power consumption, significant increase in the speed and the DC gain. Also, it has been seen that by using an optimum number of CNTs (N), the performance of the CNTFET based OTAs can be improved further [35].

Figure 10 DC Gain Plot of PMOS-NCNTFET OTA

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A Simulation, design and comparative study was accomplished by Nizamuddin et al in order to propose CNT based Cascode operational transconductance amplifiers (COTAs). The proposed CNT based (COTAs) compared with CMOS-COTA. Fig. 11 shows a pure CNT based COTA, which resulted in the minimum power consumption amongst all COTAs, also dc gains and output resistance has augmented by 45%, and 20% respectively whereas the power consumption was noticed 341 times less as compared to the conventional MOS OTA. Augmented gain and output resistance has been observed with the use of Cascoding in the CNTFET based COTAs [36].

Figure 11- Pure CNTFET COTA A Simulation and design study was undertaken by Nizamuddinet al in order to propose high performance CNT based folded cascode operational transconductance amplifiers (FC- OTAs). The circuit diagram of Proposed CNT based FC-OTA as shown in (Fig.12). Improvement in several performance measuring parameters of analog signal processing was shown as compared to CMOS-FC-OTA. DC gain, average power and output resistance were reported to be improved in proposed FC-OTA to desired level [37].

Figure 12- Proposed NCNT-PMOS Folded Cascode OTA A novel low power ternary full adder cell circuit designing and simulation was accomplished by Ebrahimi et al which demonstrated the promising performance parameters like power consumption and power-delay product(PDP). Sum calculation for adder circuit has been demonstrated in Fig. 13. 88 CNT transistors were required for implementing the proposed adder and two situations were undertaken [38]. In the first case (loads=2fF) the

http://iaeme.com/Home/journal/IJARET 117 [email protected] S. Bashiruddin proposed design had shown 77.02% and 68.74% also 92.6% and 89.04% improvement in term of average power and PDP in comparison to the first and the second design presented by Moaiyeri et al, respectively [39] and while in the second case (loads=3fF) it had 77.51% and 60.82% also 92.44% and 84.51% improvement in term of average power and PDP as compared to the first and the second design presented by Moaiyeri et al, respectively [39].

Figure 13- The Completion Adder Circuit for sum Calculation

Figure 14- Pure CNTFET 3SOA A design and calibrated simulation analysis has been performed by Nizamuddin et al in order to propose CNTFET based multistage operational amplifiers (OP AMPs). Three CNT based three stage operational amplifiers (3SOA) were designed, including pure CNTFET based 3SOA (Fig. 14) whereas two 3SOAs were hybrid technology based named as PCNTFET-NMOS-3SOA and NCNTFET-PMOS-3SOA. The proposed three 3SOAs were compared with 3SOA based on the conventional technology. The analysis has shown that CNTFET based 3SOAs have potential to replace the CMOS based 3SOA. Considerable improvement in DC gain, slew rate, power dissipation, CMRR have been noticed in CNT based 3SOAs. Conversely, reduced output resistance was noticed in the pure CNTFET based 3SOA which resulted in poor bandwidth as compared to the CMOS based 3SOA. Moreover, CNTFET based 3SOAs were found highly stable, also performance of the proposed 3SOA found to be optimised by using optimum value of number of CNTs (N), Inter CNT pitch (S) and the diameter of CNT (D CNT), using HSPICE at 0.9 V [40].

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4. CONCLUSION Novel nanoelectronic and geometric features of CNTs contribute enormously to their remarkable potentiality in highly performing as well as energy efficient nano-electronics. Development of high-performance integrated-circuit configuration signifies necessity of high purity and dense nano-tube arrays with semiconducting behaviour. Recently reported CNTFET based 3 stage operational amplifier, novel high gain operational trans-conductance amplifier (OTA), universal logic circuits, tristate buffer, Cascode Operational Transconductance Amplifiers (COTA), folded cascode operational transconductance amplifiers (FC-OTAs), Ternary Full Adder Cell shown and pure CNT based multistage operational amplifier promising results in terms of their improved performance parameters (DC gain, output resistance, slew rate, PDP, average power, speed and power consumption) as compared to respective MOS based circuits. Design, simulation and optimization of various performance measuring parameters to a desired level by changing Channel length, width, Diameter of CNTs, number of CNTs etc at nanoscale are necessitated to be extensively investigated further in order to advantage high quality intrinsic features of CNTs to the fullest.

ACKNOWLEGEMENT The author extends a sincere thanks to AFU, Faridabad, India for providing platform for study.

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