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CALIFORNIA STATE UNIVERSITY, NORTHRIDGE

DESIGN OF NEGATIVE RESISTANCE OSCILLATOR

A Graduate Project Submitted in Partial fulfillment of the Requirements

For the degree of Master of Science in Electrical Engineering

By,

Thrilok Kodihalli Dayanand

December 2016

The Graduate Project of Thrilok Kodihalli Dayanand is approved:

______Prof. Mallard, Benjamin F Date

______

Dr. Valdovinos, John Date

______

Dr. Matthew M. Radmanesh, Chair Date

California State University, Northridge

Dedication

I take this opportunity to convey my regards towards Dr. Matthew Radmanesh, who has been an outstanding advisor for me. It’s because of his support and encouragement in this design project entitled “Design of negative resistance Oscillator”. This factor not only helped me to complete this oscillator design project on time but also increased my knowledge regarding the oscillator design. I would also like to show my appreciation to Professor Benjamin Mallard and Dr. John Valdovinos, who have given me the required support and inspiration to complete my project. My project would be incomplete without all the textbooks and research material that I used in order to complete my project paper. I would also like to thank my parents for their support and encouragement.

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Contents

Signature page ii

Dedication iii

List of figures vi

List of table’s viii

Abstract ix

Chapter 1: Introduction 1

1.1 Problem definition and goal 1

Chapter 2: Oscillator Design Theory 3

2.1 Literature Review 3

2.2 Transistor 4

2.3 Theory of Negative Resistance Oscillator condition 6

2.4 D.C Biasing of Common Source Transistor 8

Chapter 3: Oscillator Design procedure 11

3.1 Design steps for Oscillator 11

3.2 Stability Check 13

3.3 Stability Circle (output) 14

3.4 Selection of ΓT 15

3.5 Design of Negative Resistance Oscillator 16

3.6 Generator Tuning Network Design 17

3.7 Terminating matching network design 20

3.8 Microstrip calculation 25

Chapter 4: Simulation Results (Microwave office)

4.1 AWR subcircuit for transistor (FPD200P70) 33

Chapter 5: Summary of Analysis 41

5.1: Conclusions 42

References 43

Appendix A: Common source FPD200P70 transistor .s2p format 44

Appendix B: Matching circuit design using lumped elements 45

Appendix C: Microstrip gap capacitance formula sheet 54

Appendix D: Matlab program for the oscillator calculation 56

Appendix E: Roger corporation RT/duroid® 3035 65

Appendix F: Excel calculation for oscillator design. 69

Appendix G: Determination of impedance using Reflection co-efficient 72

Appendix H: Selection of DC bias circuit 73

Appendix I: Datasheet FPD200P70 transistor 74

List of Figures

Figure 1.1 Diagram for radio transmitter and receiver. 1

Figure 1.2 Diagram for radio transmitter. 2

Figure 1.3 Diagram for the transmitter and receiver 2

Figure 2.1 Steps to design negative resistance oscillator. 3

Figure 2.2 Block diagram for FET. 4

Figure 2.3 the cross section of an N-type GaAs MESFET. 5

Figure 2.4 Negative Resistance Oscillator diagram using two-port 7

Figure 2.5 common source DC Biasing of FET 9

Figure 3.1 Flow chart of the oscillator design. 12

Figure 3.2 Smith chart for output stability circle 14

Figure 3.3 Matching Network at generator tuning End using smith chart 17

Figure 3.4 Generator tuning network for distributed elements using smith tool 18 Figure 3.5 Transmission line length in degrees using smith tool 18

Figure 3.6 Circuit for Generator Tuning network 19

Figure 3.7 Matching Network at Terminating End using smith chart 20

Figure 3.8 Terminating matching for distributed elements using smith tool. 21

Figure 3.9 Length of the transmission line in degrees using smith tool 21 Figure 3.10 Circuit for Terminating Tuning network 22

Figure 3.11 Transmission line circuit for generator tuning and terminating network 23

Figure 3.12 Layout of generator tuning and terminating network. 24

Figure 3.13 3D Layout of generator tuning and terminating network. 24

Figure 3.14 Layout for the negative resistance oscillator design. 32

Figure 4.1 Transistor FPD200P70 33

Figure 4.2 |S21| and MSG vs frequency from AWR 34

Figure 4.3 |S21| and MSG vs frequency from datasheet. 34

Figure 4.4 N.F. min (dB) vs frequency from AWR. 35

Figure 4.5 N.F. min (dB) vs frequency from datasheet. 35

Figure 4.6 Block diagram of IV curve for transistor. 36

Figure 4.7 Id vs VDS curve for the transistor FPD200P70 from AWR. 36

Figure 4.8 Id vs VDS curve for the transistor FPD200P70 from datasheet. 37

Figure 4.9 Schematic of Low Noise Amplifier. 38

Figure 4.10 Gain and return loss vs frequency. 38

Figure 4.11 Open loop response 39

Figure 4.12 Oscillator frequency spectrum 40

Figure B1 Smith chart for the Terminating matching network 46

Figure B2 Terminating network using smith tool 47

Figure B3 Terminating network value of lumped elements Using smith tool 47

Figure B4 Lumped Elements Circuit for Terminating Network 48

Figure B5 Smith chart for the generator tuning network 50

Figure B6 Generator tuning network using smith tool 51

Figure B7 Generator tuning network value of lumped elements Using smith tool 51

Figure B8 Lumped Elements Circuit for Generator Tuning network 52

Figure B9 Circuit for negative resistance oscillator design using lumped elements 53

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List of Tables

Table 3.4.1 Selection of ΓT 15

Table 3.7.1 Transmission line length values 23

Table 5.1.1 Summary table 41

Table B Table for lumped elements 53

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ABSTRACT

DESIGN OF NEGATIVE RESISTANCE MICROWAVE

OSCILLATOR

Thrilok Kodihalli Dayanand

Master of Science in Electrical Engineering

The topic for this project is to design an Oscillator circuit, which has applications in microwave circuits such as satellite communication systems, etc. A MESFET is selected in the common source configuration such that it exhibits a negative resistance at the desired frequency. The thesis is divided into two segments, Linear Analysis and Harmonic Simulation. In this project, the design is built around a generator-tuning network with a negative resistance and a matching circuit for the terminating network. This design depends on the output stability circle, which can be derived from the S parameters of the transistor from the datasheet. The values obtained from the hand calculations have been compared and verified with the values obtained from MATLAB software.

Chapter 1: Introduction

The Oscillator produces an AC signal across the output terminal without needing an input RF signal. Oscillator is a device, which produces current, or voltage waveform using a dc power supply from the input port. The waveforms are classified into two groups:

1) Linear - sinusoidal waveform 2) Nonlinear - sawtooth waveform

The shape of the waveform and amplitude are determined on the design of the negative resistance oscillator circuit design and its components. These types of oscillators are used in the frequency conversion in radio frequency transmitters or receiver. Similarly, it is used in modern day electronic devices such as television, watches, radio, modems, PLLs.

1.1 Problem definition and goal

Oscillator is used based on the need for receiving and transmitter module of radio signals. Based on the frequency range 15 to 20 GHz.

Figure 1.1: Diagram for Radio Reciever and Transmitter

Hence, the report is based on the designing of the high frequency negative resistance local oscillator.

Design Goal:

Oscillating Frequency: 18.5 ± 0.4 GHz

Output Power: > 20 dBm

Chapter 2: Oscillator Design Theory

2.1 Literature review

Oscillators can be designed based on the two different method: negative resistance method and positive feedback method. Since a transistor oscillates at certain frequency, this report is based on the negative resistance oscillator condition.

The first step for designing the oscillator is to choose the transistor with s-parameter and verify the condition of the transistor. Next step is to choose the generating and terminating network for the transistor in order to create the negative resistance oscillator. The circuit can be built with the distributed elements for higher frequency and lumped elements for lower frequency. However, in this thesis selected distributed elements to design the circuit and added the lumped elements design in the Appendix B as an alternate method.

There are three types of transistor configurations to design oscillators: common drain Common gate, and Common source. Common drain configuration is difficult to design for high frequency oscillator. So, common source or common gate configuration are used. The common source configuration has been chosen in this thesis.

Generator Transistor Transitor tuning and Terminating Simulation Selection Simulation network

Figure 2.1: Steps to design the Negative Resistance Oscillator

2.2 Transistor First, we have to choose the transistor, which have high frequency low noise figure. The brief summary of the transistor is explained below.

Figure 2.2: Block diagram of FET

There are three-transistor configuration that can be utilized to design 2-port oscillators:

1. Common source

2. Common drain

3. Common gate

The common source configuration is selected in this thesis.

The transistor FPD200P70 (pHEMT) is a depletion mode AlGaAs High Electron Mobility Transistor. It utilizes a (0.25 x 200) µm Schottky barrier gate field effect transistor.

The primarily used device, which also happens to be one of the most crucial device in active circuits of the Microwave industry, is the GaAs based metal semiconductor in Field Effect Transistor’s. This importance can be justified with the fact that until the late 1980s, metallic GaAs MESFET’s was used in most of the integrated circuits in the Microwave industry. Even now with the advanced technology, better performing FET’s have been introduced in the market, metallic semiconductor FET’s still dominate the applications for Power Amplifiers and Microwave Spectrum Switching Circuits in active device category. The schematic for basic MESFET is shown below in Figure 2.3. The GaAs substrate is made up of semi-insulating material and the fabrication of transistor is from this substrate

4 material. In order to remove the defects from the substrate of the transistor, a layer of buffer is grown epitaxially on this semi-insulating substrate. This epitaxially grown conducting layer is made up of semiconducting material and is situated over a layer of buffer that is thin with lightly doping (n). In Microwave transistors, the conducting channel is always an n type. The process is completed by growing a highly doped (n+) layer on the surface in order to support the fabrication of the transistor contacts having a low resistance. This layer is inscribed away in the channel region. Another method is to implant the ion in order to create the n channel. The source and the drain, which correspond to the two ohmic contacts, provide access to the outer circuit be fabricated on the high-doped layer. The gate is fabricated between these two contacts and alternatively can be fabricated by a rectifying contact as well. Typically, the ohmic contacts are based on Au–Ge material and the Schottky contact are based on Ti–Pt–Au.

Figure 2.3 The cross section of an N-Type GaAs MESFET

GaAs transistors are usually preferred over Si-based transistors, especially in high frequency applications since the GaAs carrier mobility is much higher. Moreover, the electron saturation velocity for GaAs is much larger than that of Si, resulting in a wider operating frequency range.

2.3 Theory of Negative Resistance Oscillator condition

Negative resistance oscillator design is actually a two-Port circuit design, which will use the transistor that will operate in the unstable region. However, in practice a two-port oscillator can be effectively converted to a one-Port oscillator design by terminating a potentially unstable transistor with an appropriate impedance in the unstable region.

Figure 2.4: Negative Resistance oscillator design using two-port

Where,

Zg (ZL) and Γg = Impedance of Generating matching network and generating matching reflection coefficient

ZT and ΓT = Impedance of Terminating network and terminating network reflection coefficient [S] = S-parameter of the transistor.

Unlike an amplifier (where the device is required either to have a high degree of stability or be unconditionally stable), the desire of the transistor should be unstable. To attain this condition, we select the transistor to be configured based on common source (or gate) for Field Effect Transistor.

To generate oscillation for a two-port oscillator device following condition should be satisfied:

 Unstable transistor condition:

Where

 Oscillating generator tuning port:

 Oscillating terminating port:

The matching circuits for the transistor on both sides are distributed circuits, the below conditions can be verified.

 |ΓT| < 1

 Hence |Γin| > 1 (negative resistance)

The conditions obtained from the above requirement for oscillation must also be satisfied.

(Zg + Zin) < 0

(Rg + Rin) < 0 and (Xg + Xin) = 0

As a result, the most important procedure will be using proposed method for designing the oscillators by choosing the generating network gate resistance value 1/3rd of the input port resistance (|Rin|/3). Then choose the imaginary components (Xg = -Xin).

2.4 D.C Biasing of Common Source Transistor: (Appendix H) Operating FET as an oscillator, transistor should be in the saturation region. The steps followed have been shown below.

 In Field Effect Transistor, common source biasing has been used.  The voltage selected for gate-source voltage will be negative for Field Effect Transistor.

 Since, it is a common source Drain-source voltage will be zero, gate voltage (VG) and source voltage has been connected together with single voltage source.

 The gate resistance (Rg1 and Rg2) is connected to gate end and resistance Rs is connected to source end.  The voltage will be zero across the drain since it is connected to ground.

 The drain current (ID) is considered as zero for Field Effect Transistor.  Hence, it’s a single voltage supply DC Biasing.

Common Source FET DC Biasing:

VDS = 5v

IDS = 30mA

VGG = -15V

IDSS = 60mA

Vt = -0.85V

IDS = 30 mA

VD = 0V

VS = -5V

Method 1:

VGS = -0.45V (from IV curve of transistor data sheet)

VG = VDS + VGS = -5+ (-0.45) = -5.45

(-5.45) x [R2/ (R1+R2)] = (-15)

R2 = 1MΩ, R1 = 2R2 =1.75 MΩ

Rs = V/I = 10.75/30mA = 378Ω

V= VDS - VG = -5-(-15.75) = 11.35V

Method 2: (Verifying VGS)

2 K = IDSS/Vt = 60 mA/ (-0.85) = 0.0830

IDS = K [VGS - Vt] = -0.249 > Vt and -1.45 < Vt

VG = VDS + VGS = -5+ (-0.249) = -5.25

(-5.25) x [R2/ (R1+R2)] = (-15)

R2 = 1MΩ, R1 = 2R2 =1.85 MΩ

Rs = V/I = 10.75/30mA = 358.3Ω

V= VDS - VG = -5-(-15.75) = 10.75V

Figure 2.5: Common Source DC Biasing of FET

For biasing network, f = 18.5 x 109Hz

Z0 = 50Ω

ω = 2휋f = 1.1618 x 1011

RF CHOKE:

ZL is 10 times of Z0 = 50Ω and ω = 2휋f

ZL = jωL

50 x 10 = 2πfL

L = 4.301 nH

DC BLOCK:

ZC is 1/10 times of Z0

ZC = 1/ (jωC)

50 1 ( )= ( ) 10 2πfC

C = 1.72 Pf

Chapter 3: Oscillator Design Procedure

3.1 Design steps for oscillator:

Based on the discussion, the following design procedure for a transistor Oscillator is discussed below: a) Choose a transistor, which is unstable at the certain frequency. b) Choose a Transistor with circuit configuration, i.e: a) Bipolar Junction Transistor: Common emitter or common base b) Field Effect Transistor: Common source or Common gate c) Using the smithchart draw the stability circle (output). d) Choose a value of ΓT in the region, which is unstable, will produce a negative Resistance (as large as possible) at the generating part of the transistor, i.e Zin < 0 e) Choose the generating matching network impedance (Zg), by choosing this value the obtained results will be: (Rg + Rin) < 0 To satisfy oscillation condition, a value for Rg is chosen as follows

Rg = |Rin|/3, Rin<0 The imaginary part of Zg is choosed for the circuit:

Xg = -Xin f) Design Terminating and Generating matching networks using distributed elements and lumped elements methods.

Select proper Device

DC bias design

Device S parameter Characterization

Stability Condition

Matching circuit Design Smith chart

Oscillator circuit Design

Negative Resistance Oscillator

Figure 3.1: Flow Chart for Oscillator Design

3.2 Stability Check:

The common source s-parameters at 18.5 GHz are:

S11= 0.688 ∟-4.7°

S12= 0.096 ∟-72.3°

S21= 2.307 ∟-137.3°

S22= 0.593 ∟98.4°

By the above parameters, manually check for the stability using below formulas.

K-parameter:

1−(0.688)2−(0.593)2+(0.34)2 = = 0.65 < 1 2|(0.96∟−72.3° x 2.307∟−137.3°)|

Where,

= |0.688 ∟-4.7° x 0.593 ∟98.4° - 0.096 ∟-72.3° x 2.307 ∟-137.3°|

= 0.34 < 1

Hence, it is a potentially unstable transistor.

Since, transistor in unstable region, check for the output stability circle through the smithchart and design the generating and terminating matching network for the transistor.

3.3 stability circle: (output)

The stability circle with output parameter is shown below:

2 2 DT = |S22| -|∆| = 0.236

RT = |S21S12| / DT = 0.95

* * CT = (S22 - ∆S11 ) / DT = 1.76 ∟-116°

The |S11|=0.688 < 1, unstable region lies inside the smith chart as shown below.

Figure 3.2: Smith chart for output stability circle.

3.4 Selection of 횪퐓:

ΓT Γin Zin(calculation) Zin(smithchart)

0.9∟-112° 1.05∟5.77° -8.1+16.6j -8+16j

0.87∟-110° 1.03∟7° -3.92+16.3j -4+16j

0.86∟-108° 1.01∟8.4° -0.96+14.25j -1+13j

0.84∟-127° 0.99∟-3.27° N/A N/A

1∟-90° 0.95∟27.62° N/A N/A

0.95∟-105° 1.09∟12.17° -3.3+8j -4+7.5j

1∟-100° 1.10∟18.22° -1.8+5.67j -2.2+6j

0.93∟-115 0.92∟3.26° -16.5+12.4j -16+12j

1∟-105° 1.14∟12.79° -3.98+6.5j -4+6.5j

0.98∟-105° 1.11∟12.52° -3.7+7.1j -3.7+7.2j

Table 3.4.1 Selection of ΓT

The ΓT is selected inside the stable circle with various points and has been shown in the above table. The ΓT value is selected such that Γin should be greater than one or the highest value. From the above ΓT values, I have selected 0.93∟-115° because its Γin value is greater than one and has better Zin values.

3.5 Design of Negative Resistance Oscillator

To design the oscillator, first choose a ΓT from an unstable region of the output stability circle such that Γin will be greater than one. This will create a negative resistance at the input port.

ΓT = 0.93 ∟-115° |ΓT| < 1

(S12S21ΓT ) Γin = S11 + [ ] (1−S22ΓT)

= 1.08∟3.26° > 1 (negative resistance)

1 = 0.92 ∟3.26° Γin

Input port impedance:

(1+Γin) Zin = [ ] = -16.2 + 12.4j (theoretical value) (1−Γin)

50Zin = -810 + 620j

Plot Γin on the smith chart to find the input impedance

Zin = 16 + 12j (negating r) (see appendix G)

Zin = (-16 + 12j) x 50 = -800 + 600j

Rin Rg = = 800/3 = 266.6 3

Xg = -Xin = -600j

(Rg + Xg) Zg =( ) = 5.3 - 12j 50

Finally,

(1+ΓT) (1+0.93∟−115°) ZT = [ ] = [ ] = 0.05 - 0.63j (1−ΓT) (1−0.93∟−115°)

3.6 Generator Tuning Network Design:

The above Γin was found to be 1.08 ∟3.26° and therefore, Zin to be

Zin = [(1+Γin)/ (1- Γin)] = -16.2 + 12.4j (theoretical value)

Zg = (Rg + Xg)/50 = 5.3 - 12j

Figure 3.3: Matching Network at generator tuning End using smith chart

Figure 3.4: Generator tuning matching for distributed elements using smith tool

Figure 3.5: Transmission line length in degrees using smith tool

A resistor with a resistance of 65Ω has been used at point A. The open shunt stub has been used from point A to point B (VSWR and conductance intersection). The distance between these two points are shown below.

ℓAB = (0.43λ - 0.25λ) = 0.18λ (open shunt stub)

Next point is to travel, from point B until point G on VSWR circle on the smith chart. The distance between those, two points are shown below.

ℓBG = (0.500λ - 0.434λ + 0.261λ) = 0.327λ (transmission line)

Figure 3.6: Circuit for Generator Tuning network

3.7 Terminating Matching Network Design

The above ΓT was found to be 0.93∟-115° and therefore ZT to be

[(1+Γ푇) ZT = [ ] = 0.05 – 0.63j (1−ΓT)

Figure 3.7: Matching Network at Terminating End using smith chart

Figure3.8: Terminating matching for distributed elements using smith tool

Figure3.9: Transmission line length in degrees using smith tool

From above smith chart, open shunt stub has been used to indicate above from load point 50Ω (point O) to point A (VSWR and conductance intersection). The Distance between those two points is shown below.

ℓOA = (0.47λ – 0.25λ) = 0.22λ (open shunt stub)

Next point is to travel, from point A to point B on VSWR circle on the smith chart. The distance between those two points is as shown below.

ℓAB = (0.50λ – 0.47λ + 0.411λ) = 0.441λ (transmission line)

Figure 3.10: Circuit for Terminating network

Figure 3.11: Transmission line circuit for Generator tuning and Terminating Network

Smith tool parameter smithchart calculation Verification Exact calculation (degree) calculation (0.327x9.7mm) (118.7°/360°) TL1 0.327λ 3.2 mm 118.7° 0.32λ

(0.441x9.7mm) (158°/360°) TL3 0.441λ 1.8 mm 158° 0.43λ

(0.18x9.7mm) (65.11°/360°) TL2 0.18λ 2.7 mm 65.11° 0.18λ

(0.22x9.7mm) (79°/360°) TL4 0.22λ 1.3 mm 79° 0.21λ

Table 3.7.1 Transmission line length values

Figure 3.12: Layout of generator tuning and terminating network

Figure 3.13: 3D Layout of generating and terminating network.

3.8 Microstrip calculation for transmission line

The transmission line consists of a strip of the conductor with width (w) and thickness (t), which is placed above the dielectric substrate (εr) as shown in below figure. In this project, a dielectric constant (εr = 3.55) and a dielectric thickness (h = 0.5 mm) is selected based on the Rogers data sheet (Appendix E).

Basic Diagram for Transmission Line

Transmission line of 50Ω is designed based on 18.5 GHz frequency by selecting the εr and h from the datasheet available from the Rogers datasheet. By these two specification the remaining width, wavelength, and εeff are calculated. f = 18.5 GHz

Z0 = 50Ω

εr = 3.55 (From Rogers corporation appendix E) h = 0.5 mm (From Rogers corporation appendix E)

C = 3 x 108 m/s

λo = c/f = 16.2 mm

Exact method:

Assume,

W/h ≤ 2

8푒(퐴) W/h ≤ = 2.27mm (푒(2퐴)−2)

푍표 (ε +1) (ε −1) 0.11 A = ( ) (√ 푟 ) + (( 푟 ) (0.23 +( ))) = 1.4 60 2 εr+1 ε푟

W = 2.27 x 0.5 = 1.13 mm

Graphical method:

By exact and graphical method, it is confirmed that at w/h (2.3), characteristic impedance

(Z0) is found to be 50Ω.

Since,

W/h > 0.6

λ0 εr 1/2 λ = [ W ] = 9.7 mm √εr 1+0.63(ε −1) ( )0.1255 r h

푊 ≤ 1 ℎ

Length calculation using direct method:

Length of the terminating network

Open shunt stub:

ℓ = 0.22λ = 0.22 x 9.7 = 2.13 mm

Transmission line:

ℓ = 0.441λ = 0.441 x 9.7 = 4.27 mm

Length of the generator-tuning network

Open shunt stub:

ℓ = 0.18λ = 0.18 x 9.7 = 1.76 mm

Transmission line:

ℓ = 0.327λ = 0.327 x 9.7 = 3.17 mm

Length calculation using formulas: Length of the terminating network

Open shunt stub:

2휋 βd = x 0.22λ = 1.38 휆

βdc ℓ = = 2.1 mm 2πf√εeff

Transmission line:

2휋 βd = x 0.441λ = 2.769 휆

βd c ℓ = = 4.3 mm 2πf√εeff

Length of the generator-tuning network:

Open shunt stub:

2휋 βd = x 0.18λ = 1.13 휆

βdc ℓ = = 1.8 mm 2휋푓√ε푒푓푓

Transmission line:

2휋 βd = x 0.327λ = 2.053 휆

βdc ℓ = = 3.2 mm 2휋푓√ε푒푓푓

Microstrip calculation for Characteristic impedance: f = 18.5 GHz

Z0 = 50Ω

εr = 3.55 (From Rogers corporation appendix E) h = 0.5 mm (From Rogers corporation appendix E)

C = 3x108 m/s

λo = c/f = 16.2 mm

Exact method:

Assume,

W/h ≤ 2

(8푒퐴) W/h ≤ = 2.27mm (푒(2퐴)−2)

푍표 (ε +1) (ε −1) 0.11 A = ( )(√ 푟 ) + ( 푟 ) (0.23 +( )) = 1.4 60 2 (εr+1) ε푟

W = 2.27 x 0.5 = 1.13 mm

ℓ = W/3 = 0.38 mm

Quarter wave transformer:

휆 λg = = 16.2 / √2.48 = 10.28 mm √휀푒푓푓

ℓ = λg/4 = 10.24/4 = 2.57 mm

To find width consider Z0 = 120Ω

Exact method:

Assume,

W/h ≤ 2

(8푒(퐴)) W/h ≤ = 0.40 mm (푒(2퐴)−2)

푍표 (ε +1) (ε −1) 0.11 A = ( ) (√ 푟 ) + ( 푟 ) (0.23 +( )) = 3.0 60 2 (ε푟+1) ε푟

W = 0.40 x 0.5 = 0.2 mm

Graphical method: (verification)

By exact and graphical method, it is confirmed that at w/h (0.4), characteristic impedance

(Z0) is found to be 120Ω.

Microstrip Gap Capacitance Calculation: (Appendix C)

W1 = W2 = 1.13 mm (from layout)

Cs = 1.72 pF (From Page 10) h = 0.5 mm (From Rogers corporation appendix E)

Q5 = 1.23/(1 + 0.12((w2/w1) − 1)0.9) = 1.23

s h w2 Cs [pF] = (500 h) (exp (-1.86 ) Q1 (1+4.19(1-exp (-0.785√ )))) h w1 w1

h w2 S = (log (Cs/500 h Q1 (1+4.19(1-exp (-0.785(√ ) ))))/h) x (-1.86) = 0.38mm w1 w1

Cut-off frequency: (f0)

Z0 f0 (GHz) = 0.3√ (h should be in cm) h√(εr−1)

Where,

Z0 = characteristic impedance h = height

εr = 3.55 (From Rogers corporation appendix E) h = 0.5 mm (From Rogers corporation appendix E)

50 f0 (GHz) = 0.3√ 0.05√3.55−1)

= 7.5 GHz

Figure 3.14: Layout for the negative resistance oscillator design

Chapter 4: Simulation

4.1 AWR Subcircuit for transistor: (FPD200P70) An unstable MESFET transistor was chosen on purpose so that the Oscillator can work at the decided operating frequency of 18.5 GHz. Due to this, a common source based device FPD200P70 transistor which is obtained by the Filtronic datasheet. Leads to a value of K < 1 at specified frequency. The first step was to use a simulating software such as AWR to model the selected transistor.

The simulating software such as Microwave office was used for the verification of the nonlinearity model given in the datasheet. Below figure shows the simulation of the transistor FPD200P70. Step 1: Before the simulation, we have to create the .s2p file of the FPD200P70 transistor. Step 2: extract the .s2p file in microwave office and create the subcircuit. Step 3: the subcircuit will have two pins change it to three pin (ground pin). Step 4: select the layout as FET. The transistor is obtained as shown below

Figure 4.1: Transistor FPD200P70

To verify the .s2p file of the transistor, we have to do a typical frequency response, or typical IV characteristics of the transistor.

Simulation of the transistor:

Step 1: finding the typical frequency response (|s21| and MSG vs frequency) and

(Noise figure minimum in dB vs frequency).

Figure 4.2: |s21| and MSG vs frequency

Figure 4.3: |s21| and MSG vs frequency transistor datasheet

In the above figures, we can look at the maximum available gain (MAG) and S21 parameter of the transistor FPD200P70. According to the datasheet of the FPD200P70 transistor, the MAG of 17dB is at 5.5GHz; but according to the simulation, we obtain almost 20dB at 5.5 GHz. By this way, it is easy to compare the similarities between the simulation obtained from microwave office and the datasheet value.

Figure 4.4: N. F. min (dB) vs frequency

Figure 4.5: N.F .min (dB) vs frequency based on datasheet In the above figure, we can look at the noise figure minimum in dB verses frequency. The noise figure increases its value from 0.2 to 3dB from 0.5 to 26GHz. The simulation is performed for VDS = 5v, for comparison the red line of the graph is considered from the above figure.

Step 2: Create the IV curve block for the transistor as shown in below figure (typical IV characteristics). Connect the wire from step to ground pin and sweep to collector pin.

Figure 4.6: Block diagram of IV curve for transistor.

Figure 4.7: ID vs VDS curve for the transistor FPD200P70.

Figure 4.8: ID vs VDS curve for the transistor FPD200P70 datasheet.

We have to simulate the FPD200P70 Field Effect Transistor for the IV characteristic curve the simulations obtained is compared with the results obtained by the datasheet.

Simulation for the VDS – IDS curves obtained from both the datasheet and simulated results are not comparable. According to the result from the datasheet, it is found that the ID should reach 100 mA (figure 4.8) instead it reached 50 mA as shown in figure 4.7. The reason for this change is the simulation is performed for VGS instead of VG on microwave office.

Step 3: Low Noise Amplifier Design will be Tested using gain and return loss vs frequency.

Figure4.9: Schematic of Low Noise Amplifier

Figure4.10: Gain and return loss vs frequency.

Figure 4.11: open loop response

On the left axis Open loop, response is obtained in the form of the linear s-parameter (S11) and on right axis angular S-parameter (S11) vs frequency is measured from 13GHz to 20GHz. At 18.5GHz, value is almost zero for the phase shift (red line) and the open loop response is almost one. The slope of the phase shift is negative and will significantly falls towards negative.

Figure 4.12: oscillator frequency spectrum

Oscillator frequency spectrum obtained from measuring the output power at port 2 and the value is obtained in the form of dBm for the output measurement Pharm(port2) schematic is used. At 18.5GHz the only harmonics with positive output power is of 24.86 dBm, the rest has negative values. From this, we understood that it produces oscillating output power at 18.5GHz only.

Chapter 5: Summary of Analysis

The table below shows the parameter obtained in the project from different ways mentioned below. When comparing all the three parameters on the table, it shows that there is a slight difference in the values, which are allowed.

Parameter Hand calculation MATLAB Results AWR Simulation

ΓT 0.95 ∟-105° 0.949 ∟-105° 0.95 ∟-105°

Γin 1.09∟12.17° 1.08∟11.98° 1.09∟12.17°

Zg 1.3-7.5j 1.3333 - 7.5000j 1.3-7.5j

Rg 66.6 66.6667 66.6

Xg -375j 3.7500e+02j -375j

Rin 200 200 200

CT 1.76∟-116° -0.7876 - 1.5887j 1.76∟-116°

RT 0.95 0.9435 0.95

DT 0.236 0.2347 0.23

Table 5.1.1: Summary table

5.1: Conclusions

In this project, a two-port negative resistance oscillator has been designed using the S- parameters provided by the FILTRONICS manufacturer data sheet. Using this method, the theory, design and simulation at the fixed 18.5 GHz frequency is developed and presented in this work. Oscillator works at 18.5 GHz with an output power of 24.86 dBm. The open loop response of the oscillator is found to have a narrow bandwidth between 17 GHz to 19 GHz.

Since the design is based on the 18.5 GHz, distributed elements are used for the matching networks. To find the exact length and width of the transmission lines the microstrip design equations were used. An alternate circuit is also designed based on the lumped elements and is included in Appendix B.

References

 Matthew. Radmanesh, Ph.D. Advanced RF & Microwave Circuit Design

 AWR Corporation, microwave office: Simulation and Analysis Guide.

 Agilent Technologies. Advanced Design System. Santa Clara, CA (manual)

 Pozar, M. D. Microwave engineering fourth edition Hoboken, NJ.

 http://web.mit.edu/timv/Public/Microwave_Engineering_David_M_Pozar_4ed_W iley_2012.pdf

Appendix A

Common source FPD200P70 transistor .s2p format:

Appendix B Matching circuit design using lumped elements Terminating Network Design Using Lumped Elements:

From Table-3.4.1, ΓT was found to be 0.93 ∟-115° and hence ZT to be

[(1+ΓT) ZT = [ ] (1−ΓT) 1+0.93∟−115° = [ ] 1−0.93∟−115° = 0.05 – 0.63j

Terminating network can be created from the smith chart.

st 1 step is to choose the ΓT point in the unstable region. Choose ΓT point such that Γin value should be maximum.

2nd step from point A (50Ω) move towards down on the conductance circle until the point B. Since it is on the conductance circle moving downwards, it’s a parallel capacitor with the value found to be 4.3j.

3rd step from point B move towards down on the resistance circle until point C. Since it is on the resistance circle moving downwards, it is a series capacitor, which is found to be - 0.42j.

4th step is at point A, which is found at the center of the smith chart to be a 50Ω resistor.

Figure B1: Smith chart for the Terminating network.

Figure B2: Terminating network using smith tool

Figure B3: Terminating Network value for the lumped elements using smith tool

From the smith chart, we can identify that we have to move from the resistive load (50Ω) at point A. From point A, the line is drawn on a conductance circle until it reaches the point B. Since it is on conductance circle moving, downwards parallel capacitor is used.

Then the line starts from point B to point C(ΓT) on a constant resistance circle and it is moving downwards, hence a series capacitor is used.

Shunt Capacitor:

j∗2∗3.14∗18.5∗109∗C3 4.3j = 0.02

C3 = 0.740 pF

Series Capacitor:

−j -0.42j = 2∗3.14∗18.5∗109∗C∗50

C2 = 0.409 pF

Figure B4: Lumped Elements Circuit for Terminating Network

Generator Tuning Network Design Using Lumped Elements:

From chapter 3 (section 3.5) Γinwas found to be 1.08 ∟3.26 and hence Zin to be

(1+Γin) Zin = [ ] = -16.2 + 12j (theoretical value) (1−Γin)

50Zin = -810 + 600j

(Rg + Xg) Zg = = 5.3 - 12j 50

Generator tuning network was found using smith chart.

st 1 step is to find the Γin value, since it is greater than one reciprocate the value and plot it.

nd 2 step according to the application #3 (chapter 10) (appendix G) negating Rin value and keeping the Xin value constant.

rd 3 step is finding the Zg value using below formula

Rg = Rin/3 Xg = -Xin Zg = Rg+Xg

th 4 step is to plot the Zg value and draw a line downwards from point F (265Ω) to E (Zg point). Since it is travelling downwards on a resistance circle, it is a series capacitor.

Figure B5: Smith chart for the generator-tuning network

Figure B6: Generator tuning network using smith tool

Figure B7: Generator Tuning network value for the lumped elements using smith tool

The resistor, with the resistance 65Ω, at point F is used to attain the resistive component at the generator-tuning network. From point F, the line is drawn until Zg (point E) on a constant resistance circle since it is moving downwards series capacitor be used.

Series capacitor:

−j -12j = 2π18.5x109xC1x50

−j C1 = = 0.143 pF 2π18.5x109x(−12j)x50

Figure B8: Lumped Elements Circuit for Generator Tuning Network

Figure B9: AWR Circuit for negative resistance oscillator using lumped elements.

Hand Matlab Smithtool Parameter caluculation caluculation verification

(Input series)

-14 -14 C1 1.434x10 F 1.434x10 F 14.4 fF

(output series)

-13 -13 C2 7.40x10 F 7.40x10 F 777.20 fF

(output parallel)

-13 -13 C3 4.09x10 F 4.098x10 F 404.7 fF

Table B: Table for lumped elements

Where, fF = femtofarad (10−15)

Appendix C

Microstrip gap capacitance

Appendix D

Matlab program for the oscillator calculation:

Results:

Matlab code of lumped elements for generator tuning and terminating network:

Results:

Microstrip matlab calculation for width and length of generator tuning and terminating network:

Results:

Matlab Code for DC BIASING:

Results:

Matlab calculation for the Length of the Quarter wave transformer:

Results:

Microstrip gap capacitance code:

Results:

Appendix E

Rogers Data Sheet

Appendix F

Excel Calculation

Appendix G

Determination of impedance using Reflection co-efficient

Appendix H

Selection of DC bias circuit

Appendix I

Transistor Data Sheet