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Negative Resistance in Cascode Transistors

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Negative Resistance in Cascode Transistors 1 Negative Resistance in Cascode Transistors Mohammad Samizadeh Nikoo, Member, IEEE, Armin Jafari, Nirmana Perera, Student Member, IEEE, and Elison Matioli, Member, IEEE Abstract—Cascode topology which includes a high-voltage GaN issues must be resolved to fulfill the attractive aspects of these and a low-voltage Si transistor is an attractive device concept, devices in efficient power converters. In particular, Huang et al. which uses the low ON-resistance of GaN while still being [8] reported amplification of ringing voltage, so called compatible with Si gate drivers. It demonstrates the highest divergent oscillations, following turning-OFF switching events threshold voltage among normally-OFF GaN devices, which is a favorable feature in power electronics. However, the observation of the cascode transistors, which eventually causes device of instability in power circuits using cascode devices highlights the failure due to overvoltage. need for a careful analysis to reveal the origins of this In this work, we demonstrate negative resistance in the OFF- phenomenon, to fulfill the unique feature of these devices in high state of cascode GaN devices, which causes large-signal efficiency and reliable power converters. In this letter, we instabilities in the device operation. We also show how the demonstrate the presence of negative resistance in cascode devices, frequency range of negative resistance changes with device area which explains the previously reported large-signal instabilities. We describe a theory to characterize this negative resistance (i.e., current capability). Finally, we provide an explanation for behavior based on the sub-threshold-voltage operation of the high- this negative resistance, and present guidelines for eliminating voltage GaN transistors, and propose guidelines to resolve this the issue. These observations are also of great interest for new issue in cascode devices. Negative resistance behavior, although device concepts featuring negative resistance, and for not favorable for a power transistor, is of great importance in applications such as reflection-type RF amplifiers [10]. high-frequency electronics, with applications in reflection-type power amplifiers. These results, together with the presented II. EXPERIMENTAL OBSERVATIONS analysis, could inform the development of high-stability, low-loss devices for future efficient power converters. Impedance of several commercial 650-V and 900-V-rated Index Terms—Cascode, normally-OFF, GaN, Si, negative cascode transistors (Table I) was measured using a Keysight resistance, divergent oscillations, instability. E4990A 50-MHz high precision impedance analyzer (Fig. 1a). The tool biases the device under test (DUT) at a certain DC I. INTRODUCTION level, and using phase-sensitive voltage and current IGH-ELECTRON-MOBILITY transistors (HEMTs) measurements, measures the impedance of the DUT. The H based on AlGaN/GaN heterostructures offer an method can be used for circuit modeling of any active or passive outstanding potential for power applications, thanks to superior components [7]. The devices were characterized in their OFF- material properties such as a large critical electric field and high state by shorting gate and source. Based on the measured electron saturation velocity. These properties lead to design of impedance, we extracted the output capacitance (COSS) and power devices with high voltage ratings and low ON-resistance series resistance (RS) of devices at different frequencies and voltage biases. (RON) [1]. AlGaN/GaN power HEMTs, however, are naturally normally-ON (d-mode), which is not favorable in power Fig. 1b shows COSS versus drain-source voltage (VDS) measured at 1 MHz, although measurements at other electronics. Therefore, several techniques – such as fluorine frequencies (100 Hz to 10 MHz) yield almost the same results. plasma treatment [2], p-GaN gate [3], gate recess [4] – have From VDS = 0 up to VDS ~ 20 V, the high-voltage GaN transistor been proposed to achieve normally-OFF (e-mode) operation. (HV-GaN) is ON (Fig. 1c) and the voltage stress is held by the Decreasing the ON-state current and increasing the RON are low-voltage Si MOSFET (LV-Si), resulting in a gradual potential drawbacks of these techniques. Furthermore, the reduction of its output capacitance ( ). Just after VDS ~ 20 threshold voltages of e-mode GaN transistors are considerably V, the positive bias at source of the SiGaN transistor builds a OSS smaller than those of Si and SiC devices, which is unfavorable negative bias on its gate-source voltage, which is large enough for safe operation, and also requires adapted gate drivers. to turn OFF the transistor. At this point, the output capacitance Cascode configuration that includes a high-voltage, post- of the GaN transistors ( ) acts in series with (Fig. 1d), process-free, normally-ON GaN HEMT and a low-voltage, Si GaN Si TABLE I MOSFET enables normally-OFF operation, with a high OSS OSS SPECIFICATIONS OF EVALUATED CASCODE GAN/SI TRANSISTORS threshold voltage compatible with Si and SiC gate drivers [5]. Voltage and current rating R ** Recently, dynamic measurements have revealed some Device ON Voltage (V) Current* (A) (mΩ) potential drawbacks of cascode configuration, such as higher A 650 035 035 charging/discharging output capacitance (COSS) losses [6], [7], B 650 050 050 and instabilities under high-switching currents [8], [9]. These C 650 072 072 The authors are with the Power and Wide-band-gap Electronics Research D 650 150 150 Laboratory (POWERlab), École polytechnique fédérale de Lausanne (EPFL), E 900 170 170 CH-1015 Lausanne, Switzerland (e-mail: [email protected] [email protected]). * Continues current at 25 ºC. ** Effective dynamic RON (typical) © 2020 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. 2 Impedance analyzer 3 (a) (b) (a) 3 with a built-in bias-tee Z(ω) VDS = 20 V to 28 V 20 V COSS 2 ∆V = 1 V 2 (nF) R RS S 1 21 V COSS OSS ) C 1 0 DUT Ω (k Mode 1 Mode 2 S -1 22 V R 0 0 10 20 30 40 -2 Voltage (V) -3 (c) (d) GaN Mode 1 Mode 2 COSS Negative Resistance -4 D D 1.0E+02100 1.0E+03 1k 1.0E+0410k 1.0E+05 100k 1.0E+0 1M LV-Si HV-GaN LV-Si HV-GaN Frequency (Hz) (ON) Si (OFF) C Si C (b) (c) 2 OSS OSS Measured at 400 kHz 2 0 ) Ω -2 S S Datasheet -4 (e)100 5 (f)100 5 10 10 1 VDS = 20 V VDS = 25 V -6 4 4 Measurement 10 10 Resistance ( Capacitance (nF) -8 101 3 101 3 ) Negative Resistance ) Ω 0 -10 Ω 2 2 ( 0.1 0.1 10 | ( 10 S 0 50 100 150 200 0 50 100 150 200 S R R 0.01101 | 0.01101 Voltage (V) Voltage (V) (d) 0.001100 0.001100 Negative Device E: 900-V, 15-A Resistance 0.000110-1 0.000110-1 10k 100k 1E+2100 1E+31k 1E+4 1E+5100k 1E+61M 1E+2100 1E+31k 1E+410k 1E+5 1E+61M Device D: 650-V, 16-A Frequency (Hz) Frequency (Hz) Fig. 1. (a) Measurement setup for acquiring the impedance under DC bias, Device C: 650-V, 27-A utilizing a 50-MHz impedance analyzer. (b) Measured output capacitance of a 36 A cascode transistor (device B) versus bias level (VDS). The measurements Device B: 650-V, 36-A are very consistent with frequency (the plotted data corresponds to a 1-MHz measurement). The inset shows the device model that includes a capacitance Device A: 650-V, 47-A COSS in series with a resistance RS. (c) At zero gate voltage, for VDS < 20 V Negative Resistance Window (mode 1) the GaN transistor is still ON, and (d) it turns OFF for VDS > 20 V 1.0E+0110 1.0E+02 100 1.0E+03 1k 1.0E+04 10k 1.0E+05 100k 1.0E+06 1M 1.0E+010M (mode 2). (e) RS versus frequency at VDS = 20 V (mode 1). (f) Absolute value Frequency (Hz) of R versus frequency at V = 25 V (mode 2). R is negative for the shown S DS S Fig. 2. (a) Measured R versus frequency for device B at different bias frequency range, however, the absolute values are plotted as a log scale is used. S voltages VDS = 20 V to 28 V (∆V = 1) in linear scale. (b) Measured output resulting in an abrupt reduction in the total COSS. Figs. 1e and capacitance at higher voltages up to 200 V using an external bias-tee together 1f show the real part of the measured impedance (RS) versus with reported data in datasheet. (c) Measured RS at 400-kHz for voltages up to 200-V. The device exhibits a negative resistance with a higher magnitude for frequency for VDS = 20 V and 25 V, respectively. The device higher VDS. (d) Negative frequency window measured at VDS = 40 V for cascode shows normal behavior up to VDS ~ 20 V, when the GaN devices with different voltage ratings and current capabilities (Table I). transistor is ON. The anomalous behavior of the device starts just after the GaN transistor turns OFF. As shown in Fig. 1f, the analyzer can internally apply DC bias voltages up to 40 V. To device displays normal behavior at very low frequencies, since perform measurements at higher voltages, we employed an COSS is almost open impedance, and the leakage current external bias-tee. As shown in Fig. 2b, the measured determines the RS. For the considered transistor at VDS = 25 V, capacitance up to 200 V is in agreement with data reported in for frequencies starting from 560 Hz, the device showed a datasheet, which shows the validity of measurements.
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