The Future of Semiconductor Industry – a Foundry's Perspective

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The Future of Semiconductor Industry – A Foundry's Perspective –

Dr. F.C. Tseng Vice Chairman TSMC January 24, 2008

z Semiconductor Market Outlook z Challenges and Solutions

Economic Technology z Summary

Year Growth

60% ’02 +1%

40% ’03 +18% 21% 16% ’04 +28% 20% ~8% 5% ’05 +7% Growth 0% ’06 +9%

-20% ’07 +4% ’08E +7~9% -40% ‘70 ‘75 ‘80 ‘85 ‘90 ‘95 ‘00 ‘05 ‘10 ‘15 Year Source: SIA

Increasing semiconductor penetration in electronics

Data Processing 20.9% 27.2% 28.8%

Communications 13.5% 16.4% 18.8%

Consumer 12.6% 16.3% 19.5% Electronics

‘01 ‘05 ‘10E Year

Source: WSTS, IC Insights, TSMC estimates

LCD Mobile Automotive Headset

? ? ? 1.3x$95B $1,025B $77B 1.8x $61B 10x $33B $98B LC LC FH u LC Co Luxur In 4G 2. 3G HD 5G te D D D m llig D p y a e c n t

Source: Gartner, iSuppli, Strategy Analytics t

100

1 Consumer PC Electronics End User (3C Convergence) 1/100

Units / Minicomputer

1/10000 Mainframe

‘70 ‘80 ‘90 ‘00 ‘10 Year

More Functionality 9 Voice 9 Video 9 Voice 9 Messenger Functionality 9 SMS 9 GPS 9 Voice 9 WAP 9 Wi-Fi 9 Camera 9 PDA 9 MP3 ‘90 ‘00‘ ‘05 Year

9 Voice

9 Voice Lower

Price Price

INTEL ASUS One Laptop Per Child “ClassMate” “Eee” “XO”

Product Focus Population (millions) Feature-rich & connected Advanced 800

/ e r tu e a c Emerging e n 1,500 F a m / m u e r tr ic fo c r r e P e p P S Developing (Base of the Pyramid) 4,000 Basic functions

Source: “The fortune at the bottom of the pyramid” by C. K. Prahalad, and IMF

265

255 US Semi / Person = ~$250 245

11 65

10 55

9 45

8 35 Semi $ / Person 7 25 China & India Semi / Person = ~$20 6 15

World Population (Billion) 5 5

4 -5 ‘80 ‘85 ‘90 ‘95 ‘00 ‘05 ‘10 World Population Worldwide average semiconductor $ per person

Source: US Census Bureau; IC-Insights; TSMC estimates

z Semiconductor Market Outlook z Challenges and Solutions

Economic Technology z Summary

Economic Technology

1. Huge CapEx 4. Nanometer Manufacturing 2. ROI Risk – Process 5. Nanometer Design 3. ROI Risk – Product 6. Design Complexity

z Capital expenditure for constructing a new fab is rapidly increasing

Major factor for financing and future profit

$8B ? (GigaFab with 10 100K WPM)

$3B 5 (30K WPM) $0.4B $1B (20K WPM) Capital cost of fab ($B) (20K WPM) 0 6-inch 8-inch 12-inch 18-inch

z Many IDMs are changing to either fab-lite of fabless z A wide variety of consolidation and collaboration are inevitable

PastPast PresentPresent FutureFuture Design Product IP Fabless IP Design Focused Vendor Fabless Product Vendor Service IDM Foundry Few Manufacturer IDM Foundries Getting Few Assembly Distribution Fab-lite Assembly IDMs & Test & Test OEM

Vertically IDMs in Transition, Few IDMs & Foundries, Integrated Fabless Getting Bigger Many Fabless

© 2007 TSMC, Ltd 2. ROI Risk – Process Proprietary & Confidential z Incremental challenges in developing next generation processes z Process technology development costs are continuously increasing 2.0 ?

1.5 $1.4B $1.1B $0.9B

lopment cost ($B) 1.0 e $0.7B $0.5B 0.5

Technology dev 0.13um 90nm 65nm 45nm 32nm 22nm Development Cost Ramp-up Cost 15

In-house manufacturing Foundry has the economy of scale with limited products 100% 0.13um 90% 90nm 0.25µm 65nm 80% 0.18µm 0.13µm 90nm 45nm 70% 65nm 32nm 25%25% Q-Q-to-Qto-Q

Normalized Yield 60% ImprovementImprovement

50% 12Year ’98 ’99 ’00 ’01 ’02 ’03 ’04 ’05 ’06 ’07

z Collaboration is required to overcame ever – increasing financial as well as technical challenges IMEC

Matsushita

IDM

IP & Design Service EDA

Foundries

40M 40 80 $70M

30 27M 60 $48M

20 40 16M Gate Count (M) Design Cost ($M) 10 9M $18M 20 $9.2M

0.13um 90nm 65nm 45nm Gate Count Design Cost

z Optimal system partition z Foundry

Design Infrastructure

SPICE

PDK

Foundation IP Prototyping

Cybershuttle

MLM

Minimize the product risk and NRE

z New materials and device structure

High-K gate dielectric Metal gate 3D FINFET Low-K Interconnect z New EDA solutions for technology modeling and advanced lithography

z Secure accurate SPICE modeling STI Systematic WPE effect Strained silicon effect Accuracy OPC Random Corner model effect Statistical model z Modeling in new material, 3D device and equipment / topography z Polarization, OPC, double exposure and mask 3D effects

Collaborate with EDA vendors to achieve seamless interfacing hierarchy

z Increasing systematic / parameter / random yield loss due to process variation

Physical patterning effects, open and short, etc. Chemical and mechanical impact, planarity, antenna effect, and via opens, etc. Timing, signal integrity and voltage drop z Increasing leakage (quantity, source, variation)

Physical DFM Identify hot spot, fix it and improve geometric yield.

Electrical DFM Identify electrical performance deviation, correct it and improve paramedic yield

Yield

CAA/LPC Statistic Design

STA CMP

Time Set-up standard interface between phase and design which is design and layout phase

z Foundry to set up DFM ecosystem and open license DUF to reduce cost z Standard interface between the design infrastructure and manufacturing

Example:

TSMC/GUC + EDA Alliance IP/Lib Alliance TSMC DCA Alliance

TSMC DFM Compliance Initiative

© 2007 TSMC, Ltd Solution – Low Power Proprietary & Confidential z Aggressively develop integrated low power solutions for dynamic and leakage power reduction Low power process Advanced processes with ELK/XLK die-electric: lower voltage, smaller geometry and capacitance for dynamic power reduction HK/MG and gate CD bias for leakage reduction Low power IP Full set of low power foundation IP, dual power SRAM Low power design Reference Flow Silicon proven design methodologies for TSMC IP and processes Voltage scaling (DVFS, AVS), power gating with data retention Low power design automation enabling Develop vertically integrated solution from system-level to layout and to process

Communication Device 4G Mobile Multimedia Device Full HD

Moore’s Law HD 3G

Complexity Current Design Productivity D1

VGA

‘95 ‘00 ‘05 ‘10 ‘15 ‘20 Year 27

GPrime Platform DDireirectct VectVectoror LocaLocall StStataticic SDRSDRAAMM Memory Interrupt Memory Memory Controller CPCPUU Memory Interrupt Memory Memory Controller AcAccecessss ControlControllerlerControlControllerlerControlControllerler (4(4--CCH)H) APAPBB BrBrididggee Electronic AAMMBBAA M Muultlti-i-lalayyeerr A AHHBB Main Stream AMAMBBAA A APPBB System

DAI KB DAI PWM GPIO KB WDT I2C Timer SSI RTC UART (I2S) PWM GPIO MOUSE WDT I2C Timer SSI RTC UART Level (ESL) (I2S) MOUSE

z Architecture Exploration z Software Profiling z Hardware Profiling ICE z Power Estimation

Network

z New ESL design technology to address design complexity, and to provide massively parallel heterogeneous MPSOC design z SIP and 3D packaging can integrate large capacity memory and analog circuit with short time to market and low cost z Develop product with chip and PC board at same time to improve success rate

Collaborate with EDA vendors

z Semiconductor market growth will continue but moderate z Future growth opportunities will be global but bifurcate z High ROI risks in design, fab, and technology could be alleviated with the integrated foundry model z Close collaboration is required between EDA vendors, foundry and IC companies

Thank You