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The UCLA Fixed-Plus-Variable (F+V) Structure Computer

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The UCLA Fixed-Plus-Variable (F+V) Structure Computer Reconfigurable Computer Origins: The UCLA Fixed-Plus-Variable (F+V) Structure Computer Gerald Estrin University of California at Los Angeles Gerald Estrin and his group at the University of California at Los Angeles did the earliest work on reconfigurable computer architectures. The early research, described here, provides pointers to work on models and tools for reconfigurable systems design and analysis. The earliest work on reconfigurable computer Pasta’s challenge architecture was done at the University of What triggered the UCLA work on reconfig- California at Los Angeles (UCLA), as a 1999 urable computer systems? In the spring of report in The Economist noted (see “The 1959, John Pasta, a highly respected applied Economist: Reconfigurable Systems Undergo mathematician and physicist and chairman of Revival” sidebar, p. 4). Clearly, in retrospect, the Mathematics and Computer Science digital technology was not ready for such a rev- Research Advisory Committee to the Atomic olutionary change. Now that digital technolo- Energy Commission, expressed concern about gy is enabling commercial realization, however, many vital computational problems whose the time seems right to tell this story. Of equal solutions were beyond the capabilities of exist- interest might be the saga of how a professor ing electronic computers. In his opinion, com- and his graduate students, in an academic set- mercial computer manufacturers had lost ting, can work on one complex problem over a interest in exploring risky, innovative comput- prolonged period and bring to the computer er architectures. Instead, the manufacturers science world original ideas that can them- wanted to serve the growing market for con- selves be commercially realized. This is a ventional computer systems. Consequently, process unique to academia where the research when Pasta visited me at UCLA, he challenged of students and faculty is not judged by its me to propose new ways to organize computer immediate applicability but instead by its cre- systems in the hope that research advances in ativity and the cumulative impact of discov- the public domain would lead to a surge of ered side effects. computer development in the private domain. My first attempts at telling this tale were Pasta’s challenge to me was timely. I had overwhelmed by the duration of the research come to UCLA from von Neumann’s Electronic program multiplied by the productivity of the Computer Project at the Institute for Advanced researchers. Telling everything made it too deep Study in Princeton1 after directing construction and narrow. I have instead highlighted the of a von-Neumann-type computer at Israel’s research goals and the issues they exposed. I Weizmann Institute of Science.2 Both projects begin with the challenge that triggered my pro- sought to solve problems in applied mathemat- posal for a reconfigurable computer structure ics and applied physics. The projects motivated in the first place, then reveal the issues and sup- me to explore computational concurrency, port that kept our research productive for which had been made more feasible by new almost three decades. In an attempt to avoid semiconductor technology. They also opened encumbering the reader with an outlandishly the door to departures from the conventional long bibliography, I have been arbitrarily selec- von Neumann machine architecture.3 tive and possibly unscholarly. I count on mod- When I joined the UCLA engineering facul- ern Internet search tools to help the reader’s ty in the fall of 1956, I was partially supported search for more source materials. by the Department of Mathematics’ Numerical IEEE Annals of the History of Computing 1058-6180/02/$17.00 © 2002 IEEE 3 Reconfigurable Computer Origins Analysis Research Laboratory. NARL was The Economist: responsible for applied mathematics research Reconfigurable Systems Undergo Revival and for the Standards Western Automatic On 22 May 1999, The Economist (vol. 351, no. 8120, p. 89) Computer (SWAC), whose development had reported the following. been completed by Harry Huskey in 1952. C.B. Tompkins, head of NARL, had joined In 1960 Gerald Estrin, a computer scientist at the University of California, Engineering Dean L.M.K. Boelter to aggressive- Los Angeles, proposed the idea of a “fixed plus variable structure ly recruit me. During 1957, I was visited by computer”. It would consist of a standard processor, augmented by an Marshall Yovits, a program manager from the array of “reconfigurable” hardware, the behavior of which could be Office of Naval Research (ONR). He suggested controlled by the main processor. The reconfigurable hardware could be that I submit a proposal seeking support for my set up to perform a specific task, such as image processing or pattern- research at UCLA. In May 1958, I was awarded matching, as quickly as a dedicated piece of hardware. Once the task a contract for research in digital technology. was done, the hardware could be rejigged to do something else. The That ONR contract enabled me, in turn, to sup- result ought to be a hybrid computer combining the flexibility of software port research by graduate students and, in the with the speed of hardware. summer of 1959, to totally immerse myself in Although Dr. Estrin built a demonstration machine, his idea failed to considering John Pasta’s challenge to extend catch on. Instead, microprocessors proved to be cheap and powerful the capabilities of electronic digital computers. enough to do things on their own, without any need for reconfigurable hardware. But recently Dr. Estrin’s idea has seen something of a Reconfigurable architecture response renaissance. The first-ever hybrid microprocessor, combining a I presented the first results of my brain- conventional processor with reconfigurable circuitry in a single chip, was storming at the May 1960 Western Joint launched last month. Several firms are now competing to build Computer Conference in a paper titled reconfigurable chips for use in devices as varied as telephone exchanges, “Organization of Computer Systems—The televisions and mobile telephones. And the market for them is expected Fixed Plus Variable Structure Computer.”4 to grow rapidly. Jordan Selburn, an analyst at Gartner Group (an Figure 1, from that paper, illustrates the rela- American information-technology consultancy), believes that annual sales tions between a fixed general-purpose comput- of reconfigurable chips will increase to a value of around $50 billion in er (labeled F) and a variable structure inventory 10 years time. of reconfigurable building blocks (labeled V). The “Reconfigurable Architecture Defined” sidebar quotes from that paper to highlight the primary goal of the proposed new architecture. Our reconfigurable computer sys- tems research at UCLA sought a new way to evolve higher performance computing from any general-purpose computer. Starting in 1959, we tried to design special-purpose subsystems that could run concurrently with programs in a coupled general- purpose computer. We developed “miniaturized” circuit modules and a removable, replaceable etched signal harness (see Figure 2). We were aware of the gap between available tech- nology and our needs for more auto- matic electronic control, but the inexorable advances in semiconduc- tor technology were already evident. We had many other computer sci- ence and computer engineering issues to deal with if reconfigurable systems were to be realizable. The “Early Researchers” sidebar (on p. 6) Figure 1. This diagram shows the relations between the fixed machine, the highlights the earliest investigations variable structure part, the input-output, the supervisory control, and the in our group and offers some person- humans. (Courtesy of the 1960 Western Joint Computer Conference.) al insight about them. 4 IEEE Annals of the History of Computing Reconfigurable Architecture Defined The following excerpt is from a 1960 con- ference paper1 describing my initial thinking on reconfigurable architectures. The goal was (a) … to permit computations which are beyond the capabilities of present systems by providing an inventory of high speed substructures and rules for interconnecting them such that the entire system may be temporarily distorted into a problem oriented special purpose computer. The fixed plus variable structure computer will (b) consist of a set of independent digital complexes ranging in size from individual switching elements or flip-flops to, say shift registers and counters to a high speed general purpose computer. The latter element is “fixed” in the sense that the machine user is presented with some minimum vocabulary and some minimum set of machine characteristics which do not change rapidly with time and which do not require the specification of some variable set of interconnections for each problem. The existence of the “fixed” general purpose (c) computer as an element in the system is considered essential to the evolution of higher level languages for man-machine communi- cation. If either the instruction code were always changing or the meaning of the instructions were always changing, any tendency for humans to invest effort in the definition of more complex instructions would be quickly damped despite the ability to make use of the variable structure inventory to effect higher language operations. If it is found that a number of the inventory items is used very frequently, then it may be desirable to introduce that assembly as a (d) separate inventory item with speed-optimized fixed wiring. In fact over longer periods, it may Figure 2. Basic reconfigurable modules (a), motherboard (b), wiring be observed that some substructures are used so harness for the motherboard (c), and system assembly constructed for frequently that they should be part of the “fixed” the supervisory control and transfer path between the fixed and structure general purpose computer so that variable structure computers. The author is shown using an oscillo- there is no need to explicitly specify the scope probe to observe electrical activity of the system assembly (d). substructure each time it is used. (Courtesy of IEEE.) Reference 1.
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