Clock Jitter

Introduction to the World of Analogue-to-Digital Conversion

ADC

Shraga Kraus

Analogue and Mixed Signal Haifa Research Laboratory Contents

• Introduction to A/D Conversion • Building Blocks • Basic Architectures • More Advanced Architectures • The ΔΣ Architecture

• Analogue signal: – Continuous in time – Continuous in value (within its range of existence)

• Digital signal: – Discrete in time – Discrete in value

• Conversion 1: Sampling – Continuous time  discrete time – Creates aliasing

• Conversion 2: Quantisation – Continuous value  discrete value – Creates quantisation noise

• Sampling = multiplication by an impulse train • Y(t) = X(t) · S(t)

• Ts = sampling interval

• fs = 1/Ts = sampling frequency

• In the frequency domain: • Y(f) = X(f) * S(f)

• “Aliasing” is evident

• Nyquist sampling:

• Over- sampling:

• Under- sampling:

• Nyquist sampling:

–fs –fs/2 0 fs/2 fs • Over- sampling:

–fs –fs/2 0 fs/2 fs • Under- sampling:

–fs –fs/2 0 fs/2 fs

• fs = 20 MHz • ADC’s output contains information up to 10 MHz • 13 MHz folds to 7 MHz

• fs = 20 MHz • ADC’s output contains information up to 10 MHz • 23 MHz folds to 3 MHz

• Never use your ADC at full Nyquist

• A rule of These interferers can thumb: be removed digitally over sampling ratio (OSR) of 2 is minimal

• Δ = LSB • m = number of bits 7 • Full scale 6 A amplitude: 5 4 2m 0 3 A  2 2 1 Δ 0

• If the input signal is not synchronised with the sampling clock, the error is uniformly distributed between –Δ/2 and +Δ/2

• In this case, the ADC is modelled as a linear system with noise • The noise comes from the quantisation process

• If we refer the noise to the input: • At every sampling moment a small noise is added to the input signal, bringing it to the centre of the quantisation range

• The input signal a sinusoidal wave not synchronised with the sampling clock, with a full-scale amplitude • Quantisation error distribution is:

Fqn 1/Δ

x –Δ/2 0 +Δ/2

• Signal power:

m 2 12 1 2 2 2m 3 PAsig      2 2 2 2

• Quantisation noise power:

  221 1 1 32 P F x x22 dx  x dx     qn qn     3 4 12 22

• SNR: P 223 2m 3 SNR sig   22m P 2 2 qn 12

SNRdB 10log10  SNR  6.02 m  1.76

• Effective number of bits (ENOB):

SNR 1.76 ENOB  dB 6.02

• In practice, another noise mechanisms exist in the ADC • Thermal / shot noise • Nonlinearity (not strictly a noise, but contributes to non-signal power) • To get the practical resolution of an ADC, the signal to noise-and-distortion ratio (SNDR) should be derived

• For a given SNDR of an ADC, the effective resolution is:

푆푁퐷푅 − 1.76 퐸푁푂퐵 = 푑퐵 6.02 • The above is valid for a full-scale sinusoidal continuous wave input • This test setup is feasible using standard lab equipment

• Simulation of an ideal 7-bit ADC

Quantisation noise is approximately Quantisation noise white spectral density is

(as expected 2 ∆ from a unifor- 12 mly distributed 푓푠 noise) 2

• SNR = 43.8 dB  ENOB = 7

• Out-of-band noise is filtered out digitally

푆푁퐷푅 − 1.76 퐸푁푂퐵 = 푑퐵 6.02

• OSR = 2  SNR x2 (+3dB)  ENOB += ½

• 6½ decimal digits = 106.5 levels

• 7½ bits (binary digits) = 27.5 levels

INL is the horizontal distance between the actual and ideal curves. output code Usually expressed in units of Δ. 7 6 5 4 3 2 1

0 Vin 0 Vref

DNL is the difference between the actual and ideal step widths. output code Usually expressed in units of Δ. 7 6 5 4 3 2 1

0 Vin 0 Vref

• INL and DNL provide a lot of information on what’s going on inside the ADC

• Analysis of the data depends on the structure of the specific ADC being tested

• Jitter = the time domain equivalent of phase noise • Clock jitter = changes in clock period • Deterministic / random jitter

• Clock jitter results in sampling the wrong value

The higher the slope of the signal, the larger the error

• fsig = input signal frequency

• Tj,RMS = random clock jitter RMS (in unit time)

• SNRj = SNR of an ADC as if clock jitter was the only noise source

1 푆푁푅푗 = 2휋 ∙ 푓푠푖푔 ∙ 푇푗,푅푀푆

• Clock jitter is painful in SNRj depends only on the input signal sampling of high frequency frequency, NOT sampling frequency! signals • No solution was found to date

1 푆푁푅푗 = 2휋 ∙ 푓푠푖푔 ∙ 푇푗,푅푀푆

Pure Sine

Signal Generator ADC

Signal Generator

Dual Tone

Signal Generator ADC

Signal Generator SFDR

• Introduction to A/D Conversion • Building Blocks • Basic Architectures • More Advanced Architectures • The ΔΣ Architecture

• Differential pair – When CLK = ‘1’ the input difference is amplified

• Regenerative load (positive feedback) – When CLK = ‘0’ the amplified difference if further enhanced to the rails One of many topologies, from Wikipedia – Regardless of the inputs

• Offset – Originates from mismatch in the differential pair

• Noise – Like in every active circuit – The input-referred noise may result in incorrect decision for small input difference

• Regeneration Time – The smaller the input signal, the longer the regeneration is

• Metastability – Occurs when the regeneration is too long – Adding digital buffers at the output can reduce the probability of metastability

• Hysteresis – A result of residual charge somewhere in the load network – Some circuit techniques alleviate this effect

• Consists of two cascaded latched comparators • Reduces the probability of metastability • Has constant input-to-output delay • But – the delay is long (½ clock cycle)

inp outp inp outp

CK CK inn outn inn outn

• Serves in almost every type of ADC • Based on a differential pair at the input – except of low voltage technologies, but this makes no difference for our discussion

• Offset – Originates from mismatch in the differential pair

• Noise – Like in every active circuit

• Finite Gain and Bandwidth – Feedback is imperfect, results in gain error

• Inaccurate Gain – Due to either gain error or mismatch between the feedback devices

• Settling Time – May set a limit in several architectures

NMOS

PMOS Both

• Switch resistance (“ON”) RSW depends on Vin

Vctrl = VDD ; Vctrl = 0 Both VGS = Vctrl – Vin Vin

• Nonlinear RSW results in a nonlinear voltage divider • Signal is distorted

• The gate overlaps with the areas of source and drain • In addition, the gate capacitance exists

COL G COL

S CG D

• When φ goes down, the charge in the channel is drained to both sides φ The path of the The voltage on charge depends CL changes! on the values of

VOL, CG, and tfall of the clock The exact amount of C charge is input Vin L dependent

• Keeps VGS constant • Usually incorporates a charge pump • May also include a sub circuit for alleviating charge injection effect

From P.E. Allen’s lecture notes, 2010 http://www.aicdesign.org/SC NOTES/2010notes/Lect2UP1 40_%28100325%29.pdf

• Tracks the input signal when clock is low • Freezes (“holds”) the input value upon clock rising • Uses a capacitor to store the analogue φ information (voltage)

• Charge injection by the switch • Leaky capacitor • Buffer’s nonidealities (including noise) • Total noise of the capacitor itself is 퐾푇 φ 푉2 퐶

• Introduction to A/D Conversion • Building Blocks • Basic Architectures • More Advanced Architectures • The ΔΣ Architecture

Vin

VREF • Nº of comparators = 2m – 1 • Thermometer code output Thermo- meter Dout to <2:0> • Converted to binary by Binary a simple logic • Fastest topology

• Like a bar graph indicator • The represented decimal number is the number of ‘1’s. 01 01 01 01 01 01 012345678 01 01

Vin

VREF • Many comparators – area, power • Resistor matching – area Thermo- meter Dout to <2:0> • Input capacitance Binary – requires a buffer • Comparators’ offset – Can generate bubbles

Vin

VREF • Input buffer • Resistor mismatch • Comparators’ offset Thermo- • Clock/Vin skew meter Dout to <2:0> or Binary input S&H

• Nº of comparators = 2m/2 + 1 – 2 • Reduces area and power significantly – Compared to flash vout

• In the blue zones, VREF zeros should be counted rather than ones (in ) vin VREF

• Consider an 8-bit ADC:

• A flash ADC requires 28 – 1 = 255 comparators

• A folding ADC, with 4-4 structure, requires 2 · (24 – 1) = 30 comparators

• Same as flash: the MSB flash, , must be as accurate as the LSB (Δ) – Resistor matching – Comparators’ offset • The folding amplifier, , must be as accurate as the LSB (Δ) – Transistor matching

• The folding amplifier introduces a delay and results in skew between the two flash ADCs – Significant at high frequencies – Requires introduction of a S&H at the input

• Nonlinearity of the flash ADCs – In particular • Nonlinearity of the folding amplifier • Clock/Vin skew between the two flashes or input S&H

S&H

vslope Stop!Start! VREF v • Comparator’s• Counter resetoutput to flips0 in • Counterand starts stops counting t • Slope initiates

• The slope must be calibrated – Its exact slope is unknown

• The comparator makes a decision around Vin, not around a constant voltage

– If the comparator’s offset is constant for every Vin, this only shifts the range of voltages being quantised

– If the comparator’s offset changes with Vin, this results in nonlinearity

• The S&H has its own nonidealities • The slope can be nonlinear • Incomplete capacitor discharge (“memory effect”) • It’s Slooooooooooow – 2m clock cycles / conversion

• A line of ADCs samples a line of pixels simultaneously • To implement the line: – One slope for the entire line – One counter for the entire line or a counter for each ADC – A S&H, a comparator and a register for each ADC – Most CCDs do not require a S&H, though.

• Introduction to A/D Conversion • Building Blocks • Basic Architectures • More Advanced Architectures • The ΔΣ Architecture

• Starts from the MSB • Then moves on to the next stage – to extract the next bit • Meanwhile, the first stage treats the next sample

1. Decide about the MSB 2. According to the decision – magnify the appropriate range (2x, shift to centre) 3. Decide about the next bit; go to 2

–VREF/2 then C C x2 C 2 x2 1 0

‘1’ ‘0’ ‘1’

• Implemented in switched-capacitor technique • A single-stage DAC + 2x amplifier (MDAC):

Value of VREF is set according to the decision of the previous Josh comparatorCarnes and Un-Ku Moon, “The effect of switch resistance on pipelined ADC MDAC settling time”, Proc. ISCAS 2006

• During φ12: 푉표푢푡 = 2푉푖푛 − 푉푅퐸퐹

–VREF/2 then C C x2 C 2 x2 1 0

Should be ‘0’!

‘1’ ‘0’ ‘0’

• Sensitive to comparator’s offset – Solved by redundancy (next slide) • Sensitive to op amp’s offset – Solved by correlated double sampling (CDS) • Charge injection from the switches – Solved by bottom plate sampling • Gain must be exactly 2x – Limited by capacitor mismatch & op amp’s gain • Op amp’s DC gain must be high – To reduce gain error

–VREF/2 then C2B x2 C1B –VREF/4 then C0 C2A C1A x2

We’re in the lower part ‘11’ of the 3 upper values ‘01’ ‘0’  D<2:0> = ‘101

MSB = ‘1’ B1 = ? Now we have all for sure We’ll decide the information later on for making a decision

–VREF/2 then C2B x2 C1B C C0 C 1A 2A x2

‘10’ ‘00’ ‘1’

MSB = ‘1’ B1 = ‘0’ LSB = ‘1’ for sure for sure for sure

• Sensitive to comparator’s offset – Solved by redundancy • Sensitive to op amp’s offset – Solved by correlated double sampling (CDS) • Charge injection from the switches – Solved by bottom plate sampling • Gain must be exactly 2x – Limited by capacitor mismatch & op amp’s gain • Op amp’s DC gain must be high – To reduce gain error

• Gain is not exactly 2x – Capacitor mismatch – Low DC gain of the op amp (gain error) – Changes the slope of the transfer function

• Long settling time – Op amp should settle during a clock period

• Nº of comparators = 2m (due to redundancy) • Nº of MDACs = m – 1 • 1 clock cycle / conversion • Propagation delay = m clock cycles • Requires descent op amps – Not trivial in contemporary CMOS technologies

• Based upon binary search (Successive Approximation Register) • SAR = ‘10000

• DAC > Vin ? • SAR = ‘C1000

• DAC > Vin ? • SAR = ‘CC100 • And so on…

• Capacitors are charged to Vin • Charge is distributed 푆퐴푅 so that 푉 = 푉 ∙ − 푉 = 퐷퐴퐶 − 푉 − 푅퐸퐹 2푚 − 1 푖푛 푖푛

• Comparator’s offset – Solved by redundancy • Charge injection from the switches – The larger the capacitors, the smaller the effect but the slower the ADC is • Capacitor mismatch

• Low impedance sources of Vin end Vref are required

• Only one comparator • m clock cycles / conversion – Quite slow • Exponentially scaled capacitors – A lot of area • No op amp (!!!) – Attractive for contemporary CMOS technologies – Low power

• Introduction to A/D Conversion • Building Blocks • Basic Architectures • More Advanced Architectures • The ΔΣ Architecture

• Over sampling – Relatively high OSR • Noise shaping – Quantisation noise is attenuated at the frequencies of interest – It is amplified, on the other hand, at other frequencies • Feedback structure

• N = loop resolution [bits] • M = final resolution [bits] “Quantiser”

For the sake of clarity we will discuss

Loop Filter low pass ΔΣ ADC only

Loop filter of a Quantisation • Linear Model: low pass ΔΣ noise of the quantiser

• Loop equation: 푌 = 푋푧−1 + 퐸 1 − 푧−1

• Signal Transfer Function (STF): 푌 Delay 푆푇퐹 = = 푧−1 푋 퐸=0 • Noise Transfer Function (NTF): 푌 푁푇퐹 = = 1 − 푧−1 High pass filter 퐸 푋=0 • Substituting z = ej·2πf in NTF we get:

푁푇퐹 푓 2 = 2sin 휋푓 2 Indeed, a high pass filter f is normalized:

Quantisation noise is amplified at high frequencies

Quantisation noise is Quantisation attenuated at low noise of high frequencies frequencies can be filtered out digitally

OSR = 16 The grey noise is filtered out digitally (decimation filter)

Here, where our signal resides, the quantisation noise is significantly attenuated

• In a “standard” Nyquist ADC: – OSR = 16  ENOB += 2

• A 1-bit ADC with OSR = 16: – ENOB = 3

• A 1-bit 1st order ΔΣ ADC with OSR = 16: – ENOB = 6.4

• Recall the scheme of a feedback system:

B • The closed loop gain is approximately 1/B – Every pole in B becomes a zero – Every zero in B becomes a pole

• In the signal path, the loop filter serves as the amplifier, and there is unity feedback:

• The signal passes as is, with the integrator limiting its bandwidth

• In the error path, the loop filter serves as the feedback, and there is a unity amplifier:

• The closed loop gain is a high pass filter

• N = loop resolution [bits] • M = final resolution [bits]

Two feedback loops

• Linear Model:

• Loop equation: 푌 = 푋푧−1 + 퐸 1 − 푧−1 2

• Signal Transfer Function (STF): 푌 푆푇퐹 = = 푧−1 푋 퐸=0 • Noise Transfer Function (NTF): 푌 푁푇퐹 = = 1 − 푧−1 2 퐸 푋=0 • Substituting z = ej·2πf in NTF we get: 푁푇퐹 푓 2 = 2sin 휋푓 4

Quantisation noise is OSR x 2  attenuated st stronger + 1.3 bit (1 order) + 1.7 bit (2nd order) + 1.9 bit (3rd order) + 2.1 bit (4th order)

• Higher loop orders are possible. However: • Up to 2nd order the modulator is unconditionally stable – If the linear model shows that the modulator is stable, it will be stable for every input signal • From 3rd order and above the modulator is conditionally stable – Even if the linear model shows that the modulator is stable, it might become unstable for certain input signals

Never do anything not understanding what you’re doing