Introduction to the World of Analogue-to-Digital Conversion ADC Shraga Kraus Analogue and Mixed Signal Haifa Research Laboratory Contents • Introduction to A/D Conversion • Building Blocks • Basic Architectures • More Advanced Architectures • The ΔΣ Architecture ©2016 Copyright Shraga Kraus «2» Contents • Introduction to A/D Conversion • Building Blocks • Basic Architectures • More Advanced Architectures • The ΔΣ Architecture ©2016 Copyright Shraga Kraus «3» Introduction to A/D Conversion ©2016 Copyright Shraga Kraus «4» Types of Signals • Analogue signal: – Continuous in time – Continuous in value (within its range of existence) • Digital signal: – Discrete in time – Discrete in value ©2016 Copyright Shraga Kraus «5» The Two Conversions • Conversion 1: Sampling – Continuous time discrete time – Creates aliasing • Conversion 2: Quantisation – Continuous value discrete value – Creates quantisation noise ©2016 Copyright Shraga Kraus «6» Sampling • Sampling = multiplication by an impulse train • Y(t) = X(t) · S(t) • Ts = sampling interval • fs = 1/Ts = sampling frequency Ts t ©2016 Copyright Shraga Kraus «7» Sampling in the Frequency Domain • In the frequency domain: • Y(f) = X(f) * S(f) • “Aliasing” is evident ©2016 Copyright Shraga Kraus «8» Over/Under Sampling • Nyquist sampling: • Over- sampling: • Under- sampling: ©2016 Copyright Shraga Kraus «9» Information at the Output • Nyquist sampling: –fs –fs/2 0 fs/2 fs • Over- sampling: –fs –fs/2 0 fs/2 fs • Under- sampling: –fs –fs/2 0 fs/2 fs ©2016 Copyright Shraga Kraus «10» “Folding” the Frequency Axis ©2016 Copyright Shraga Kraus «11» Finding the Final Frequency ©2016 Copyright Shraga Kraus «12» Example 1: f = 13 MHz • fs = 20 MHz • ADC’s output contains information up to 10 MHz • 13 MHz folds to 7 MHz ©2016 Copyright Shraga Kraus «13» Example 2: f = 23 MHz • fs = 20 MHz • ADC’s output contains information up to 10 MHz • 23 MHz folds to 3 MHz ©2016 Copyright Shraga Kraus «14» Anti-Aliasing Filter • Never use your ADC at full Nyquist • A rule of These interferers can thumb: be removed digitally over sampling ratio (OSR) of 2 is minimal ©2016 Copyright Shraga Kraus «15» Quantisation • Δ = LSB • m = number of bits 7 • Full scale 6 A amplitude: 5 4 2m 0 3 A 2 2 1 Δ 0 ©2016 Copyright Shraga Kraus «16» Quantisation Error • If the input signal is not synchronised with the sampling clock, the error is uniformly distributed between –Δ/2 and +Δ/2 t ©2016 Copyright Shraga Kraus «17» ADC model • In this case, the ADC is modelled as a linear system with noise • The noise comes from the quantisation process • If we refer the noise to the input: • At every sampling moment a small noise is added to the input signal, bringing it to the centre of the quantisation range ©2016 Copyright Shraga Kraus «18» A Test Case: Continuous-Wave • The input signal a sinusoidal wave not synchronised with the sampling clock, with a full-scale amplitude • Quantisation error distribution is: Fqn 1/Δ x –Δ/2 0 +Δ/2 ©2016 Copyright Shraga Kraus «19» Signal and Noise Power • Signal power: m 2 12 1 2 2 2m 3 PAsig 2 2 2 2 • Quantisation noise power: 221 1 1 32 P F x x22 dx x dx qn qn 3 4 12 22 ©2016 Copyright Shraga Kraus «20» Signal and Noise Power • SNR: P 223 2m 3 SNR sig 22m P 2 2 qn 12 SNRdB 10log10 SNR 6.02 m 1.76 • Effective number of bits (ENOB): SNR 1.76 ENOB dB 6.02 ©2016 Copyright Shraga Kraus «21» Practical ENOB • In practice, another noise mechanisms exist in the ADC • Thermal / shot noise • Nonlinearity (not strictly a noise, but contributes to non-signal power) • To get the practical resolution of an ADC, the signal to noise-and-distortion ratio (SNDR) should be derived ©2016 Copyright Shraga Kraus «22» Derivation of ENOB • For a given SNDR of an ADC, the effective resolution is: 푆푁퐷푅 − 1.76 퐸푁푂퐵 = 푑퐵 6.02 • The above is valid for a full-scale sinusoidal continuous wave input • This test setup is feasible using standard lab equipment ©2016 Copyright Shraga Kraus «23» Simulation Example • Simulation of an ideal 7-bit ADC Quantisation noise is approximately Quantisation noise white spectral density is (as expected 2 ∆ from a unifor- 12 mly distributed 푓푠 noise) 2 • SNR = 43.8 dB ENOB = 7 ©2016 Copyright Shraga Kraus «24» Simulation Example - Oversampling • Out-of-band noise is filtered out digitally 푆푁퐷푅 − 1.76 퐸푁푂퐵 = 푑퐵 6.02 • OSR = 2 SNR x2 (+3dB) ENOB += ½ ©2016 Copyright Shraga Kraus «25» What is ½ Bit? • 6½ decimal digits = 106.5 levels • 7½ bits (binary digits) = 27.5 levels ©2016 Copyright Shraga Kraus «26» Integral Nonlinearity INL is the horizontal distance between the actual and ideal curves. output code Usually expressed in units of Δ. 7 6 5 4 3 2 1 0 Vin 0 Vref ©2016 Copyright Shraga Kraus «27» Differential Nonlinearity DNL is the difference between the actual and ideal step widths. output code Usually expressed in units of Δ. 7 6 5 4 3 2 1 0 Vin 0 Vref ©2016 Copyright Shraga Kraus «28» Nonlinearity Information • INL and DNL provide a lot of information on what’s going on inside the ADC • Analysis of the data depends on the structure of the specific ADC being tested ©2016 Copyright Shraga Kraus «29» Clock Jitter • Jitter = the time domain equivalent of phase noise • Clock jitter = changes in clock period • Deterministic / random jitter ©2016 Copyright Shraga Kraus «30» Sampling With Clock Jitter • Clock jitter results in sampling the wrong value The higher the slope of the signal, the larger the error ©2016 Copyright Shraga Kraus «31» Effect of Clock Jitter • fsig = input signal frequency • Tj,RMS = random clock jitter RMS (in unit time) • SNRj = SNR of an ADC as if clock jitter was the only noise source 1 푆푁푅푗 = 2휋 ∙ 푓푠푖푔 ∙ 푇푗,푅푀푆 ©2016 Copyright Shraga Kraus «32» Meaning of Clock Jitter • Clock jitter is painful in SNRj depends only on the input signal sampling of high frequency frequency, NOT sampling frequency! signals • No solution was found to date 1 푆푁푅푗 = 2휋 ∙ 푓푠푖푔 ∙ 푇푗,푅푀푆 ©2016 Copyright Shraga Kraus «33» Lab Characterisation - SNR Pure Sine Signal Generator ADC Signal Generator ©2016 Copyright Shraga Kraus «34» Lab Characterisation - SNDR Dual Tone Signal Generator ADC Signal Generator SFDR ©2016 Copyright Shraga Kraus «35» Contents • Introduction to A/D Conversion • Building Blocks • Basic Architectures • More Advanced Architectures • The ΔΣ Architecture ©2016 Copyright Shraga Kraus «36» Building Blocks ©2016 Copyright Shraga Kraus «37» Latched Comparator • Differential pair – When CLK = ‘1’ the input difference is amplified • Regenerative load (positive feedback) – When CLK = ‘0’ the amplified difference if further enhanced to the rails One of many topologies, from Wikipedia – Regardless of the inputs ©2016 Copyright Shraga Kraus «38» Comparator’s Nonidealities • Offset – Originates from mismatch in the differential pair • Noise – Like in every active circuit – The input-referred noise may result in incorrect decision for small input difference ©2016 Copyright Shraga Kraus «39» Comparator’s Nonidealities • Regeneration Time – The smaller the input signal, the longer the regeneration is • Metastability – Occurs when the regeneration is too long – Adding digital buffers at the output can reduce the probability of metastability ©2016 Copyright Shraga Kraus «40» Comparator’s Nonidealities • Hysteresis – A result of residual charge somewhere in the load network – Some circuit techniques alleviate this effect ©2016 Copyright Shraga Kraus «41» Master-Slave Comparator • Consists of two cascaded latched comparators • Reduces the probability of metastability • Has constant input-to-output delay • But – the delay is long (½ clock cycle) inp outp inp outp CK CK inn outn inn outn ©2016 Copyright Shraga Kraus «42» More Information ©2016 Copyright Shraga Kraus «43» Op Amp • Serves in almost every type of ADC • Based on a differential pair at the input – except of low voltage technologies, but this makes no difference for our discussion ©2016 Copyright Shraga Kraus «44» Op Amp’s Nonidealities • Offset – Originates from mismatch in the differential pair • Noise – Like in every active circuit • Finite Gain and Bandwidth – Feedback is imperfect, results in gain error ©2016 Copyright Shraga Kraus «45» Op Amp’s Nonidealities • Inaccurate Gain – Due to either gain error or mismatch between the feedback devices • Settling Time – May set a limit in several architectures ©2016 Copyright Shraga Kraus «46» More Information ©2016 Copyright Shraga Kraus «47» MOS Switch NMOS PMOS Both • Switch resistance (“ON”) RSW depends on Vin Vctrl = VDD ; Vctrl = 0 Both VGS = Vctrl – Vin Vin ©2016 Copyright Shraga Kraus «48» What’s the Problem With That? • Nonlinear RSW results in a nonlinear voltage divider • Signal is distorted ©2016 Copyright Shraga Kraus «49» Parasitic Capacitances • The gate overlaps with the areas of source and drain • In addition, the gate capacitance exists COL G COL S CG D B ©2016 Copyright Shraga Kraus «50» Charge Injection • When φ goes down, the charge in the channel is drained to both sides φ The path of the The voltage on charge depends CL changes! on the values of VOL, CG, and tfall of the clock The exact amount of C charge is input Vin L dependent ©2016 Copyright Shraga Kraus «51» Bootstrapped Switch • Keeps VGS constant • Usually incorporates a charge pump • May also include a sub circuit for alleviating charge injection effect From P.E. Allen’s lecture notes, 2010 http://www.aicdesign.org/SC NOTES/2010notes/Lect2UP1 40_%28100325%29.pdf ©2016 Copyright Shraga Kraus «52» More Information ©2016 Copyright Shraga Kraus «53» Sample & Hold / Track & Hold • Tracks