ECE1371 Advanced Analog Circuits

Lecture 7 Amplifier Design 1

Trevor Caldwell [email protected] Lecture Plan

Date Lecture (Wednesday 2-4pm) Reference Homework 2020-01-07 1 MOD1 & MOD2 PST 2, 3, A 1: Matlab MOD1&2 2020-01-14 2 MODN +  Toolbox PST 4, B 2:  Toolbox 2020-01-21 3 SC Circuits R 12, CCJM 14 2020-01-28 4 Comparator & Flash ADC CCJM 10 3: Comparator 2020-02-04 5 Example Design 1 PST 7, CCJM 14 2020-02-11 6 Example Design 2 CCJM 18 4: SC MOD2 2020-02-18 Reading Week / ISSCC 2020-02-25 7 Amplifier Design 1 2020-03-03 8 Amplifier Design 2 2020-03-10 9 Noise in SC Circuits 2020-03-17 10 Nyquist-Rate ADCs CCJM 15, 17 Project 2020-03-24 11 Mismatch & MM-Shaping PST 6 2020-03-31 12 Continuous-Time  PST 8 2020-04-07 Exam 2020-04-21 Project Presentation (Project Report Due at start of class)

2 ECE1371 Circuit of the Day: Cascode Current Mirror

• How do we bias cascode transistors to optimize signal swing? • Standard cascode current mirror wastes too much swing

VX = VEFF + VT

VY = 2VEFF + 2VT

Minimum VZ is 2VEFF + VT, which is VT larger than necessary

3 ECE1371 What you will learn…

• Choice of VEFF Several trade-offs with Noise, Bandwidth, Power,… • Amplifier Topology • Amplifier Settling Dominant Pole, Zero and Non-Dominant Pole • Gain-Boosting Stability, Pole-Zero Doublet • Delaying vs. Non-Delaying stages

4 ECE1371 Choice of Effective Voltage

• Effective Voltage VEFF = VGS -VT

2IDD 2I VEFF  g  C W m nox L

Assumes square-law model In weak-inversion, this relationship will not hold

• What are the trade-offs when choosing an appropriate effective voltage? Noise Power Bandwidth Matching Linearity Swing

5 ECE1371 Thermal Noise and VEFF • Noise Current and Noise Voltage

2 2 4kT IkTgnm 4  Vn  gm • Ex. Common Source with transistor load CS transistor has input referred noise voltage proportional to VEFF

2 4kT VVnEFF ,1 2ID Current source has input referred noise voltage inversely proportional to VEFF 2 2 4kT VEFF,1 Vn  2IVDEFF,2

6 ECE1371 Thermal Noise and VEFF

2 B n,2

2 IN n,1

• Total Noise

2 4kT VEFF,1 VVnEFF,1 1 2IVDEFF,2

Use small VEFF for input transistor, large VEFF for load (current source) transistor

7 ECE1371 Bandwidth and VEFF • Bandwidth dependent on transistor unity gain frequency fT

gm fT  2( CCGS GD )

If CGS dominates capacitance 1.5 fV n TEFF2 L2

Small L, large  maximizes fT

For a given current, decreasing VEFF increases W, increases CGS, and slows down the transistor

• fT increases with VEFF

8 ECE1371 Linearity and VEFF • Look at distortion through a CS amplifier Compare amplitude of fundamental and second-order distortion term

1 W 2 ICVVtcos( ) DnoxEFFA2 L WW1 ICVV cos( t )  CV 2  1  cos(2 t ) noxLL EFFA4 nox A    VVFHD2

VV HD2 A OUT VVFEFF4

IN D

• Linearity increases with VEFF

9 ECE1371 Power and VEFF

• Efficiency of a transistor is gm/ID Transconductance for a given current – high efficiency results in lower power

Bipolar devices have gm=IC/Vt, while (square-law) MOS devices have gm=2ID/VEFF

30

• VEFF is inversely 25

proportional to gm/ID 20 D

Increasing V reduces /I 15

EFF m efficiency of the transistor g 10 Biasing in weak inversion increases efficiency 5 0 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 V -V GS T

10 ECE1371 Matching and VEFF

• With low VEFF, transistor is in weak inversion

What happens with mismatch in Vt?

• Use a current-mirror as an example with mismatched threshold voltages

IN OUT

t,1 t,2

11 ECE1371 Matching and VEFF

• In strong inversion with Vt mismatch there is a quadratic relationship 2 IOUT ()VVGS t,2  2 IVVIN() GS t,1

1mV error in Vt is ~1% error in IOUT (for VEFF~200mV)

• In weak inversion with Vt mismatch there is an exponential relationship

VVGS t,1 VVtt,2 ,1 I e nVT OUT e nVT VVGS t,2 IIN e nVT

1mV error in Vt is ~4% error in IOUT 12 ECE1371 Swing and VEFF

• Minimum VDS of a transistor to keep it in saturation is VEFF

Usually VDS is VEFF + 50mV or more to keep ro high (keep the transistor in the saturation region)

With limited supply voltages, the larger the VEFF, the larger the VDS across the transistor, less room for signal swing

• With large VEFF… Can’t cascode – reduced OTA gain Stage gain is smaller – input referred noise is larger (effectively the SNR at the stage output is less)

13 ECE1371 Speed-Efficiency Product

• What is the optimal VEFF using a figure of merit defined as the product of fT and gm/ID

Optimal point at VEFF = 130mV in 0.18m

300

250

200 T *f

D 150 /I m g 100

50

0 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 V -V GS T

14 ECE1371 Summary of Trade-Offs

• Benefits of larger VEFF Larger bandwidth Higher linearity Better device matching Lower noise for current-source transistors

• Benefits of smaller VEFF Better efficiency – lower power Larger signal swings Better noise performance for input transistors

Good starting point: VEFF ~ VDD/10

15 ECE1371 Amplifier Design - Topology

Output Power Topology Gain Speed Noise Swing Dissipation

Telescopic Medium Medium Highest Low Low

Folded- Medium Medium High Medium Medium Cascode

Two-Stage High Highest Low Medium Low

Gain- High Medium Medium High Medium Boosted

From Razavi Ch.9

16 ECE1371 Amplifier Errors

• Two errors: Dynamic and Static

• Static Errors Limit the final settling accuracy of the amplifier

Capacitor Mismatch (C1/C2 error) Finite OTA gain 1 V CCCCA1( )/ O ()z  1212 11/ A VCI 2  z  1(CCCA212 )/ 17 ECE1371 Amplifier Errors

• Dynamic Errors: Occurs in the integration phase when a ‘step’ is applied to the OTA Slewing Finite bandwidth Feedforward path Non-dominant poles

18 ECE1371 Static Amplifier Errors

• First look at frequency independent response Static error term 1/A

VO CC1111  1  VCI 2211/ A C A C   2 CCC12IN

• Example: 0.1% error at output (Gain = 4)

C1 = 4pF, C2 = 1pF, CIN = 1pF

VO 6 41  VAI  A > 6000 for 0.1% error

19 ECE1371 Dynamic Amplifier Errors

• What is the transfer function of this circuit? By inspection…

Gain is -C1/C2

Zero when VXsC2 = VXGm

Pole at Gm/CL,eff where CL,eff = C2(1-) + CL sC 1 2 V CG O  1 m VCsC I 2 1 Leff, Gm 20 ECE1371 Single-Pole Settling Error

• Step response of 1st-order (unity-gain) system

1 1 Unit step through system s 1/ s unity 1 Inverse Laplace transform of ss(1 /unity ) Step response is 1 e unityt

Error is e unityt

N ln2 Settles to N-bit accuracy in t  unity

21 ECE1371 Pole and Zero Settling Error

• Step response, 1st-order with feedforward zero

1 1/ s  Unit step through system z s 1/ s unity 1/ s  Inverse Laplace transform of z ss(1 /unity )  Step response is 1 ee unityttunity unity z  Error is ee unitytt unity unity z  N ln2 ln(1  / ) Settles to N-bit accuracy in t  unity z unity unity

22 ECE1371 Effect of Zero on Settling

• Zero slows down settling time Additional settling term   unity e unityt z Coefficient a function of feedback factor   GC/ C unity mLeff,  2 zmGC/(1)22 C C L

• To reduce impact of feedforward zero… Smaller  (one of the few advantages of reducing )

Larger CL

23 ECE1371 Effect of Zero on Settling

• Example of settling behaviour

 = 1/2, CL = C2/2

1.2

1

0.8

0.6

0.4 Amplitude 0.2

0 No Zero w/ Zero 0 0.2 0.4 0.6 0.8 1 Time (ns)

24 ECE1371 Two-Pole Settling Error

• Dominant and non-dominant pole, 2nd-order sys.

(assumes p2 >> p1 = unity/A) 1 1 2 Unit step through system ss s 1 p2  unity  unity

Step response is dependent on relative values of unity and p2

3 Cases:

Overdamped, p2 > 4unity

Critically damped, p2 = 4unity

Underdamped, p2 < 4unity

25 ECE1371 Two-Pole Settling Error

• Closed loop response of the amplifier (ignoring zero, including 2nd pole)

26 ECE1371 Two-Pole Settling Error

• Overdamped, p2 > 4unity 2nd pole much larger than unity-gain frequency Similar to 1st-order settling as 2nd pole approaches infinity BA Step response is 1eeAt Bt BA AB  2 p2 p22 4 p unity AB,  𝝎𝒑𝟐, 𝜷𝝎𝒖𝒏𝒊𝒕𝒚 22

• Critically damped, p2 = 4unity No overshoot 22unitytt unity Step response is 12eteunity

27 ECE1371 Two-Pole Settling Error

• Underdamped, p2 < 4unity Minimum settling  time depending on desired SNR  Increasing overshoot as p2 decreases Step response is    2  p2 t  2 p2 etsinunity p2  p2 2 4  t  1coset2 p2  unity p2 4 4 unity   1 p2

28 ECE1371 Two-Pole Settling

• Example:

unity/2 = 1GHz

p2/2 = 1GHz, 4GHz, 100GHz

1.2

1

0.8

0.6

Amplitude 0.4

Critically Damped 0.2 Overdamped Underdamped 0 0 0.2 0.4 0.6 0.8 1 Time (ns)

29 ECE1371 Two-Pole Settling

• Critically damped system settles faster than single-pole system

0 Critically Damped -20 Overdamped Underdamped

-40

-60

-80 Settling Error (dB) Error Settling -100

-120 0 1 2 3 4 Time (ns)

30 ECE1371 Two-Pole Settling

• Underdamped system gives slightly better settling time depending on the desired SNR

0  =4 p2 unity -20  =3.8 p2 unity  =3.6 -40 p2 unity

-60

-80

-100 Settling Error (dB) Error Settling

-120

-140 0 0.5 1 1.5 2 Time (ns)

31 ECE1371 Two-Pole Settling

• For a two-pole system, phase margin can be used equivalently

180   PM 90 tan1 p2    unity 

Critically damped: PM = 76 degrees Underdamped: PM < 76 degrees

(45 degrees if p2 = unity) Overdamped: PM = 76 to 90 degrees

32 ECE1371 Gain-Boosting

• Increase output impedance of cascoded transistor Impedance boosted by gain of amplifier A

VOUT/VIN = -gmROUT B 2 ROUT ~ Agmro OUT b L • Trade-offs X Does not require extra headroom IN Amplifier requires some power, but does not have to be very fast

33 ECE1371 Gain-Boosting

• Need to analyze gain-boosting loop to ensure that it is stable Cascade of amplifier A and source follower from node Y to node X

B

• Load capacitance at node Y CC OUT b May need extra capacitance CC to stabilize loop Y X

IN

34 ECE1371 Gain-Boosting

AORIG: Original amplifier response without gain-boosting

AADD: Frequency response of feedback amplifier A

ATOT: Gain-boosted amplifier frequency response

35 ECE1371 Gain-Boosting

• Stability of gain-boosted amplifier For 1st-order roll-off, the unity-gain frequency of the additional amplifier must be greater than the 3dB frequency of the original stage

3dB < UG,A

(if 3dB > UG,A there will be a discontinuity in the 1st order roll-off between UG,A and 3dB)

36 ECE1371 Gain-Boosting

• 2nd pole of feedback loop is equivalent to 2nd pole of main amplifier Set unity-gain frequency of additional amplifier lower than 2nd pole of main amplifier

UG,A < 2nd

• Only 45 degree phase margin if UG,A = 2nd

UG,A ~ 2nd/3 for a phase margin of ~71 degrees

UG,A ~ 2nd/4 for a phase margin of 76 degrees

37 ECE1371 Gain-Boosting

• Pole-zero doublet occurs at UG,A Must ensure that this time constant does not dominate the settling behaviour

• Set 5 (3dB frequency of closed loop amplifier response) below UG,A Ensures that time constant is dominated by 3dB frequency and not the pole-zero doublet

 < UG,A

Final Constraint: 5 < UG,A < 2nd

38 ECE1371 Pole-Zero Doublet

ZCL: Load Capacitance 2 ZOUT: gain-boosted output impedance ~ (1+A)gmro 2 ZORIG: cascoded output impedance ~ gmro

ZTOT: Total Output Impedance

CL OUT TOT

ORIG pole-zero

1 2 3dB UG,A 5 2nd

39 ECE1371 Pole-Zero Doublet

• Why is this a problem? Doublet introduces a slower settling component in the step response

Step response (where z and p are the doublet pole and zero locations, ~UG,A):     unityt zp t 1ee z unity

A higher-frequency doublet will always have an impact but will die away quickly A lower-frequency doublet will not have as large an impact, but it will persist much longer

40 ECE1371 Delaying vs. Non-Delaying Stage

• Depending on the architecture and stage sizing, this can be a power concern

Large CL reduces the power efficiency of an amplifier Larger amplifier results in a smaller feedback factor and reduced bandwidth

41 ECE1371 Delaying Stage

• Delaying Following stage does not load the output

Very little CL on output of the amplifier

• Example: 1st stage 4x larger than 2nd stage

(C3 = 0 for delaying, C3 = C1/4 for non-delaying)

Each stage has gain of 2 (C1/C2 = 2, C3/C4 = 2)

CC21() CIN CCCCCLeff,313 () IN CCC12IN

 ggmm ()unity delay  Pgdelay m CCCLeff,1 IN

42 ECE1371 Non-Delaying Stage

• Non-Delaying Following stage loads the output Applicable in pipeline ADCs, sometimes  (usually following stages much smaller, depending on OSR) Opamp is wasted during the non-amplifying stage (could power it down to save power)

• Example (continued):

 ggmm ()unity non delay  CCCLeff,11.75 1.5 IN

Increase gm by 1.75  CIN increases by 1.75 (approximately the same bandwidth with 1.75x power)

Pgnon delay 1.75 m for ()unity non delay () unity delay

43 ECE1371 Amplifier Stability

• Both phases are important Different loading on sampling and amplification phase

• Feedback factor is larger in sampling phase than amplification phase Amplifier could potentially go unstable if it was originally sized for optimal phase margin in the amplification mode

• Non-Delaying stages are more susceptible to instability in sampling phase since a much smaller load capacitance is present

44 ECE1371 Amplifier Stability

• Example:

C1 = 2pF, C2 = 1pF, CIN = 1pF

CL = 0.5pF (load of subsequent stage) Delaying Stage

Amplification: unity = gm/3pF Sampling:  = 1/2, CL,eff = 1pF, unity = gm/2pF Phase Margin: 73  65 (assume same p2)

45 ECE1371 Amplifier Stability

Non-Delaying Stage

Amplification:  = 1/4, CL,eff = 1.25pF, unity = gm/5pF

Sampling:  = 1/2, CL,eff = 0.5pF, unity = gm/1pF

Phase Margin: 73  33 (assume same p2)

46 ECE1371 Circuit of the Day: Cascode Current Mirror

47 ECE1371 What You Learned Today

• Choice of VEFF Trade-offs with various parameters • Amplifier Topology • Amplifier Step Response • Gain-Boosting • Choice of Delaying/Non-Delaying Stages Impact on stability of sampling/integrating phases

48 ECE1371