The Electrochemical Effects of Immersion on Electroless and its Consequences on the Hermetic Reliability of a Semiconductor Device

Juan Herbsommer, Osvaldo Lopez, Thorsten Teutsch and Andrew Strandjord

Abstract:

We have analyzed the effects of immersion gold (i-Au) and electroless nickel (e-Ni) thickness, on the reliability of a semiconductor device which has special constraints on the absolute Ni and Au layer thickness . The electrochemical reactions involved in the deposition of immersion Au over Ni involves a substitution process by which Ni are replaced by Au atoms. We demonstrate that in some cases this reaction changes the microstructure of the nickel near the perimeter of the pad where the nickel layer overlaps the layer of a semiconductor die, forming a mechanical seal to the passivation. This seal is extremely important for hermetic applications where one wants to keep moisture and contaminants away from the active pad area of the semiconductor die. We have found that extended exposure of this nickel-to-passivation interface, to the Au chemicals, damages this interface, leading to reliability issues. In this work, we analyze the phenomena by changing the Ni and Au layer thicknesses and observing its effects on MOSFET devices which are subjected to accelerated reliability stress testing in an autoclave. We conclude with a suggested solution to minimize the effect.

Keywords: ENIG, Immersion Gold, Electroless Nickel, Reliability, Under Bump Metallurgy

Introduction:

Electroless Nickel - Immersion Gold (ENIG) has become one of the more extensively used plating methods in the microelectronics industry for creating an under-bump-metallurgy (UBM) [1-3]. Several reasons for this are: low cost, high throughput, and simplicity of the process, i.e. no photolithography, no high vacuum steps, and no current is applied as is the case for electroplated UBM layers [4-6]. In addition, the reliability has shown to be extremely good for most non-hermetic bumping applications [7] where 5 µm of nickel is plated only on the existing I/O on the top of the die . However, several other aspects need to be considered when the ENIG process is to be used in devices which are used in hermetic applications , have physical constraints on the nickel thickness, or are hyper- sensitive to moisture. The MOSFET device in this study has nickel and gold simultaneously deposited on the I/O pads on the top side of the die, as well as on the entire backside of the die to enable electrical connection to a leadframe. The purpose of this work is to conduct a set of experiments that shows the importance of controlling the immersion Au deposition process and minimizing any detrimental interactions with the electroless nickel layer.

The electroless nickel and immersion gold layers are deposited using a series of wet chemical baths. The wafers are first immersed in chemicals that clean the bond pads of any impurities and then in chemicals that activate the pad surface for selective deposition of the nickel. This activation is typically a “zincation” process for aluminum pads and palladium process for pads. The nickel selectively plates only on this activated metal surface. No plating is observed on the passivation layers or on bare silicon. The electrochemical process for depositing metallic nickel is an autocatalytic reaction and thus the total thickness of the nickel layer is determined by the amount of time the wafers are in the nickel bath. As the nickel grows vertically, it also grows laterally at nearly the same rate, thus creating the typical “mushroom” shaped deposit. This growth is often constrained by the passivation layers on the wafer. The adhesion between the nickel and the passivation is only mechanical and not chemical, thus leaving potential channels for chemicals to migrate to the active bond pad.

Chemical Mechanical i-Au Adhesion Adhesion Passivation e-Ni

Al Si e-Ni e-Ni i-Au

Figure 1. Schematic diagram showing growth electroless nickel and immersion gold layers.

Several studies have shown that the immersion gold process can interact with the nickel layer [8-10] causing mechanical damage and of the nickel. We have examined this attack of Au chemicals on the Ni layer and found that this attach is isolated to the region near the edge of the bond pad where the nickel and passivation form a mechanical seal. This damage is shown in the SEM cross-sections in Figures 2a & b. Three different degrees of damage are observed: 1) an area where the galvanic attack produced a very porous Ni layer, 2) a region where the Ni was completely dissolved creating a void, and 3) a part where the EDX detected a Ni layer very rich in Au. a) b)

Figure 2: a) SEM cross section image of the ENIG layers near the interface with the passivation of the silicon die. Observe the damage caused by the galvanic attack of Au on the Ni layer (red oval). b) EDX analysis allowed us to identify the composition of the different areas of the affected interface. Colors are introduced to clarify the findings.

The literature attributes this phenomenon to a hyperactive electrochemical reaction between the gold and nickel and refers to the region as porous or spongy nickel. These voids and change in chemical composition at this interface between the electroless nickel metallization and the passivation can reduce any mechanical adhesion between the layers and further increase the size of channel. Moisture and ionic contaminants could then more easily migrate through these openings, reach the active area of the integrated circuit, and cause a device failure.

Test Device:

In this work, we used an epoxy encapsulated MOSFET transistors (5x6 mm QFN package type) as the microelectronics device under study. Humidity/temperature accelerated stress testing was performed using an autoclave (126ºC at 2 atm for 96 hours) to induce reliability failures.

Figure 3: Three dimensional drawing of a MOSFET device using a clip QFN power package

One of the main reasons why power devices need to have metallization on the both the backside of the die as well as the I/O pads of the semiconductor die, is to create solderable surfaces in order to solder the die to a Cu leadframe on the bottom and to allow a metallic clip to make electrical contact to the top side of the die. This approach is used in many power electronic devices where the stringent electrical and thermal performance requires extremely good and reliable interconnects. In our case, the bottom of the silicon die is soldered to a leadframe and the top I/Os to a cooper clip using a high solder compound (see Figure 3). Since the standard pad metallization for most high power device wafers is still mainly aluminum (with a few percent of Si or Cu), a solderable metallization like ENIG is required on top of this pad metal in order to solder the clip to the top side of the die. Using this technology, a 10 mm 2 silicon based MOSFET die devices is capable of conducting more than 25 amps of current, with a typical resistance of 1 mOhm, and a thermal resistance (junction to case) lower than 1 C/W. For most flip chip and WLCSP applications, 5 µm on nickel is deposited only on the I/O pads on the top side of the die, creating a significant amount of surface area overlap between the nickel and the passivation. This provides a good mechanical seal between the nickel and the die. In a MOSFET device, where the backside metal is simultaneously deposited, the wafer warpage resulting from 5 µm of nickel, makes the wafer hard to handle in subsequent processing steps. This dictates that the nickel thickness be kept to a minimum in order to minimize absolute stress.

It is an unavoidable fact that, during the reflow of the solder paste, a substantial amount of flows out over the entire semiconductor die. Even though many solder pastes claim to use no clean fluxes, we have found that in general, they are a very serious source of ionic contamination and should be cleaned and eliminated immediately after solder reflow. In particular we have found that these contaminants are especially damaging when combined with moisture. We believe the reason for this is that some of the ionic compounds in the flux are soluble in water, and the transport effect of moisture could drive these molecules deep into the active area of the chip, where they could create leakages in the transistor channel area (channeling failures).

In this work, we present a detailed analysis of the reliability effects of different ENIG process conditions and the assembly process flow to eliminate this issue.

Experimental:

The ENIG variables that were changed in this study were Ni thickness and immersion time in the Au plating bath . By changing the time in the Au bath, one varies the time that the Ni atoms in the already deposited Ni layer, can be substituted by Au atoms, and so affecting the degree of potential damage of the ENIG in the joint with the passivation. Our expectation is that longer times in the gold bath will lead to greater amounts of Ni corrosion and therefore increase the failure rate during autoclave testing.

The motivation for changing the Ni thickness needs a more detailed explanation. The electroless nickel deposit does not form an adhesive chemical bond to passivation materials like silicon nitride. The only “seal” that may be present between these two layers, is simply a mechanical one. The as-deposited electroless Ni layer has some intrinsic tensile stress that tends to pull the Ni layer away from the passivation at this interface. Thus a thicker Ni layer which has more total stress, has a higher tendency to flex and create a gap between the passivation and the ENIG. In addition, a larger gap would allow more Au chemicals into the gap and thus increase the amount of spongy nickel. This in turn, would increase the possibility of a leakage failure due to ionic contamination into the channel area. In this case, we expect to see an increase in the failure rate for the cells with thicker Ni.

Table 1, shows the different legs of the experiment for two different assembly processes: 1) with flux cleaning step, and 2) without flux cleaning step. The purpose of these two legs, is to modify the amount of possible ionic contamination inside the package, for moisture to transport through the nickel to passivation gaps, into the active area. Each group contains 77 test devices.

Table 1: Matrix detailing the variables of the experiment and the number of units per cell.

FLUX CLEAN PROCESS NO FLUX CLEAN PROCESS Ni (um) Au time (min) Nnumber of units Ni (um) Au time (min) Nnumber of units 1 10 77 1 10 77 1 20 77 1 20 77 1 45 77 1 45 77

2 10 77 2 10 77 2 20 77 2 20 77 2 45 77 2 45 77

The cleaning step was performed immediately after the reflow process using Zestron™ cleaning solution in an ultrasonic cleaner at 45% of full ultrasonic power for 15 minutes at room temperature, 15 minutes of DI water rinsing, and 10 minutes of blowing to dry the parts.

Results:

The MOSFET devices were electrically measured before and after the autoclave tests. The following parameters were measured: Idss (drain to source leakage), Igss (gate to source leakage), Rdson (resistance of the device in the ON state), BVDSS (breakdown voltage), VF (forward diode voltage) and Vth (device threshold voltage).

If the difference between the initial and final measured value is larger than a specified value of 100 nanoAmps for lgss and/or ldss, the device is considered a failure. After the final measurement is complete, all the leakage failures are subjected to an overnight bake at 100ºC to eliminate the failures that are related to a superficial moisture path. The failures remaining after the bake are mostly due to ionic contaminants that were driven by the moisture to the active area

The electrical measurements after the autoclave stress testing showed, that all the failures encountered were due to leakage, as predicted. Figure 4 shows the percentage of leakage failures observed after 96 hours of autoclave for the NO CLEAN legs of the experiments (after overnight bake)

Leakage failures after 96hs AC Leakage failures after 96hs AC 50% 50% No Clean No Clean Ni Thickness =2 um 40% 40% Ni Thickness = 1 um

30% 30%

20% 20%

10% Percentage failures of

10% Percentage failures of

0% 0% 0 10 20 30 40 50 0 10 20 30 40 50 Time in the Au bath (min) Time in the Au bath (min)

Figure 4: Percentage of leakage failures after 96 hours of autoclave testing for Ni = 2 µm (left) and Ni = 1 µm (right) for the No Clean assembly process flow.

The samples with 2 µm thick Ni show a clear relationship between the device failure rate and the amount of time in the gold plating bath (electrochemical degradation). There are more failures as the plating time increases. This effect is very important, as we reach almost 50% failures at 45 minutes in the Au bath. This Au bath time corresponds to 0.1 µm of Au thickness as measured in a Scanning Electron Microscope, in an area away from the joint between the ENIG and passivation glass.

The data for the 1 µm Ni samples show a much reduced quantity of failures in comparison with the 2 µm Ni data, and also the number of failures does not increase with exposure time in the Au bath.

Our interpretation of the data is the following: the “No Clean” process flow provides an abundant quantity of ionic molecules inside the package that are available for the moisture to drive into the active area through the gaps created between in the ENIG-passivation interface. As postulated above, the tensile stress of the Ni layer is proportional to its thickness and this plays an important role in defining the size of the gap between the Ni and passivation. Thus, for a similar degree of corrosion (determined by the Au bath time), the devices with 2 µm Ni layer are more susceptible to opening a gap at the ENIG-passivation interface, than the devices with 1 µm Ni (with lower total tensile stress and reduced tendency to peel from the passivation)

Figure 5 shows the percentage of leakage failures observed after 96 hours of autoclave for the CLEAN legs of the experiments. Leakage failures after 96hs AC Leakage failures after 96hs AC 50% Clean 50% Clean Ni Thickness =2 um Ni Thickness =1 um 40% 40%

30% 30%

20% 20%

10% 10% Percentage of failures of Percentage Percentage of failures of Percentage 0% 0% 0 10 20 30 40 50 0 10 20 30 40 50 Time in the Au bath (min) Time in the Au bath (min)

Figure 5: Percentage of leakage failures after 96 hours of autoclave for Ni = 2 µm (left) and Ni = 1 µm (right) for the Clean assembly process flow

The data for the samples in the “CLEAN” leg shows quite a different behavior in comparison with the NO CLEAN leg of the experiment. The data for the 2 µm thick Ni samples, shows only 1 or 2 failures out of 77 units, and there is little dependence on time in the gold bath. The data for the 1 µm Ni samples shows zero failures for 10 and 20 minutes of Au bath (indicated with arrows in the Figure 5) and only 1 sample exhibited leakage failure at 45 min in the Au bath.

Our interpretation of the data is the following: introducing the “Clean” step into the process flow substantially reduces the amount of ionic contaminants from the flux that could cause migrate through any gap in the nickel to passivation interface, and cause leakage failures (this is evident for both the 1 µm and 2 µm Ni thicknesses). This indicates that the level of ions in the package can be reduced to a low enough level by: 1) using 1 µm thick nickel, using the short immersion times in the Au bath (10 and 20 min), and cleaning after reflow. This last statement is extremely important because it indicates that there is a process that can be used so of the parts will pass our reliability specification.

To visually verify the effect that we are observing, the epoxy encapsulation was removed from some of the devices to expose the silicon die and inspect them after the moisture stress was finished. Figure 6 shows a top down view of the dies after the encapsulation was removed. Image A) corresponds to a device that was immersed for 10 min in the Au bath, and image B) shows a device that was plated for 45 minutes. The part in A does not show any damages due to the moisture, while part B shows significant signs of Al corrosion. Our interpretation of the images is that part B was subjected to longer time to the Au bath and the interface ENIG- passivation was damaged opening a gap for the moisture to move under the passivation and corrode the Al. In part A the aluminum layer was not affected by the moisture due to a tighter ENIG-passivation interface. Ionic contamination driven by the moisture that caused the corrosion is suspected to be the main cause of the leakage failures detected in the thicker Au parts.

Figure 6: Optical images of device A (10 min Au) and device B (45 min Au) after the encapsulation mold compound was removed. These parts were subject to the Autoclave reliability stress Several parts were also cross sectioned from the same experimental legs and inspected by SEM Figure 7 shows side view SEM images of the devices after the cross section polishing was finished. Image A) corresponds to a device that was immersed for 10 min in the Au bath and image B) shows a device that was Au plated for 45 minutes. Part A) does not show any damage to the device structure under the ENIG and the passivation. In contrast, part B shows extensive damage under the passivation due to the volume corrosion and subsequent expansion and cracking of the aluminum, which tend to create a blister that breaks the passivation. Once the glass protection is broken the failure mechanism accelerates due the ingress of massive amounts of moisture into the device.

A) Au=10 min B) Au=45 min

Al ENIG Passivation Si

Figure 7: SEM images of cross section parts A (10 min Au) and B (45 min Au). These parts were subject to the Autoclave reliability stress

Tradeoffs between Au thickness and solderability and wirebondability of the ENIG:

In general, after solder reflow it is sometimes necessary to wire bond unbumped pads on the MOSFET die to the lead frame in order to make the required electrical connections between the die and the package. For the device described in this paper, the gate pad needs to be wire bonded to one of the pins of the package. Although the reflow step is performed in a nitrogen atmosphere, thermal exposure often cause a small amount of nickel to diffuse through the thin immersion gold layer, where it can oxidize at room temperature and therefore affect the quality and reliability of the wire bond [11-13].

Using Auger electron spectroscopy on the ENIG surface after reflow we have detected NiO 2 on the Ni/Au plated gate pad. The formation of this is a consequence of Ni diffusion to the surface during the reflow process and subsequent oxidation when the part is exposed to the atmosphere. To minimize the Ni diffusion one can increase the Au thickness but as we discussed above an extended Au bath time degrades the interface ENIG-passivation. We have a tradeoff: if the Au is too thin we are exposed to oxidation of the gate pad but if the Au is too thick we will have damage in the ENIG-passivation interface which will make our devices susceptible to reliability failures.

To find a solution to this tradeoff we have measured two critical parameters of the wire bond to characterize its quality: wire pull and ball shear as a function of the Au thickness after reflow.

Figure 8: Wire pull and ball shear of gate wire bond for different Au thickness

The Ni thickness for all the samples is 1 um and for each Au thickness we show the minimum, average and maximum value for a group of 30 samples.

Figure 8 shows the results obtained for the minimum, maximum and average values of each data distribution. The wire pull data shows that there is an increase in the minimum, average and maximum values as we increase the Au bath time (equivalent to Au thickness). This is evidence that that the Ni diffusion and further oxidation decreases as the Au becomes thicker.

If we look at the ball shear data we see that the strength of the bond increases from 10 to 20 min of Au bath and there is saturation for Au bath greater than 20 min. In this case the specification determines a minimum value of 80.5 grams and clearly 20 min of Au bath time seems to be the optimum parameter.

The results of the tradeoff analysis are very good if we take into account that to pass qualification we need to use a clean process with 10 or 20 min of Au bath time. From this latest tradeoff analysis the 10 min option is eliminated because the Au is too thin and does not prevent the oxidation of the gate pad.

Conclusions:

We have analyzed the effects of immersion gold (i-Au) and electroless nickel (e-Ni) thickness, on the reliability of a semiconductor device. The experiment was conducted on MOSFETS high power transistors which Si dies were subjected to different degrees of galvanic corrosion caused by Au on Ni. The packaged devices were then subjected to an Autoclave reliability test to measure the effects of the corrosion in the performance of the device.

The results show that the extended Au bath times deteriorate the interface between the passivation and the ENIG metallization. This corrosion opens a gap in the area affected that allows contaminants to be driven by moisture to reach the active area of the devices causing electrical leakage failures. We observed also that this effect is enhanced when the Ni thickness is increased. We conclude that this effect is due to the increased stress of the Thicker Ni layer which helps to open a gap between the passivation and the ENIG. This affect would not be true for common flip chip and WLCSP parts where 5 µm on nickel is deposited and no backside metal is necessary.

We also observed a very important effect of the flux cleaning process in the rate of failures after Autoclave. The flux present in the NO CLEAN samples provided abundant source of contaminant ions inside the package. This allowed us to see how the failure rate decreases with reduced Au bath time and thinner Ni metallization. However, we conclude that an extremely important condition to have a reliable device is to clean the flux even in the case of using a non-clean flux like we did in this case. The flux cleaning process reduced the failure from 20-50 % failure rate to few percents in the worst case scenario.

Finally, we conclude that the galvanic corrosion caused by extended i-Au process can be avoided by optimizing ENIG process without degradation of the wire bondable and solderable characteristics of the ENIG metallization. The final result is a reliable process flow that maintains the desirable characteristics of the ENIG metallization and at the same time is able to successfully pass the most stringent reliability qualification process.

References:

[1]. T. Oppert, E. Zakel, and T. Teutsch, ”A Roadmap to Low Cost Flip Chip and CSP using Electroless Ni/Au”, Proceedings of the International Electronics Manufacturing Technology Symposium (IEMT) Symposium, Omiya, Japan, April 15-17, 1998.

[2] Riedel, W., “Electroless Nickel Plating”. ASM International, Finishing Publishing LTD., 1991.

[3] A.J.G. Strandjord, S.P. Popelar, and C. Jauernig, “Interconnecting to Aluminum and Copper Based Semiconductors (Electroless-Nickel/Gold for Solder Bumping and Wirebonding)”, Microelectronics Reliability, Volume 42/2, pp. 265-283, March 2002.

[4] G. Motulla, "A Low Cost Bumping Service Based on Electroless Nickel and Solder Printing," Proc. IEMT/IMC Symposium., Omiya, Japan, 1997.

[5] J. Kloeser, A. Ostmann, J. Gwiasda, F. Bechtold, E. Zakel, and H. Reichl, “Low Cost Flip Chip Technologies Based on Chemical Nickel Bumping and Solder Printing,” ISHM, 1996.

[6] A. Ostmann, C. Jauernig, C. Dombrowski, R. Aschenbrenner, and H. Reichl, “Electroless Metal Deposition for Back End Wafer Processing”, Advanced Microelectronics, May-June 1999, pp. 23-26.

[7]. A.J.G. Strandjord, M. Johnson, H. Lu, D. Lawhead, R. Hanson, and R. Yassie, “Electroless Nickel-Gold Reliability UBM, Flipchip, and WLCSP, (Part I of III)” ", Proceedings of IMAPS 2000 San Diego CA, October 2006.

[8] B. Houghton: ITRI project on electroless nickel/immersion gold joint cracking; Proc. IPC Printed Circuits Expo 99, March 16-19, Long Beach, CA, S18-4.

[9] N. Biunno: A Root Cause Failure Mechanism for Solder Joint Integrity of Electroless Nickel/Immersion Gold Surface Finishes; Future Circuits International, 1998, pp 133-137.

[10] Jodi A. Roepsch, Robert F. Champaign, Barbara M. Waller, “Black Pad Defects Influence of Geometry and other Factors”, Proceedings SMTA 2003, pp.404-411.

[11] BT Ng, Ganesh VP and C Lee, ‘Optimization of Gold on ElectrolessNickel Immersion Gold for High Temperature Applications’, IEEE Electronic Packaging Technology Conference (EPTC) 2006.

[12] Bob Chylak, Tom Thieme, Jamin Ling , and Horst Clauberg , “Next Generation Nickel-Based Bond Pads Enable Copper Wire Bonding”, SEMICON China 2009.

[13] P.Retchav, et al., ‘Mechanical reliability of Au and Cu wire bonds to Al, Ni-Au and Ni-Pd-Au Capped Cu Bond Pad’, Micro Electronic Reliability, 2006 .