The Electrochemical Effects of Immersion Gold on Electroless Nickel and its Consequences on the Hermetic Reliability of a Semiconductor Device Juan Herbsommer, Osvaldo Lopez, Thorsten Teutsch and Andrew Strandjord Abstract: We have analyzed the effects of immersion gold (i-Au) and electroless nickel (e-Ni) thickness, on the reliability of a semiconductor device which has special constraints on the absolute Ni and Au layer thickness . The electrochemical reactions involved in the deposition of immersion Au over Ni involves a substitution process by which Ni atoms are replaced by Au atoms. We demonstrate that in some cases this reaction changes the microstructure of the nickel near the perimeter of the pad where the nickel layer overlaps the passivation layer of a semiconductor die, forming a mechanical seal to the passivation. This seal is extremely important for hermetic applications where one wants to keep moisture and contaminants away from the active pad area of the semiconductor die. We have found that extended exposure of this nickel-to-passivation interface, to the Au plating chemicals, damages this interface, leading to reliability issues. In this work, we analyze the phenomena by changing the Ni and Au layer thicknesses and observing its effects on MOSFET devices which are subjected to accelerated reliability stress testing in an autoclave. We conclude with a suggested solution to minimize the effect. Keywords: ENIG, Immersion Gold, Electroless Nickel, Reliability, Under Bump Metallurgy Introduction: Electroless Nickel - Immersion Gold (ENIG) has become one of the more extensively used plating methods in the microelectronics industry for creating an under-bump-metallurgy (UBM) [1-3]. Several reasons for this are: low cost, high throughput, and simplicity of the process, i.e. no photolithography, no high vacuum steps, and no current is applied as is the case for electroplated UBM layers [4-6]. In addition, the reliability has shown to be extremely good for most non-hermetic solder bumping applications [7] where 5 µm of nickel is plated only on the existing I/O on the top of the die . However, several other aspects need to be considered when the ENIG process is to be used in devices which are used in hermetic applications , have physical constraints on the nickel thickness, or are hyper- sensitive to moisture. The MOSFET device in this study has nickel and gold simultaneously deposited on the I/O pads on the top side of the die, as well as on the entire backside of the die to enable electrical connection to a leadframe. The purpose of this work is to conduct a set of experiments that shows the importance of controlling the immersion Au deposition process and minimizing any detrimental interactions with the electroless nickel layer. The electroless nickel and immersion gold layers are deposited using a series of wet chemical baths. The wafers are first immersed in chemicals that clean the bond pads of any impurities and then in chemicals that activate the pad surface for selective deposition of the nickel. This activation is typically a “zincation” process for aluminum pads and palladium process for copper pads. The nickel selectively plates only on this activated metal surface. No plating is observed on the passivation layers or on bare silicon. The electrochemical process for depositing metallic nickel is an autocatalytic reaction and thus the total thickness of the nickel layer is determined by the amount of time the wafers are in the nickel bath. As the nickel grows vertically, it also grows laterally at nearly the same rate, thus creating the typical “mushroom” shaped deposit. This growth is often constrained by the passivation layers on the wafer. The adhesion between the nickel and the passivation is only mechanical and not chemical, thus leaving potential channels for chemicals to migrate to the active bond pad. Chemical Mechanical i-Au Adhesion Adhesion Passivation e-Ni Al Si e-Ni e-Ni i-Au Figure 1. Schematic diagram showing growth electroless nickel and immersion gold layers. Several studies have shown that the immersion gold process can interact with the nickel layer [8-10] causing mechanical damage and corrosion of the nickel. We have examined this attack of Au chemicals on the Ni layer and found that this attach is isolated to the region near the edge of the bond pad where the nickel and passivation form a mechanical seal. This damage is shown in the SEM cross-sections in Figures 2a & b. Three different degrees of damage are observed: 1) an area where the galvanic attack produced a very porous Ni layer, 2) a region where the Ni was completely dissolved creating a void, and 3) a part where the EDX detected a Ni layer very rich in Au. a) b) Figure 2: a) SEM cross section image of the ENIG layers near the interface with the passivation of the silicon die. Observe the damage caused by the galvanic attack of Au on the Ni layer (red oval). b) EDX analysis allowed us to identify the composition of the different areas of the affected interface. Colors are introduced to clarify the findings. The literature attributes this phenomenon to a hyperactive electrochemical reaction between the gold and nickel and refers to the region as porous or spongy nickel. These voids and change in chemical composition at this interface between the electroless nickel metallization and the passivation can reduce any mechanical adhesion between the layers and further increase the size of channel. Moisture and ionic contaminants could then more easily migrate through these openings, reach the active area of the integrated circuit, and cause a device failure. Test Device: In this work, we used an epoxy encapsulated MOSFET transistors (5x6 mm QFN package type) as the microelectronics device under study. Humidity/temperature accelerated stress testing was performed using an autoclave (126ºC at 2 atm for 96 hours) to induce reliability failures. Figure 3: Three dimensional drawing of a MOSFET device using a clip QFN power package One of the main reasons why power devices need to have metallization on the both the backside of the die as well as the I/O pads of the semiconductor die, is to create solderable surfaces in order to solder the die to a Cu leadframe on the bottom and to allow a metallic clip to make electrical contact to the top side of the die. This approach is used in many power electronic devices where the stringent electrical and thermal performance requires extremely good and reliable interconnects. In our case, the bottom of the silicon die is soldered to a leadframe and the top I/Os to a cooper clip using a high lead solder compound (see Figure 3). Since the standard pad metallization for most high power device wafers is still mainly aluminum (with a few percent of Si or Cu), a solderable metallization like ENIG is required on top of this pad metal in order to solder the clip to the top side of the die. Using this technology, a 10 mm 2 silicon based MOSFET die devices is capable of conducting more than 25 amps of current, with a typical resistance of 1 mOhm, and a thermal resistance (junction to case) lower than 1 C/W. For most flip chip and WLCSP applications, 5 µm on nickel is deposited only on the I/O pads on the top side of the die, creating a significant amount of surface area overlap between the nickel and the passivation. This provides a good mechanical seal between the nickel and the die. In a MOSFET device, where the backside metal is simultaneously deposited, the wafer warpage resulting from 5 µm of nickel, makes the wafer hard to handle in subsequent processing steps. This dictates that the nickel thickness be kept to a minimum in order to minimize absolute stress. It is an unavoidable fact that, during the reflow of the solder paste, a substantial amount of flux flows out over the entire semiconductor die. Even though many solder pastes claim to use no clean fluxes, we have found that in general, they are a very serious source of ionic contamination and should be cleaned and eliminated immediately after solder reflow. In particular we have found that these contaminants are especially damaging when combined with moisture. We believe the reason for this is that some of the ionic compounds in the flux are soluble in water, and the transport effect of moisture could drive these molecules deep into the active area of the chip, where they could create leakages in the transistor channel area (channeling failures). In this work, we present a detailed analysis of the reliability effects of different ENIG process conditions and the assembly process flow to eliminate this issue. Experimental: The ENIG variables that were changed in this study were Ni thickness and immersion time in the Au plating bath . By changing the time in the Au bath, one varies the time that the Ni atoms in the already deposited Ni layer, can be substituted by Au atoms, and so affecting the degree of potential damage of the ENIG in the joint with the passivation. Our expectation is that longer times in the gold bath will lead to greater amounts of Ni corrosion and therefore increase the failure rate during autoclave testing. The motivation for changing the Ni thickness needs a more detailed explanation. The electroless nickel deposit does not form an adhesive chemical bond to passivation materials like silicon nitride. The only “seal” that may be present between these two layers, is simply a mechanical one. The as-deposited electroless Ni layer has some intrinsic tensile stress that tends to pull the Ni layer away from the passivation at this interface.