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United States Patent (19) (11 Patent Number: 4,739,475 Mensch, Jr

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United States Patent (19) (11 Patent Number: 4,739,475 Mensch, Jr United States Patent (19) (11 Patent Number: 4,739,475 Mensch, Jr. (45) Date of Patent: Apr. 19, 1988 (54 TOPOGRAPHY FOR SIXTEEN BIT CMOS Polysilicon-Gate FETs', IBM Technical Disclosure MCROPROCESSORWTH EGHT BT Bulletin, v 20, No. 4, pp. 1640-1643, 9/77. EMULATION AND ABORT CAPABLTY Western Design Center, "OXI-CMOS W65SC8XX 76 Inventor: William D. Mensch, Jr., 1924 E. and W65SC9XX 16-Bit Microprocessor Family". Hope St., Mesa, Ariz. 85203 Primary Examiner-Archie E. Williams, Jr. (21) Appl. No.: 675,831 Assistant Examiner-Michael J. Ure 22 Filed: Nov. 28, 1984 Attorney, Agent, or Firm-Cahill, Sutton & Thomas Related U.S. Application Data (57) ABSTRACT 63 Continuation-in-part of Ser. No. 534,181, Sep. 20, 1983. The topography of a sixteen bit CMOS microprocessor 51) Int. Cl'.......................... G06F1/00; G06F 9/44; chip including circuitry for enabling it to emulate, G06F 13/38; HO1L 27/00 under software control, a prior art 6502 microprocessor 52) U.S. C. ..................................... 364/200; 307/468 includes an N-channel minterm logic section including 58) Field of Search ... 364/200 MS File, 900 MS File; 498 "vertical' diffused minterm lines across which 32 357/41; 307/468, 469 "horizontal" metal lines from an instruction register and (56) References Cited a timing generator pass and make selective contact to separate polycrystalline silicon gate electrodes to effec U.S. PATENT DOCUMENTS tuate a first level of instruction op code decoding. The 3,943,377 3/1976 Suzuki ................................. 307/469 resulting minterm signals are inverted by a row of 3,987,418 10/1976 Buchanan .. ... 364/200 CMOS inverters, the outputs of which are connected to 4,044,340 8/1977 Itoh....... 357/41 polycrystalline lines extending into an N-channel sum 4,144,562 3/1979 Cooper .............. ... 364/200 4,180,861 12/1979 Armstrong et al. ... 364/900 of-minterm section. "Horizontal' metal sum-of-min 4,213,176 7/1980 Cooper .............. ... 364/200 term conductors contact various N-channel field effect 4,245,324 1/1981 Machol et al. ... 307/468 transistors in the sum-of-minterm region. Those sum-of 4,272,828 6/1981 Negi et al.......... ... 364/900 minterm lines having fewest field effect transistors con 4,317,171 2/1982 Maejima et al....... ... 364/200 nected thereto are positioned on the bottom of the sum 4,363,091 12/1982 Pohlman, III et al. ... 364/200 4,402,042 8/1983 Guttag. ... 364/200 of-minterm array, and those having the most connec 4,402,043 8/1983 Guttag. ... 364/200 tions to N-channel FETs are positioned at the top 4,447,878 5/1984 Kinnie et al. ............. ... 364/200 thereof to minimize the amount of chip surface area 4,449,184 5/1984 Pohlman, III et al. ... ... 364/200 required for the sum-of-minterm array and for routing 4,511,812 4/1985 Satake ....................... ... 307/.465 of the sum-of-minterm signals produced thereby to 4,661,728 4/1987 Kashimura .......................... 307/468 transfer gate logic on the chip. OTHER PUBLICATIONS Cook et al., "Programmable Logic Arrays. Using 13 Claims, 16 Drawing Sheets DIFFUSED MINTERM LINES SEGE Sir FEl Festsease res 1. I32 METAL 3. As SUM OF MINTERM ExE5 EEC. It INES (/as aga CEiftee As East A35-4 ExE SETI A36-3 EE IT Fr.E. fas-2 FF II WA As DFFUSED OR POLY SUM OF MINTERM LiNES ROUTED TO REGISTER TRANSFER losic 3 U.S. Patent Apr. 19, 1988 Sheet 2 of 8 4,739.475 & H H s U.S. Patent Apr. 19, 1988 Sheet 3 of 8 4,739,475 MINTERM498 Di FFUSED LINES A rig A2.4 WSS O)4 - DIFFUSED MINTERM LINES 1z - - -44 MICRONS- - -N \-1-1 POLY feso -N-D-S-1 A79 r1N- 1 1 M'44 , 1,4-4 5. LINES 776 776 so, LiNSfRUCTION f/6A A. A. REGISTER ZZ 22 | - N-Nu f79' 175 N LN-J - DIFFUSED MINTERM LINES - 44 MCRONS-> f75-1N1 N. Jal" L. METAL JUMPERS U.S. Patent Apr. 19, 1988 Sheet S of 8 4,739,475 TO RDY CONTROL-- - - - - - - - - - - X f/2 /7O CIRCUIT A9/ REGISTER D DO-Do-XI-DS7 EOUT 6. f/3. s A556 L A6/ - Y C aaaaaaa - adaaaaaaru . is CLK REGISTER BT amaaaaaa- a aaaaaaaaaaa r///4 X A55AM E BT OF E TO MNTERM NSTRUCTION DECODNG (6A) REGISTER E | FIG. STACK FRCBRKL WPA HILDP SUM OF MINTERM CODNG SYNC X 2O5 GOTOZ D sk?-205 D. HLDP Air Eg-1. U.S. Patent Apr. 19, 1988 Sheet 6 of 8 4,739,475 | sæ-’tz0) !!!|-| 66/ ±7c-E77,7- | |||| U.S. Patent Apr. 19, 1988 Sheet 7 of 8 4,739,475 2Oe- * A 71-16 WEC T55. NSFER 2/O VECTOR CONTROL CRCUITRY 16- Arg-12 WP - RES VSS- 4O-RES ROY - 2 WDA RDY-2 39 - O2 (OUT) ABORT-3 MAX CD (OUT) - H3 38 -SO RO - 4 CD2 (IN) RC-4 37 H-CDON) ML-5 BE NC 5 36 - NC NM - 6 E NM - 6 35 - NC WPA - 7 R/W SYNC 7 34 - R/W WDD - 8 DO/BAO VDD-8 33 - DO AO - S DA BA AO - 9 32 - D W65SC816 D2A BA2 A O W65SC8O2 3-D2 A2 D3/8A3 A2 - 3OH- D3 A3 D 4/BA4 A3 - 2 29 - D4 A4 D5/BA5 A4 - 3 28 H-D5 A5 D6/BAS A5 - 4 27 - DS A6 D7/BA7 AS-15 26- D7 A7 A5 A7 - 6 25 - A15 A8 A 4 A8 - 7 24 H A4 A9 A3 A9 - 8 23 HA3 AIO Al2 AO A2 All WSS A U.S. Patent Apr. 19, 1988 Sheet 8 of 8 4,739,475 RO 2/4 2/5 N. ROY WAT ( //7 CD 2 X STATUS M/X REG. CD 20 2/6 M LR - TO MiNTERM DECODNG (f/64) AND MODE SECT DECODE (/6O) M M FROM SUM OF MINTERM DECODNG ( //6A ) F. G. - F 'rg-157 4,739,475 1. 2 over diffused regions in most silicon gate manufacturing TOPOGRAPHY FOR SIXTEEN BIT CMOS processes, and the constraint that conductors on the MCROPROCESSORWTH EIGHT BIT same layer of insulating oxide cannot cross over like EMULATION AND ABORT CAPABILITY conductors. Furthermore, the high amount of capacitances associ CROSS-REFERENCE TO RELATED ated with diffused regions and the high resistances of APPLICATIONS both diffused regions and polycrystalline silicon con This application is a continuation-in-part of my co ductors must be carefully considered by the circuit pending application "TOPOGRAPHY OF INTE designer and also by the chip designer in arriving at an GRATED CIRCUIT CMOS MICROPROCESSOR 10 optimum chip topography. For many types of circuits, CHIP”, Ser. No. 534,181, filed Sept. 20, 1983, and en such as the microprocessor of the present invention, an tirely incorporated herein by reference. extremely large number of conductive lines between sections of logic circuitry are required. The practically BACKGROUND OF THE INVENTION infinite number of possibilities for routing the various The invention relates to an efficient topography for a 15 conductors and placing of the various MOSFETS taxes sixteen bit CMOS microprocessor chip having the capa the skill and ingenuity of even the most resourceful chip bility of either operating as a sixteen bit microprocessor designers and circuit designers (and is far beyond the or operating to emulate the well-known 6502 eight bit capability of the most sophisticated computer layout integrated circuit microprocessor, depending only on programs yet available). Other constraints faced by the the state of a software "emulation bit' or 'E' bit. 20 chip layout designer and the circuit designer involve Those skilled in the art of integrated circuit design, the need to minimize cross-coupling and parasitic ef and particularly microprocessor chip design, know that fects which occur between various conductive lines and the size of a high volume integrated circuit chip is a conductive regions. Such effects may degrade voltages dominant factor in the ultimate yield and manufacturing on various conductors, leading to inoperative circuitry cost per unit. In all of the integrated circuit technolo 25 gies, including the CMOS technology, large scale inte or low reliability operation under certain operating grated (LSI) chips such as microprocessor chips include conditions. thousands of conductive lines and P-channel MOS The technical and commercial success of an elec FETS (metal-oxide-semiconductor field effect transis tronic product utilizing MOSLSI technology hinges on tors) and N-channel MOSFETS. Some of the lines are 30 the ability of the chip designer to achieve an optimum composed of aluminum metal interconnection layers chip topography. It is well known that a very high level and others are composed of polycrystalline silicon inter of creative effort is required, usually both by circuit connection layers on different insulative layers, and designers or layout draftsmen, to achieve a chip topog others of the conductors are diffused conductors. Cer raphy or layout which enables the integrated circuit to tain minimum line widths and spacings between the 35 have acceptable operating speeds and low power dissi respective lines and the sources and drains of the MOS pation and yet is sufficiently small in chip area to have FETS must be maintained to avoid short circuits and a high chip per wafer yield, i.e., to be economically parasitic effects despite slight variations in the manufac feasible. Often, many months of such effort between turing processes due to presence of minute particulates chip designers and circuit designers result in numerous that are invariably present in the semiconductor manu trial layout designs and redesigns and concomitant cir facturing facilities. Due to the low current supplying cuit design revisions before a reasonably optimum to capability of the very small MOSFETS that must be pography for a single MOSLSI chip is achieved.
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