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Rockwell MICROPROCESSOR PRELIMINARY INTRODUCTION

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Rockwell MICROPROCESSOR PRELIMINARY INTRODUCTION R65C00/21 • R65C29 R65C00/21 DUAL CMOS MICROCOMPUTER AND R65C29 DUAL CMOS Rockwell MICROPROCESSOR PRELIMINARY INTRODUCTION FEATURES • Two enhanced CMOS R6502 CPU's in one device • Nine interrupts — Common memory and I/O — Positive and negative edge detect — Shared data and subroutines — Low level detect (external IRQ) — IndependentCPU registers and interrupt vectors — Counter/Timer A and B underflow — Independent reset operation and programs — Inter-processor communication — R6502 software and timing compatible — Host computer data transfer • 10 new instructions for faster and smaller programs — Non-maskable — Unsigned Multiply (MUL) — Reset — Set and Reset Memory Bit (SMB and RMB) • Flexible system operation — Branch on Bit Set and Reset (BBS and BBR) — Memory mapped I/O for easy programming — Unconditional Branch (BRA) — Page zero location for memory efficient access — Push and Pull Index Registers (PHX, PHY, PLX, PLY) • Low power at normal frequency (40 mw at 2 MHz) • Microcomputer/microprocessor/peripheral controller operation • Reduced power at low frequency (2.0 mw at 2 MHz/128) — Stand-alone microcomputer • System clock rates from 10 KHz to 4 MHz 2048 x 8 mask programmable ROM • 5V ± 10% power supply 128 x 8 random access memory (RAM) • 64-pin QUIP — Enhanced microprocessor Built-in RAM, ROM and I/O with expandability 8-, 12- or 16-bit extension address bus SUMMARY — Programmable peripheral controller The Rockwell R65C00/21 is a complete, high performance Host data bus interface (Z80/8080 or 6500/6800 option) 8-bit, CMOS dual microcomputer in a single chip and is com­ Self-contained or expandable patible with all R6500 microprocessors except that it has • 16-bit Counter/Timer A with eight modes, and prescaler additional instructions including a 10-clock time multiply. — Timer Off — Free-Run Event Counter The R65C00/21 consists of two enhanced instruction set 6502 — Free-Run Pulse Width Measurement CPU’s in one device. The device also has 2048 bytes of Read- Only Memory (ROM), 128 bytes of Random Access Memory — One-Shot Retriggerable Timer (RAM) and versatile interface circuitry. The interface circuitry — One-Shot Interval Timer consists of two multimode programmable 16-bit counter/timers — Free-Run Interval Timer and 52 general purpose input/output lines. Some of these input/ — One-Shot Pulse Generator output lines may be used as address, data and control lines — Free-Run Pulse Generator for expanded systems or as data and control lines when the • 16-bit Counter/Timer B with four modes R65C00/21 is used as a programmable peripheral controller. — Free-Run Interval Timer The two CPU's in the R65C00/21 are functionally independent. — Free-Run Pulse Generator Each has its own set of registers, its own reset and interrupt — Event Counter vectors and operates under control of its own program. The two — Pulse Width Measurement CPU s do, however, share the same memory and system I/O • Up to 52 general purpose input/output lines resources. This allows direct communication between the two CPU’s and allows sharing of subroutines and common data — Five bidirectional 8-bit ports (PA, PB, PC, PD and PF) areas where desired. Programming and system design for — One 8-bit output port (PE) applications which require simultaneous control of two or more — One 4-bit input port (PG) independent asynchronous processes is thus simplified because — Multi-purpose operation for selected ports one CPU may control one process while the other controls Document No. 29651N64 Product Description Order No. 2161 Rev. 2, October 1984 3-3 R65C00/21 • R65C29 Dual CMOS Microcomputer/Microprocessor another one. Consequently, complex programming usually DEVELOPMENT SYSTEM SUPPORT needed to interleave the control functions or to implement an Prototype circuit and software development support are avail­ interrupt driven system, is not required. able using the Rockwell Design Center (RDC) and R65C00/21 Personality Module. Program development and debugging aids In a multiple computer approach, both processors may need the such as text editing, symbolic assembly with conditionals and same subroutines so that some portions of memory must be macros at the absolute and relocatable/linking level, and single/ duplicated in both systems. The dual CPU’s share the same multiple step execution with instruction/data tracing are pro­ program memory, therefore only one set of subroutines is vided. Real-time in-circuit emulation in the target environment required and both CPU's may even be using them at the same is also supported. time without interference. In addition to the dual CPU’s, the R65C00/21 also has the innovative architecture and the demonstrated high performance NOTE of the well established R6502 CPU, flexible input/output which All descriptions of R65C00/21 operation in this document provides improvements over the R6522 Versatile Interface also apply to the R65C29 except for internal ROM, and Adapter (VIA) device, and production efficient on-chip ROM and as otherwise noted. RAM. These features make the R65C00/21 a leading candidate for most imbedded microcomputer applications. A system using the R65C00/21 Dual CMOS Microcomputer will ORDERING INFORMATION be simpler in design, use less program memory, require fewer components, reduce circuit board sizes, simplify test require­ The R65C00/21 Dual CMOS Microcomputer can be ordered in ments, and minimize field maintenance— all contributing to lower volume quantities with the following speed capability and mask production and support costs. In addition, simpler designs shorten option indicated in the R65C00/21 ROM Code Order Form (Doc­ development effort and time— leading to reduced development ument Order No. 2134) costs and faster product to market. • 1, 2, 3, or 4 MHz system clock (02) • Crystal/master clock or slaved clock input mask option The R65C29 Dual CMOS Microprocessor, a ROM-less version of the R65C00/21 with permanently extended data and address The R65C29 Dual CMOS Microprocessor has the following bus, is also available. The R65C29 is ideal for dual CPU appli­ characteristics: cations requiring changeable ROM and/or extended RAM, ROM or I/O, and can also be used for R65COO/21 prototype circuit • Crystal/master clock input development. The R65C00/21 can also operate in an emulation • 8-bit data bus and 16-bit address bus extension mode, like the R65C29, with its internal ROM disabled. • No internal ROM 3-4 R65C00/21 • R65C29 Dual CMOS Microcomputer/Microprocessor INTERFACE The interfaces for the R65C00/21 and R65C29 are illustrated The interface signals for the R65C00/21 and R65C29 are in Figure 1. described in Table 2. The descriptions of the selectable bus expansion pins (16-bit address mode) for the R65C00/21 apply The pin assignments for the R65C00/21 and the R65C29 are to permanent bus expansion pins for the R65C29. shown in Figure 2. The R65C29 pin assignments are the same as the R65C00/21 except that bus expansion functions are per­ manently assigned instead of general purpose ports D and E. ¥d d _____ PORT A PA0-PA7 Vss RES PORT B PB0/PB7 XTALO OSCILLATOR XTALI CLOCK PORT C ---------1 PC0-PC7 GENERATOR OPTIONAL USE: NMtA HOST DATA BUS — i 2048 x 8 ROM PORT D PD0-PD7 NMiB R65C00/21 ONLY OPTIONAL USE: i EXP. BUS DATA/LOWER ADDR. (ADDR. LOW) R/W 128x8 PE0-PE7 PORT E RAM OPTIONAL USE: t> EXP. BUS EMS UPPER ADDR. (ADDR. HIGH) ■m CONTROL PORT F PF0-PF7 REGISTERS OPTIONAL USE: n PFO POS. EDGE DETECT PF1 NEG. EDGE DETECT __ SYNC PF2 EXT. IRQ INPUT PF3 TIMA I/O PF4 TIMB I/O 0A P F 5----- P F 6----- PF7 HINT PORT G PG0-PG3 I c OPTIONAL USE: PGO H02/HRD PGt HR/W/HWR PG2 HRS PG3 CS Figure 1. R65C00/21 and R65C29 Interface Diagram 3-5 R65C00/21 • R65C29 Dual CMOS Microcomputer/Microprocessor XTALO 1 64 Vcc XTALI c 2 63 RES 02 3 62 NMIA 0A ____ c 4 61 N M lI EMS 5 60 PGO SYNC _ C 6 59 PG1 R/W 7 58 PG2 PE7 c 8 57 PG3 PE6 9 56 PDO PE5 C 10 55 PD1 PE4 11 54 PD2 PE3 C 12 53 PD3 PE2 13 52 PD4 R65C00/21 PE1 C 14 51 PD5 PEO 15 50 PD6 PF7 C 16 49 PD7 PF6 17 48 PCO PF5 c 18 47 PC1 PF4 19 46 PC2 PF3 c 20 45 PC3 PF2 21 44 PC4 PF1 c 22 43 PC5 PFO 23 42 :□ PC6 PA7 C 24 41 PC7 PA6 25 40 n PBO PA5 C 26 39 PB1 PF4 27 38 => PB2 PA3 C 28 37 PB3 PA2 29 36 PB4 PA1 C 30 35 PB5 PAO 31 34 PB6 Vss C 32 33 PB7 XTALO l=l 1 64 Z) Vcc ----- XTALI l 2 63 RES 02 c r 3 62 NMIA 0A r 4 61 i NMIB EMS cz 5 60 Z] PGO SYNC 6 59 PG1 R/W 7 58 PG2 A1S 8 57 PG3 A14 cq 9 56 AO/DO A13 c ~ 10 55 A1/D1 A12 c r : 11 54 A2/D2 A11 r 12 i A3/D3 A10 cr: 13 52 ID A4/D4 R65C29 A9 r~ 14 51 AS/DS AS CI 15 50 1 3 A6/D6 PF7 16 49 l A7/D7 PF6 L _ | 17 48 p PCO PF5 18 47 PC1 PF4 cz 19 46 n PC2 PF3 20 45 i PC3 PF2 t_ 21 44 r: PC4 PF1 22 43 PC5 PFO c z 23 42 Z1 PC6 PA7 24 PC7 PA6 a 25 40 z: PBO PAS 26 39 i PB1 PA4 LT 27 38 PB2 PA3 I 28 37 i PB3 PA2 L. 29 36 PB4 PA1 I 30 35 PB5 PAO nz 31 34 ZD PB6 Vss I 32 33 ------------- J PB7 Figure 2.
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