Memory Management in Linux Is a Complex System ○ Supports a Variety of Systems from MMU-Less Microcontrollers to Supercomputers
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Memory Protection at Option
Memory Protection at Option Application-Tailored Memory Safety in Safety-Critical Embedded Systems – Speicherschutz nach Wahl Auf die Anwendung zugeschnittene Speichersicherheit in sicherheitskritischen eingebetteten Systemen Der Technischen Fakultät der Universität Erlangen-Nürnberg zur Erlangung des Grades Doktor-Ingenieur vorgelegt von Michael Stilkerich Erlangen — 2012 Als Dissertation genehmigt von der Technischen Fakultät Universität Erlangen-Nürnberg Tag der Einreichung: 09.07.2012 Tag der Promotion: 30.11.2012 Dekan: Prof. Dr.-Ing. Marion Merklein Berichterstatter: Prof. Dr.-Ing. Wolfgang Schröder-Preikschat Prof. Dr. Michael Philippsen Abstract With the increasing capabilities and resources available on microcontrollers, there is a trend in the embedded industry to integrate multiple software functions on a single system to save cost, size, weight, and power. The integration raises new requirements, thereunder the need for spatial isolation, which is commonly established by using a memory protection unit (MPU) that can constrain access to the physical address space to a fixed set of address regions. MPU-based protection is limited in terms of available hardware, flexibility, granularity and ease of use. Software-based memory protection can provide an alternative or complement MPU-based protection, but has found little attention in the embedded domain. In this thesis, I evaluate qualitative and quantitative advantages and limitations of MPU-based memory protection and software-based protection based on a multi-JVM. I developed a framework composed of the AUTOSAR OS-like operating system CiAO and KESO, a Java implementation for deeply embedded systems. The framework allows choosing from no memory protection, MPU-based protection, software-based protection, and a combination of the two. -
Go Forth with TTL !
Go Forth with TTL ! The Gigatron TTL Color Computer Forth for a Very Unusual Processor Ken Boak SV Fig. Forth Day 2019 . In September of 1975, MOS Technology launched the 6502 at the Wescon75 Computer Conference in San Francisco. Chuck Peddle and his team had created a very lean, stripped down, small die cpu. Costing just $25, the 6502 was a fraction of the cost of its nearest competitor. At that time the Intel 8080 was $360 and the Motorola 6800 was $175 . The 6502 was clearly a disruptive usurper. 25 year old, HP Engineer, Steve Wozniak, realised that this new microprocessor would be a game-changer and went on to incorporate it into the small computer he was developing. That machine went on to become the Apple I. In 1975 7400 TTL was the “Bread and Butter” of logic design: 7400 series TTL integrated circuits were developed in the early 1960’s. Initially quite expensive so mainly used in Military and Aerospace applications. By the early 1970’s TTL had become a versatile family of standardised, low cost,. easy to use logic. Typically about $1 per device. 7400 series logic was widely used in the design of minicomputers, including the PDP-11, the Data General Nova 1200 and later models of PDP-8. TTL was a viable, faster and cheaper processing solution than the emerging 8-bit microprocessors such as MOS 6502, Intel 8080 and the Motorola 6800. Essential Reading 16-bit TTL CPU board from Data General Nova 1200 The Gigatron TTL Computer – What is it? Started as a Hackaday.io project in Spring 2017 by Marcel van Kervinck of The Hague, Netherlands. -
Exploring Software Inefficiency With
ZeroSpy: Exploring Software Inefficiency with Redundant Zeros Xin You∗, Hailong Yang∗y, Zhongzhi Luan∗, Depei Qian∗ and Xu Liuz Beihang University, China∗, North Carolina State University, USAz State Key Laboratory of Mathematical Engineering and Advanced Computing, Wuxi, Chinay fyouxin2015,hailong.yang,07680,[email protected]∗, [email protected] Abstract—Redundant zeros cause inefficiencies in which the 1 for(int i=0;i<1000;++i) { 2 A[i] = 0; B[i] = i; zero values are loaded and computed repeatedly, resulting in 3 } 4 ... unnecessary memory traffic and identity computation that waste 5 for(int i=0;i<1000;++i) memory bandwidth and CPU resources. Optimizing compilers 6 I C[i] = A[i]-B[i]; is difficult in eliminating these zero-related inefficiencies due to Listing 1. An example code working on redundant zeros, where all variables are 32-bit integers. limitations in static analysis. Hardware approaches, in contrast, optimize inefficiencies without code modification, but are not enough to fulfill the computation, which yields better cache widely adopted in commodity processors. In this paper, we 1 propose ZeroSpy - a fine-grained profiler to identify redundant usage and vectorization potentials . zeros caused by both inappropriate use of data structures and Actually, a larger number of real-world applications (e.g., useless computation. ZeroSpy also provides intuitive optimization deep neural network and high-efficiency video coding) have guidance by revealing the locations where the redundant zeros already been reported to contain a significant amount of happen in source lines and calling contexts. The experimental redundant zeros and achieved significant speedup from the results demonstrate ZeroSpy is capable of identifying redundant zeros in programs that have been highly optimized for years. -
HALO: Post-Link Heap-Layout Optimisation
HALO: Post-Link Heap-Layout Optimisation Joe Savage Timothy M. Jones University of Cambridge, UK University of Cambridge, UK [email protected] [email protected] Abstract 1 Introduction Today, general-purpose memory allocators dominate the As the gap between memory and processor speeds continues landscape of dynamic memory management. While these so- to widen, efficient cache utilisation is more important than lutions can provide reasonably good behaviour across a wide ever. While compilers have long employed techniques like range of workloads, it is an unfortunate reality that their basic-block reordering, loop fission and tiling, and intelligent behaviour for any particular workload can be highly subop- register allocation to improve the cache behaviour of pro- timal. By catering primarily to average and worst-case usage grams, the layout of dynamically allocated memory remains patterns, these allocators deny programs the advantages of largely beyond the reach of static tools. domain-specific optimisations, and thus may inadvertently Today, when a C++ program calls new, or a C program place data in a manner that hinders performance, generating malloc, its request is satisfied by a general-purpose allocator unnecessary cache misses and load stalls. with no intimate knowledge of what the program does or To help alleviate these issues, we propose HALO: a post- how its data objects are used. Allocations are made through link profile-guided optimisation tool that can improve the fixed, lifeless interfaces, and fulfilled by -
6502 Introduction
6502 Introduction Philipp Koehn 18 September 2019 Philipp Koehn Computer Systems Fundamentals: 6502 Introduction 18 September 2019 1 some history Philipp Koehn Computer Systems Fundamentals: 6502 Introduction 18 September 2019 1971 2 • First microprocessor on an integrated circuit: Intel 4004 • 4-bit central processing unit, 12 bit address space (4KB) Philipp Koehn Computer Systems Fundamentals: 6502 Introduction 18 September 2019 1975 3 • MOS Technology 6502 • Dominant CPU in home computers for a decade (Atari, Apple II, Nintendo Entertainment System, Commodore PET) Philipp Koehn Computer Systems Fundamentals: 6502 Introduction 18 September 2019 1977 4 • Atari 2600 • Video game console: Pong, Pac Man, ... connected to TV Philipp Koehn Computer Systems Fundamentals: 6502 Introduction 18 September 2019 1980 5 • Commodore VIC20 • 1 MHz, 5KB RAM, BASIC, 3.5KB RAM, 176x184 3 bit color video Philipp Koehn Computer Systems Fundamentals: 6502 Introduction 18 September 2019 1982 6 • Commodore C64 • 64KB RAM, 320x200 4 bit color video Philipp Koehn Computer Systems Fundamentals: 6502 Introduction 18 September 2019 Commodore C64 7 • BASIC programming language, but serious programs written in assembly • No fancy stuff like multi-process, user accounts, virtual memory, etc. • Machine itself had no mass storage - had to buy tape drive, then floppy disk drive, machine was obsolete once hard drives came around Philipp Koehn Computer Systems Fundamentals: 6502 Introduction 18 September 2019 BASIC Demo 8 • Commands get executed (just like Python interpreter) -
Chapter 4 Memory Management and Virtual Memory Asst.Prof.Dr
Chapter 4 Memory management and Virtual Memory Asst.Prof.Dr. Supakit Nootyaskool IT-KMITL Object • To discuss the principle of memory management. • To understand the reason that memory partitions are importance for system organization. • To describe the concept of Paging and Segmentation. 4.1 Difference in main memory in the system • The uniprogramming system (example in DOS) allows only a program to be present in memory at a time. All resources are provided to a program at a time. Example in a memory has a program and an OS running 1) Operating system (on Kernel space) 2) A running program (on User space) • The multiprogramming system is difference from the mentioned above by allowing programs to be present in memory at a time. All resource must be organize and sharing to programs. Example by two programs are in the memory . 1) Operating system (on Kernel space) 2) Running programs (on User space + running) 3) Programs are waiting signals to execute in CPU (on User space). The multiprogramming system uses memory management to organize location to the programs 4.2 Memory management terms Frame Page Segment 4.2 Memory management terms Frame Page A fixed-lengthSegment block of main memory. 4.2 Memory management terms Frame Page A fixed-length block of data that resides in secondary memory. A page of data may temporarily beSegment copied into a frame of main memory. A variable-lengthMemory management block of data that residesterms in secondary memory. A segment may temporarily be copied into an available region of main memory or the segment may be divided into pages which can be individuallyFrame copied into mainPage memory. -
Download a Sample
Preface Like many American kids in 1979, I woke up to find that Santa had left a brand new Atari VCS1 under the tree (thanks, Mom and Dad, for paying Santa’s invoice!). This was a pretty big deal for a six- year-old who could tell you the location and manufacturer of every standup arcade cabinet within a five mile radius. Having an “arcade in your home” wasn’t just a thing you saw on Silver Spoons, it was now a real thing. The sights and sounds that jumped o↵ of our little Panasonic color TV probably deserve a gigantic run-on sentence worthy of Dylan Thomas, as my brother and I bounced tiny pixellated missiles o↵ of walls in Combat, combed through the perplexing game modes of Space Invaders, battled angry duck-like dragons in Adventure, and became Superman as we put flickering bad guys in a flickering jail. These cartridges were opaque obelisks packaged in boxes with fantastically unattainable illustrations, available at K-Mart for $30 or so. You could tell these species of video games weren’t related to arcade games, though they had a unique look-and-feel of their own. We also had an Apple ][ by this time, so I tried to fit all of these creatures into a digital taxonomy. Atari games had colors and fast motion, but not as much as arcade games, and they never were as complex as Apple ][ games. What made them tick? Why were Activision games so much more detailed? Would the missile still blow up your spaceship if you turned the TV o↵? (Turns out the answer is yes.) 1 It wasn’t sold as “Atari 2600” until 1982. -
Memory Management
Memory Management These slides are created by Dr. Huang of George Mason University. Students registered in Dr. Huang’s courses at GMU can make a single machine readable copy and print a single copy of each slide for their own reference as long as the slide contains the copyright statement, and the GMU facilities are not used to produce the paper copies. Permission for any other use, either in machine-readable or printed form, must be obtained form the author in writing. CS471 1 Memory 0000 A a set of data entries 0001 indexed by addresses 0002 0003 Typically the basic data 0004 0005 unit is byte 0006 0007 In 32 bit machines, 4 bytes 0008 0009 grouped to words 000A 000B Have you seen those 000C 000D DRAM chips in your PC ? 000E 000F CS471 2 1 Logical vs. Physical Address Space The addresses used by the RAM chips are called physical addresses. In primitive computing devices, the address a programmer/processor use is the actual address. – When the process fetches byte 000A, the content of 000A is provided. CS471 3 In advanced computers, the processor operates in a separate address space, called logical address, or virtual address. A Memory Management Unit (MMU) is used to map logical addresses to physical addresses. – Various mapping technologies to be discussed – MMU is a hardware component – Modern processors have their MMU on the chip (Pentium, Athlon, …) CS471 4 2 Continuous Mapping: Dynamic Relocation Virtual Physical Memory Memory Space Processor 4000 The processor want byte 0010, the 4010th byte is fetched CS471 5 MMU for Dynamic Relocation CS471 6 3 Segmented Mapping Virtual Physical Memory Memory Space Processor Obviously, more sophisticated MMU needed to implement this CS471 7 Swapping A process can be swapped temporarily out of memory to a backing store (a hard drive), and then brought back into memory for continued execution. -
The Ultimate C64 Overview Michael Steil, 25Th Chaos Communication Congress 2008
The Ultimate C64 Overview Michael Steil, http://www.pagetable.com/ 25th Chaos Communication Congress 2008 Retrocomputing is cool as never before. People play Look and Feel C64 games in emulators and listen to SID music, but few people know much about the C64 architecture A C64 only needs to be connected to power and a TV and its limitations, and what programming was like set (or monitor) to be fully functional. When turned back then. This paper attempts to give a comprehen- on, it shows a blue-on-blue theme with a startup mes- sive overview of the Commodore 64, including its in- sage and drops into a BASIC interpreter derived from ternals and quirks, making the point that classic Microsoft BASIC. In order to load and save BASIC computer systems aren't all that hard to understand - programs or use third party software, the C64 re- and that programmers today should be more aware of quires mass storage - either a “datasette” cassette the art that programming once used to be. tape drive or a disk drive like the 5.25" Commodore 1541. Commodore History Unless the user really wanted to interact with the BA- SIC interpreter, he would typically only use the BA- Commodore Business Machines was founded in 1962 SIC instructions LOAD, LIST and RUN in order to by Jack Tramiel. The company specialized on elec- access mass storage. LOAD"$",8 followed by LIST tronic calculators, and in 1976, Commodore bought shows the directory of the disk in the drive, and the chip manufacturer MOS Technology and decided LOAD"filename",8 followed by RUN would load and to have Chuck Peddle from MOS evolve their KIM-1 start a program. -
A Hybrid Swapping Scheme Based on Per-Process Reclaim for Performance Improvement of Android Smartphones (August 2018)
Received August 19, 2018, accepted September 14, 2018, date of publication October 1, 2018, date of current version October 25, 2018. Digital Object Identifier 10.1109/ACCESS.2018.2872794 A Hybrid Swapping Scheme Based On Per-Process Reclaim for Performance Improvement of Android Smartphones (August 2018) JUNYEONG HAN 1, SUNGEUN KIM1, SUNGYOUNG LEE1, JAEHWAN LEE2, AND SUNG JO KIM2 1LG Electronics, Seoul 07336, South Korea 2School of Software, Chung-Ang University, Seoul 06974, South Korea Corresponding author: Sung Jo Kim ([email protected]) This work was supported in part by the Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education under Grant 2016R1D1A1B03931004 and in part by the Chung-Ang University Research Scholarship Grants in 2015. ABSTRACT As a way to increase the actual main memory capacity of Android smartphones, most of them make use of zRAM swapping, but it has limitation in increasing its capacity since it utilizes main memory. Unfortunately, they cannot use secondary storage as a swap space due to the long response time and wear-out problem. In this paper, we propose a hybrid swapping scheme based on per-process reclaim that supports both secondary-storage swapping and zRAM swapping. It attempts to swap out all the pages in the working set of a process to a zRAM swap space rather than killing the process selected by a low-memory killer, and to swap out the least recently used pages into a secondary storage swap space. The main reason being is that frequently swap- in/out pages use the zRAM swap space while less frequently swap-in/out pages use the secondary storage swap space, in order to reduce the page operation cost. -
An Evolutionary Study of Linux Memory Management for Fun and Profit Jian Huang, Moinuddin K
An Evolutionary Study of Linux Memory Management for Fun and Profit Jian Huang, Moinuddin K. Qureshi, and Karsten Schwan, Georgia Institute of Technology https://www.usenix.org/conference/atc16/technical-sessions/presentation/huang This paper is included in the Proceedings of the 2016 USENIX Annual Technical Conference (USENIX ATC ’16). June 22–24, 2016 • Denver, CO, USA 978-1-931971-30-0 Open access to the Proceedings of the 2016 USENIX Annual Technical Conference (USENIX ATC ’16) is sponsored by USENIX. An Evolutionary Study of inu emory anagement for Fun and rofit Jian Huang, Moinuddin K. ureshi, Karsten Schwan Georgia Institute of Technology Astract the patches committed over the last five years from 2009 to 2015. The study covers 4587 patches across Linux We present a comprehensive and uantitative study on versions from 2.6.32.1 to 4.0-rc4. We manually label the development of the Linux memory manager. The each patch after carefully checking the patch, its descrip- study examines 4587 committed patches over the last tions, and follow-up discussions posted by developers. five years (2009-2015) since Linux version 2.6.32. In- To further understand patch distribution over memory se- sights derived from this study concern the development mantics, we build a tool called MChecker to identify the process of the virtual memory system, including its patch changes to the key functions in mm. MChecker matches distribution and patterns, and techniues for memory op- the patches with the source code to track the hot func- timizations and semantics. Specifically, we find that tions that have been updated intensively. -
Understanding Memory Resource Management in Vmware Vsphere® 5.0
Understanding Memory Resource Management in ® VMware vSphere 5.0 Performance Study TECHNICAL WHITE PAPER Understanding Memory Resource Management in VMware vSphere 5.0 Table of Contents Overview......................................................................................................................................................................................................................... 3 Introduction................................................................................................................................................................................................................... 3 ESXi Memory Management Overview ............................................................................................................................................................. 4 Terminology .......................................................................................................................................................................................................... 4 Memory Virtualization Basics ........................................................................................................................................................................ 4 Memory Management Basics in ESXi ......................................................................................................................................................... 5 Memory Reclamation in ESXi ..............................................................................................................................................................................