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Low-Cost Epoch-Based Correlation Prefetching for Commercial Applications Yuan Chou Architecture Technology Group Microelectronics Division

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Low-Cost Epoch-Based Correlation Prefetching for Commercial Applications Yuan Chou Architecture Technology Group Microelectronics Division Low-Cost Epoch-Based Correlation Prefetching for Commercial Applications Yuan Chou Architecture Technology Group Microelectronics Division 1 Motivation Performance of many commercial applications limited by processor stalls due to off-chip cache misses Applications characterized by irregular control-flow and complex data access patterns Software prefetching and simple stride-based hardware prefetching ineffective Hardware correlation prefetching more promising - can remember complex recurring data access patterns Current correlation prefetchers have severe drawbacks but we think we can overcome them 2 Talk Outline Traditional Correlation Prefetching Epoch-Based Correlation Prefetching Experimental Results Summary 3 Traditional Correlation Prefetching Basic idea: use current miss address M to predict N future miss addresses F ...F (where N = prefetch depth) 1 N Miss address sequence: A B C D E F G H I assume N=2 Use A to prefetch B C Use D to prefetch E F Use G to prefetch H I Correlations recorded in correlation table Correlation table size proportional to application working set 4 Correlation Prefetching Drawbacks Very large correlation tables needed for commercial apps - impractical to store on-chip No attempt to eliminate all naturally overlapped misses Miss address sequence: A B C D E F G H I time A C F H B D G I E compute off-chip access 5 Correlation Prefetching Drawbacks Very large correlation tables needed for commercial apps - impractical to store on-chip No attempt to eliminate all naturally overlapped misses Miss address sequence: A B C D E F G H I time A C F H B D G I E Since C, D and E naturally overlapped, prefetching only C may not improve performance 5 Correlation Prefetching Drawbacks Very large correlation tables needed for commercial apps - impractical to store on-chip No attempt to eliminate all naturally overlapped misses Prefetches misses naturally overlapped with current miss Miss address sequence: A B C D E F G H I time A C F H B D G I E Since A and B naturally overlapped, prefetching B does not improve performance but wastes table storage 5 Epoch-Based Correlation Prefetching (EBCP) 6 Epoch MLP Model At high off-chip latencies, overlappable off-chip accesses appear to issue and complete together Program execution separates into recurring periods of on- chip computation followed by off-chip accesses time A C F H B D G I E compute off-chip access 7 Epoch MLP Model At high off-chip latencies, overlappable off-chip accesses appear to issue and complete together Program execution separates into recurring periods of on- chip computation followed by off-chip accesses time A C F H B D G I E Epoch i Epoch i+1 Epoch i+2 Epoch i+3 Call each period an epoch 7 Epoch MLP Model At high off-chip latencies, overlappable off-chip accesses appear to issue and complete together Program execution separates into recurring periods of on- chip computation followed by off-chip accesses time A C F H B D G I E Epoch i Epoch i+1 Epoch i+2 Epoch i+3 Call each period an epoch Group off-chip accesses based on which epoch they issue Epoch i i+1 i+2 i+3 Miss addresses A B C D E F G H I 7 Epoch Model Insights Insight #1: Target removal of entire epochs instead of individual misses Miss address sequence: A B C D E F G H I time A C F H B D G I E Epoch i Epoch i+1 Epoch i+2 Epoch i+3 Epoch i i+1 i+2 i+3 Miss addresses A B CX D E XF G H I Use first miss in epoch to prefetch all misses in next 2 epochs Results in removal of 2 epochs 8 Epoch-Based Correlation Prefetcher No prefetching Epoch i i+1 i+2 i+3 Miss addresses A B C D E F G H I Epoch-based correlation prefetching (EBCP) Epoch i i+1 Miss addresses A B H I Prefetches C D E F G Traditional correlation prefetching (depth=2) Epoch i i+1 i+2 Miss addresses A B E H I Prefetches B C D F G EBCP achieves better epoch reduction 9 Epoch Model Insights Insight #2: Hide latency of correlation table access under previous epoch time A C F H B D G I E Epoch i Epoch i+1 Epoch i+2 Epoch i+3 Epoch i i+1 i+2 i+3 Miss addresses A B C D E F G H I Read Prefetches c o r r e l a t io n F G H I table Use miss in epoch i to prefetch all misses in epochs i+2 and i+3 Use epoch i to read correlation table Use epoch i+1 to issue prefetches 10 Epoch Model Insights Insight #2: Hide latency of correlation table access under previous epoch time A C F H B D G I E Epoch i Epoch i+1 Epoch i+2 Epoch i+3 Epoch i i+1 i+2 i+3 Miss addresses A B C D E XF G XH I Read Prefetches c o r r e l a t io n F G H I table Results in removal of 2 epochs Correlation table can be stored in main memory! 10 EBCP Advantages Trad: store correlation table on-chip EBCP: store correlation table in main memory (hide table access latency under previous epoch) Trad: no attempt to eliminate all naturally overlapped misses EBCP: target removal of entire epochs Trad: prefetch misses naturally overlapped with current miss EBCP: avoid prefetching these misses EBCP overcomes drawbacks of traditional correlation prefetchers 11 EBCP Components L1-I L1-I Processor Processor Prefetch Core L1-D Core L1-D Control Crossbar L2 L2 L2 L2 bank bank bank bank Memory Controller Memory Controller Correlation Table Correlation Table DRAM DRAM • Prefetcher control observes all L2 cache requests • L2 banks notify prefetcher control which requests are misses 12 EBCP Prefetcher Control Request OS for memory to store correlation table Detect epochs observe when number of off-chip misses transition 0 to 1 Learn correlations record correlations in main memory correlation table Issue prefetches use first miss address in epoch to look up correlation table select miss addresses from correlation table entry issue prefetches (lower priority than demand accesses) Return memory to OS if needed EBCP very simple and requires almost zero on-chip storage! 13 Experimental Results 14 Baseline Processor Model Moderate out-of-order issue core single thread 4-wide issue 64 entry issue queue, 128 entry reorder buffer 32KB 4-way L1 instruction and data caches 2MB 4-way L2 cache prefetches installed into prefetch buffer Memory bandwidth model 9.6 GB/s read bandwidth 4.8 GB/s write bandwidth 500 cycle unloaded memory latency Commercial applications benchmarks OLTP, TPC-W, SPECjbb2005, SPECjAppServer2004 15 Effects of Prefetch Degree Infinite correlation table 45% OLTP TPC-W SPECjbb SPECjAppServer 40% t n 35% me e v 30% o r p m 25% I e c 20% n ma r 15% o f r e 10% P % 5% 0% 2 4 6 8 2 6 2 2 4 6 8 2 6 2 2 4 6 8 2 6 2 2 4 6 8 2 6 2 1 1 3 1 1 3 1 1 3 1 1 3 Prefetch Degree Performance improvement increases with prefetch degree 16 Coverage vs Accuracy 60% OLTP TPC-W SPECjbb SPECjAppServer 50% e g a 40% r e v 30% o C 20% % 10% 0% 2 4 6 8 2 6 2 2 4 6 8 2 6 2 2 4 6 8 2 6 2 2 4 6 8 2 6 2 1 1 3 1 1 3 1 1 3 1 1 3 Prefetch Degree 50% OLTP TPC-W SPECjbb SPECjAppServer y 40% c a r u 30% c c A 20% % 10% 0% 2 4 6 8 2 6 2 2 4 6 8 2 6 2 2 4 6 8 2 6 2 2 4 6 8 2 6 2 1 1 3 1 1 3 1 1 3 1 1 3 • take-away Prefetch Degree 17 Memory Bandwidth Sensitivity 45% OLTP TPC-W SPECjbb SPECjAppServer 40% t n 35% me e 30% v o r p 25% m I BW=3.2GB/s e 20% BW=6.4GB/s c n 15% BW=9.6GB/s ma r o f 10% r e P 5% % 0% -5% 4 8 6 2 4 8 6 2 4 8 6 2 4 8 6 2 1 3 1 3 1 3 1 3 Prefetch Degree Optimal prefetch degree depends on available memory BW 18 Correlation Table Size Prefetch degree 8 35% OLTP TPC-W SPECjbb SPECjAppServer t 30% n me e 25% v o r p m 20% I e c n 15% ma r o f 10% r e P 5% % 0% K K K K K K K K K K K K K K K K M M M M M M M M M M M M M M M M 4 8 6 2 4 8 6 2 4 8 6 2 4 8 6 2 1 2 4 8 1 2 4 8 1 2 4 8 1 2 4 8 6 2 5 1 6 2 5 1 6 2 5 1 6 2 5 1 1 2 5 1 2 5 1 2 5 1 2 5 Predictor Table Entries Storing table in main memory makes such large sizes practical 19 Comparison with Other Prefetchers Global History Buffer G/AC (GHB) address correlation, unique table storage (small: 256KB large: 4MB) Tag Correlating Prefetcher (TCP) tag correlation (small: 256KB large: 4MB) Stream traditional stride-based stream prefetcher Spatial Memory Streaming (SMS) spatial locality within region (128KB) Solihin memory-side address correlation prefetcher (64MB) Prefetch degree = 6 for all prefetchers (except SMS) Prefetches brought into 64 entry prefetch buffer 20 C o E % Performance Improvement 1 1 2 2 B m 0 5 0 5 0 5 C % % % % % % P p GHB small o GHB large a u TCP small O t r p TCP large LT i e Stream P s r SMS f o Solihin 3,2 o r Solihin 6,1 m EBCP minus n s EBCP a GHB small w l l GHB large i p TCP small TP t r e TCP large h C f Stream - e W SMS t O c Solihin 3,2 h Solihin 6,1 e EBCP minus t h r EBCP s f GHB small e o GHB large r SP r TCP small a E TCP large P l C l Stream j f b SMS r o b Solihin 3,2 e u Solihin 6,1 r f EBCP minus b EBCP e e t SP n GHB small c c E h GHB large C h m TCP small j TCP large A e p a Stream pS r SMS r k e s Solihin 3,2 s r Solihin 6,1 v e EBCP minus r EBCP 2 1 Summary EBCP successfully overcomes drawbacks of traditional correlation prefetchers stores large correlation table in main memory exploits unused memory capacity and bandwidth targets removal of entire epochs very simple prefetcher control almost zero on-chip storage EBCP performs very well on all four commercial benchmarks Future work: efficient implementation for chip multi-processors improved accuracy Epoch-based concept can be applied to other uarch techniques! 22 Yuan Chou [email protected] 28 Prefetch degree 8 Prefetch Buffer Size 1 million table entries 35% OLTP TPC-W SPECjbb SPECjAppServer t n 30% me e v 25% o r p m I 20% e c n 15% ma r o f r 10% e P % 5% 0% 6 2 4 8 6 6 2 4 8 6 6 2 4 8 6 6 2 4 8 6 1 3 6 2 5 1 3 6 2 5 1 3 6 2 5 1 3 6 2 5 1 2 1 2 1 2 1 2 Prefetch Buffer Entries 64 entries sufficient for all four benchmarks 19.
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