Principles of Computer Architecture Chapter 6: Datapath and Control

6-1 Chapter 6: Datapath and Control

Principles of Computer Architecture Miles Murdocca and Vincent Heuring

Chapter 6: Datapath and Control

6.1 Basics of the Microarchitecture 6.2 A Microarchitecture for the ARC 6.3 Hardwired Control 6.4 Case Study: The VHDL Hardware Description Language

• The steps that the control unit carries out in executing a program are: (1) Fetch the next instruction to be executed from memory. (2) Decode the opcode. (3) Read operand(s) from main memory, if any. (4) Execute the instruction and store results. (5) Go to step 1.

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring 6-4 Chapter 6: Datapath and Control High Level View of Microarchitecture • The microarchitecture consists of the control unit and the pro- grammer-visible registers, functional units such as the ALU, and any additional registers that may be required by the control unit.

Registers Control Unit

ALU

Datapath Control Section (Data Section)

SYSTEM BUS

Mnemonic Meaning Memory ld Load a register from memory st Store a register into memory sethi Load the 22 most significant bits of a register andcc Bitwise logical AND Logic orcc Bitwise logical OR orncc Bitwise logical NOR srl Shift right (logical) Arithmetic addcc Add call Call subroutine jmpl Jump and link (return from subroutine call) be Branch if equal Control bneg Branch if negative bcs Branch on carry bvs Branch on overflow ba Branch always

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 SETHI Format 00 rd op2 imm22

Branch Format 000 cond op2 disp22

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 CALL format 01 disp30 i

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 10 rd op3 rs1 0 00000000 rs2 Arithmetic Formats 10 rd op3 rs1 1 simm13

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 11 rd op3 rs1 0 00000000 rs2 Memory Formats 11 rd op3 rs1 1 simm13

op Format op2 Inst. op3 (op=10) op3 (op=11) cond branch 00 SETHI/Branch 010 branch 010000 addcc 000000 ld 0001 be 01 CALL 100 sethi 010001 andcc 000100 st 0101 bcs 10 Arithmetic 010010 orcc 0110 bneg 11 Memory 010110 orncc 0111 bvs 100110 srl 1000 ba 111000 jmpl

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PSR nzvc

3 %r3

4 %r4 C c1 37 b 38 0 B Decoder 5 %r5 c Decoder 37 b %r6 37 6 6 6 %r7 7 From Control 8 %r8 Unit

9 %r9 CLOCK UNIT 10 %r10

. . ARC Datapath .

30 %r30 %r31 32 31

32 %pc 64-to-32 %temp0 MUX 33 %temp1 C Bus 34 MUX 35%temp2

36%temp3

37 %ir MUX Control 32 32 24 Main To Data Line (From 32 Memory Control Unit) F0 F From 32 ALU 1 To Control F2 Control Address To To Address F3 Unit

Unit Memory Main Data From Main Memory Main From Data 4 n, z, v, c Set Condition Codes (SCC) Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring 6-8 Chapter 6: Datapath and Control ARC ALU Operations

F3 F2 F1 F0 Operation Changes Condition Codes

0 0 0 0 ANDCC (A, B) yes 0 0 0 1 ORCC (A, B) yes 0 0 1 0 NORCC (A, B) yes 0 0 1 1 ADDCC (A, B) yes 0 1 0 0 SRL (A, B) no 0 1 0 1 AND (A, B) no 0 1 1 0 OR (A, B) no 0 1 1 1 NOR (A, B) no 1 0 0 0 ADD (A, B) no 1 0 0 1 LSHIFT2 (A) no 1 0 1 0 LSHIFT10 (A) no 1 0 1 1 SIMM13 (A) no 1 1 0 0 SEXT13 (A) no 1 1 0 1 INC (A) no 1 1 1 0 INCPC (A) no 1 1 1 1 RSHIFT5 (A) no

b31 a31 b30 a30 b1 a1 b0 a0 0 Block F0:3 . . . 4 ALU ALU ALU ALU Diagram LUT LUT LUT LUT 31 30 1 0 4 of ALU 2 carry 4 b0-4

z31 z30 z1 z0

BARREL Direction of Shift Barrel Shifter SHIFTER Shift Amount (SA) Control LUT 5

. . . F3 F2

V C N c31 c30 Z c1 c0 SCC: Set Condition Codes

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring 6-10 Chapter 6: Datapath and Control Gate-Level Layout of Barrel Shifter Bit 31 Bit 30 Bit 1 Bit 0 . Bit 3 Bit 2 Bit 29 Bit 28 . .

Shift Right

SA1

. . .

Bit 2 Bit 29

Shift Right

SA0

. . .

F3 F2 F1 F0 Carry ai bi zi Carry In Out 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 1 0 0 0 0 ANDCC 0 0 0 0 1 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 1 0 1 0 1 0 0 0 0 1 0 1 1 1 0 0 0 0 1 1 0 0 0 0 ORCC 0 0 0 1 1 0 1 1 0 ......

Data inputs from C Bus

C31 C30 C0 . . . D Q D Q D Q CLK

Write select (from c1 bit of C Decoder)

. . . A bus enable (from a1 bit of A Decoder) . . . B bus enable (from b1 bit of B Decoder)

A31 A30 A0 B31 B30 B0

Data outputs to A Bus Data outputs to B Bus

Data inputs from C Bus C31 C0

Instruction Register %ir 313029282726252423222120191817161514131211109876543210

Instruction fields rdop2 rs1 rs2 op op3 bit 13

To A Decoder 6 Control Store Address Incrementer (CSAI) 8 A MUX Select MIR 11 100 To C 0, rs1 A field 11 00 = Next Decoder 01 = Jump 5 6 10 = Inst. Dec. 6 Next Decode Jump Microarch- Scratchpad To B Decoder CS Address MUX C MUX 6 11 MIR C field 0, rd

B MUX Select 6 5 MIR itecture of 0, rs2 B field 2048 word × 41 bit Control

Store Select %i Microcode r 5 6 %ir rd rs2 rs1 ops 41 Instruction A B C Register the ARC M M M (MIR) U U U RW

AX BX C X D R ALU COND JUMP ADDR IR[13] CLOCK

Cbus UNIT

32 A bus A Bbus 2 IR[30,31,19-24]

32 32

1 64-to-32 MUX F 0 Control C Bus F1 3 ALU F2 4 branch MUX F 3 logic (CBL) 4 n, z, v, c 4 %psr

Set Condition Codes

Data In RD WR MAIN MEMORY Address 232 byte address Acknowledge (ACK) space Data Out Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring 6-15 Chapter 6: Datapath and Control Microword Format

A B C M M M U U U RW AX BX C X D R ALU COND JUMP ADDR

C2 C1 C0 Operation

0 0 0 Use NEXT ADDR 0 0 1 Use JUMP ADDR if n = 1 0 1 0 Use JUMP ADDR if z = 1 0 1 1 Use JUMP ADDR if v = 1 1 0 0 Use JUMP ADDR if c = 1 1 0 1 Use JUMP ADDR if IR[13] = 1 1 1 0 Use JUMP ADDR 1 1 1 DECODE

op op3

100 IR bits 31 30 24 23 22 21 20 19 op2

Settling time for slave sections of registers. Perform ALU Master sections settle. functions. n, z, v,and c flags become stable.

Clock

Master sections of Slave sections of registers loaded on registers loaded on rising edge falling edge

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring Address Operation Statements Comment 6-19 Chapter 6: Datapath and Control 0000: R[ir] ← AND(R[pc],R[pc]); READ;/ Read an ARC instruction from main memory 0001: DECODE; / 256-way jump according to opcode 00// / sethi 1152: R[rd] ← LSHIFT10(ir); GOTO 2047;/ Copy imm22 field to target register 00// / call 1280: R[15] ← AND(R[pc],R[pc]); / Save %pc in %r15 1281: R[temp0] ← ADD(R[ir],R[ir]); / Shift disp30 field left 1282: R[temp0] ← ADD(R[temp0],R[temp0]);/ Shift again 1283: R[pc] ← ADD(R[pc],R[temp0]); / Jump to subroutine GOTO 0; 0//0 / addcc 1600: IF R[IR[13]] THEN GOTO 1602; / Is second source operand immediate? 1601: R[rd] ← ADDCC(R[rs1],R[rs2]); / Perform ADDCC on register sources GOTO 2047; Partial ARC 1602: R[temp0] ← SEXT13(R[ir]); / Get sign extended simm13 field 1603: R[rd] ← ADDCC(R[rs1],R[temp0]);/ Perform ADDCC on register/simm13 GOTO 2047; / sources 00// / andcc Microprogram 1604: IF R[IR[13]] THEN GOTO 1606; / Is second source operand immediate? 1605: R[rd] ← ANDCC(R[rs1],R[rs2]); / Perform ANDCC on register sources GOTO 2047; 1606: R[temp0] ← SIMM13(R[ir]); / Get simm13 field 1607: R[rd] ← ANDCC(R[rs1],R[temp0]);/ Perform ANDCC on register/simm13 GOTO 2047; / sources 00// / orcc 1608: IF R[IR[13]] THEN GOTO 1610; / Is second source operand immediate? 1609: R[rd] ← ORCC(R[rs1],R[rs2]); / Perform ORCC on register sources GOTO 2047; 1610: R[temp0] ← SIMM13(R[ir]); / Get simm13 field 1611: R[rd] ← ORCC(R[rs1],R[temp0]);/ Perform ORCC on register/simm13 sources GOTO 2047; 00// / orncc 1624: IF R[IR[13]] THEN GOTO 1626; / Is second source operand immediate? 1625: R[rd] ← NORCC(R[rs1],R[rs2]); / Perform ORNCC on register sources GOTO 2047; 1626: R[temp0] ← SIMM13(R[ir]); / Get simm13 field 1627: R[rd] ← NORCC(R[rs1],R[temp0]);/ Perform NORCC on register/simm13 GOTO 2047; / sources 00// / srl 1688: IF R[IR[13]] THEN GOTO 1690; / Is second source operand immediate? 1689: R[rd] ← SRL(R[rs1],R[rs2]); / Perform SRL on register sources GOTO 2047; 1690: R[temp0] ← SIMM13(R[ir]); / Get simm13 field 1691: R[rd] ← SRL(R[rs1],R[temp0]); / Perform SRL on register/simm13 sources GOTO 2047; 00// / jmpl 1760: IF R[IR[13]] THEN GOTO 1762; / Is second source operand immediate? 1761: R[pc] ← ADD(R[rs1],R[rs2]); / Perform ADD on register sources Principles of Computer Architecture by M. Murdocca and V. Heuring GOTO 0; © 1999 M. Murdocca and V. Heuring 1762: R[temp0] ← SEXT13(R[ir]); / Get sign extended simm13 field 6-20 1763: R[pc] ← ADD(R[rs1],R[temp0]);Chapter / Perform 6: ADDDatapath on register/simm13 and Control sources GOTO 0; 00// / ld 1792: R[temp0] ← ADD(R[rs1],R[rs2]); / Compute source address IF R[IR[13]] THEN GOTO 1794; 1793: R[rd] ← AND(R[temp0],R[temp0]);/ Place source address on A bus READ; GOTO 2047; 1794: R[temp0] ← SEXT13(R[ir]); / Get simm13 field for source address 1795: R[temp0] ← ADD(R[rs1],R[temp0]); / Compute source address GOTO 1793; 00// / st Partial ARC 1808: R[temp0] ← ADD(R[rs1],R[rs2]); / Compute destination address IF R[IR[13]] THEN GOTO 1810; 1809: R[ir] ← RSHIFT5(R[ir]); GOTO 40;/ Move rd field into position of rs2 field 40: R[ir] ← RSHIFT5(R[ir]); / by shifting to the right by 25 bits. Microprogram 41: R[ir] ← RSHIFT5(R[ir]); 42: R[ir] ← RSHIFT5(R[ir]); 43: R[ir] ← RSHIFT5(R[ir]); 44: R[0] ← AND(R[temp0], R[rs2]);/ Place destination address on A bus and WRITE; GOTO 2047; / place operand on B bus (cont’) 1810: R[temp0] ← SEXT13(R[ir]); / Get simm13 field for destination address 1811: R[temp0] ← ADD(R[rs1],R[temp0]); / Compute destination address GOTO 1809; 00// / Branch instructions: ba, be, bcs, bvs, bneg 1088: GOTO 2; / Decoding tree for branches 2: R[temp0] ← LSHIFT10(R[ir]); / Sign extend the 22 LSB’s of %temp0 3: R[temp0] ← RSHIFT5(R[temp0]); / by shifting left 10 bits, then right 10 4: R[temp0] ← RSHIFT5(R[temp0]); / bits. RSHIFT5 does sign extension. 5: R[ir] ← RSHIFT5(R[ir]); / Move COND field to IR[13] by 6: R[ir] ← RSHIFT5(R[ir]); / applying RSHIFT5 three times. (The 7: R[ir] ← RSHIFT5(R[ir]); / sign extension is inconsequential.) 8: IF R[IR[13]] THEN GOTO 12; / Is it ba? R[ir] ← ADD(R[ir],R[ir]); 9: IF R[IR[13]] THEN GOTO 13; / Is it not be? R[ir] ← ADD(R[ir],R[ir]); 10: IF Z THEN GOTO 12; / Execute be R[ir] ← ADD(R[ir],R[ir]); 11: GOTO 2047; / Branch for be not taken 12: R[pc] ← ADD(R[pc],R[temp0]); / Branch is taken GOTO 0; 13: IF R[IR[13]] THEN GOTO 16; / Is it bcs? R[ir] ← ADD(R[ir],R[ir]); 14: IF C THEN GOTO 12; / Execute bcs 15: GOTO 2047; / Branch for bcs not taken 16: IF R[IR[13]] THEN GOTO 19; / Is it bvs? 17: IF N THEN GOTO 12; / Execute bneg 18: GOTO 2047; / Branch for bneg not taken 19: IF V THEN GOTO 12; / Execute bvs Principles of Computer Architecture by M. Murdocca and V. Heuring 20: GOTO 2047; ©/ Branch 1999 forM. bvs Murdocca not taken and V. Heuring 2047: R[pc] ← INCPC(R[pc]); GOTO 0; / Increment %pc and start over 6-21 Chapter 6: Datapath and Control Branch Decoding

• Decoding tree for branch instructions shows correspond- Line 8 IR[28] ing microprogram 01 lines: IR[27] Line 9 Line 12 ba 01

IR[26] Line 13 be Line 10 cond 01 28 27 26 25 branch 0 0 0 1 be IR[25] Line 16 0 1 0 1 bcs Line 14 bcs 0 1 1 0 bneg 01 0 1 1 1 bvs 1 0 0 0 ba

Line 17 bneg bvs Line 19

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring 6-22 A B C Chapter 6: Datapath and Control M M M Microstore U U U RW Address AX BX C X D R ALU COND JUMP ADDR 0 10 0000010 000001 00101010010100000000000000 1 00 0000000 000000 00000000010111100000000000 1152 10 0101000 000000 00000100101011011111111111 1280 10 0000010 000000 01111000010100000000000000 1281 10 0101010 010101 00001000100000000000000000 Assembled 1282 10 0001010 000101 00001000100000000000000000 1283 10 0000010 000101 00000000100011000000000000 1600 00 0000000 000000 00000000010110111001000010 1601 00 0000100 000010 00000100001111011111111111 ARC 1602 10 0101000 000001 00001000110000000000000000 1603 00 0000110 000100 00000100001111011111111111 1604 00 0000000 000000 00000000010110111001000110 Microprogram 1605 00 0000100 000010 00000100000011011111111111 1606 10 0101000 000001 00001000101100000000000000 1607 00 0000110 000100 00000100000011011111111111 1608 00 0000000 000000 00000000010110111001001010 1609 00 0000100 000010 00000100000111011111111111 1610 10 0101000 000001 00001000101100000000000000 1611 00 0000110 000100 00000100000111011111111111 1624 00 0000000 000000 00000000010110111001011010 1625 00 0000100 000010 00000100001011011111111111 1626 10 0101000 000001 00001000101100000000000000 1627 00 0000110 000100 00000100001011011111111111 1688 00 0000000 000000 00000000010100011010011010 1689 00 0000100 000010 00000100010011011111111111 1690 10 0101000 000001 00001000101100000000000000 1691 00 0000110 000100 00000100010011011111111111 1760 00 0000000 000000 00000000010110111011100010 1761 00 0000100 000011 00000000100011000000000000 1762 10 0101000 000001 00001000110000000000000000 1763 00 0000110 000101 00000000100011000000000000 1792 0 0 0000100 000011 00001000100010111100000010 Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring 6-23 A B C Chapter 6: Datapath and Control M M M U U U RW AX BX C X D R ALU COND JUMP ADDR 1793 1000 000101 000100 0000110010111011111111111 1794 1000 010100 000001 0001000110000000000000000 1795 0000 000011 000101 0001000100011011100000001 Assembled 1808 0000 000010 000011 0001000100010111100010010 1809 1000 010100 000001 0101000111111000000101000 40 1000 010100 000001 0101000111100000000000000 ARC 41 1000 010100 000001 0101000111100000000000000 42 1000 010100 000001 0101000111100000000000000 43 1000 010100 000001 0101000111100000000000000 Microprogram 44 1000 000100 000010 0000001010111011111111111 1810 1000 010100 000001 0001000110000000000000000 1811 0000 000011 000101 0001000100011011100010001 (cont’) 1088 0000 000000 000000 0000000010111000000000010 2 1000 010100 000001 0001000101000000000000000 3 1000 000100 000001 0001000111100000000000000 4 1000 000100 000001 0001000111100000000000000 5 1000 010100 000001 0101000111100000000000000 6 1000 010100 000001 0101000111100000000000000 7 1000 010100 000001 0101000111100000000000000 8 1000 010101 010001 0101000100010100000001100 9 1000 010101 010001 0101000100010100000001101 10 1000 010101 010001 0101000100001000000001100 11 0000 000000 000000 0000000010111011111111111 12 1000 000001 000101 0000000100011000000000000 13 1000 010101 010101 0101000100010100000010000 14 0000 000000 000000 0000000010110000000001100 15 0000 000000 000000 0000000010111011111111111 16 0000 000000 000000 0000000010110100000010011 17 0000 000000 000000 0000000010100100000001100 18 0000 000000 000000 0000000010111011111111111 19 0000 000000 000000 0000000010101100000001100 20 0000 000000 000000 0000000010111011111111111 Principles of Computer Architecture by M. Murdocca and2047 V. Heuring1000 000000 000001 000000011101100000000000 © 1999 M. Murdocca and V. Heuring0 6-24 Chapter 6: Datapath and Control Example: Add the subcc Instruction • Consider adding instruction subcc (subtract) to the ARC instruction set. subcc uses the Arithmetic format and op3 = 001100. 1584: R[temp0] ← SEXT13(R[ir]); / Extract rs2 operand IF IR[13] THEN GOTO 1586; / Is second source immediate? 1585: R[temp0] ← R[rs2]; / Extract sign extended immediate operand 1586: R[temp0] ← NOR(R[temp0], R[0]); / Form one’s complement of subtrahend 1587: R[temp0] ← INC(R[temp0]); GOTO 1603; / Form two’s complement of subtrahend

A B C M M M U U U RW AX BX C X D R ALU COND JUMP ADDR 1584 1000001010 000001 0001000110010111000110010

1585 00100000000 00001 0001000100000000000000000

1586 10100000010 00000 0001000011100000000000000

1587 10100000010 00000 0001000110111011001000011

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring 6-25 Chapter 6: Datapath and Control Branch Table • A branch table for trap handlers and interrupt service routines: AddressContents Trap Handler . . . 60JUMP TO 2000 Illegal instruction 64JUMP TO 3000 Overflow 68JUMP TO 3600 Underflow 72JUMP TO 5224 Zerodivide 76JUMP TO 4180 Disk 80JUMP TO 5364 Printer 84JUMP TO 5908 TTY 88JUMP TO 6048 Timer . . .

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring 6-26 Chapter 6: Datapath and Control Microprogramming vs. Nanoprogramming   k = log2(n)   = log2(100) w = 41 bits = 7 bits • (a) Micropro- gramming vs.

(b) nano- m

Micro- nanowords 100 = programming. Original program Microprogram

w = 41 bits

= 2048 words 2048 = words 2048 =

n n

Total Area = n × w = Microprogram Area = n × k = 2048 × 7 2048 × 41 = 83,968 bits = 14,336 bits Nanoprogram Area = m × w = 100 × 41 = 4100 bits Total Area = 14,336 + 4100 = 18,436 bits (a) (b) Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring 6-27 Chapter 6: Datapath and Control Hardware Description Language MODULE: MOD_4_COUNTER. INPUTS: x. Preamble OUTPUTS: Z[2]. MEMORY: • HDL sequence ← for a resettable 0: Z 0,0; GOTO {0 CONDITIONED ON x, modulo 4 1 CONDITIONED ON x}. counter. 1: Z ← 0,1; GOTO {0 CONDITIONED ON x, Statements 2 CONDITIONED ON x}. 2: Z ← 1,0; GOTO {0 CONDITIONED ON x, 3 CONDITIONED ON x}. 3: Z ← 1,1; GOTO 0.

END SEQUENCE. Epilogue END MOD_4_COUNTER.

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring 6-28 Chapter 6: Datapath and Control Circuit Derived from HDL • Logic design for a modulo 4 counter described in HDL.

Z[0]

Z[1] DATA SECTION

CONTROL SECTION

D Q D Q D Q D Q 0 123 CLK

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring MODULE: ARC_CONTROL_UNIT. 6-29 INPUTS: Chapter 6: Datapath and Control OUTPUTS: C, N, V, Z. ! These are set by the ALU MEMORY: R[16][32], pc[32], ir[32], temp0[32], temp1[32], temp2[32], temp3[32].

0: ir ← AND(pc, pc); Read ← 1; ! Instruction fetch HDL for ARC ! Decode op field 1: GOTO {2 CONDITIONED ON ir[31]×ir[30], ! Branch/sethi format: op=00 4 CONDITIONED ON ir[31]×ir[30], ! Call format: op=01 8 CONDITIONED ON ir[31]×ir[30], ! Arithmetic format: op=10 10 CONDITIONED ON ir[31]×ir[30]}. ! Memory format: op=11 ! Decode op2 field 2: GOTO 19 CONDITIONED ON ir[24]. ! Goto 19 if Branch format • HDL description of the 3: R[rd] ← ir[imm22]; ! sethi GOTO 20. ARC control unit. 4: R[15] ← AND(pc, pc). ! call: save pc in register 15 5: temp0 ← ADD(ir, ir). ! Shift disp30 field left 6: temp0 ← ADD(ir, ir). ! Shift again 7: pc ← ADD(pc, temp0); GOTO 0. ! Jump to subroutine ! Get second source operand into temp0 for Arithmetic format 8: temp0 ← { SEXT13(ir) CONDITIONED ON ir[13]×NOR(ir[19:22]), ! addcc R[rs2] CONDITIONED ON ir[13]×NOR(ir[19:22]), ! addcc SIMM13(ir) CONDITIONED ON ir[13]×OR(ir[19:22]), ! Remaining R[rs2] CONDITIONED ON ir[13]×OR(ir[19:22])}. ! Arithmetic instructions ! Decode op3 field for Arithmetic format 9: R[rd] ← { ADDCC(R[rs1], temp0) CONDITIONED ON XNOR(IR[19:24], 010000), ! addcc ANDCC(R[rs1], temp0) CONDITIONED ON XNOR(IR[19:24], 010001), ! andcc ORCC(R[rs1], temp0) CONDITIONED ON XNOR(IR[19:24], 010010), ! orcc NORCC(R[rs1], temp0) CONDITIONED ON XNOR(IR[19:24], 010110), ! orncc SRL(R[rs1], temp0) CONDITIONED ON XNOR(IR[19:24], 100110), ! srl ADD(R[rs1], temp0) CONDITIONED ON XNOR(IR[19:24], 111000)}; ! jmpl GOTO 20. ! Get second source operand into temp0 for Memory format 10: temp0 ← {SEXT13(ir) CONDITIONED ON ir[13], R[rs2] CONDITIONED ON ir[13]}. 11: temp0 ← ADD(R[rs1], temp0). ! Decode op3 field for Memory format GOTO {12 CONDITIONED ON ir[21], ! ld 13 CONDITIONED ON ir[21]}. ! st Principles of Computer Architecture by M. Murdocca and V. Heuring12: R[rd] ← AND(temp0, temp0); Read ← 1; © GOTO 1999 20.M. Murdocca and V. Heuring 13: ir ← RSHIFT5(ir). 6-30 Chapter 6: Datapath and Control

HDL for ARC 14: ir ← RSHIFT5(ir). 15: ir ← RSHIFT5(ir). (cont’) 16: ir ← RSHIFT5(ir). 17: ir ← RSHIFT5(ir). 18: r0 ← AND(temp0, R[rs2]); Write ← 1; GOTO 20. 19: pc ← { ! Branch instructions ADD(pc, temp0) CONDITIONED ON ir[28] + ir[28]×ir[27]×Z + ir[28]×ir[27]×ir[26]×C + ir[28]×ir[27]×ir[26]×ir[25]×N + ir[28]×ir[27]×ir[26]×ir[25]×V, INCPC(pc) CONDITIONED ON ir[28]×ir[27]×Z + ir[28]×ir[27]×ir[26]×C + ir[28]×ir[27]×ir[26]×ir[25]×N + ir[28]×ir[27]×ir[26]×ir[25]×V}; GOTO 0. 20: pc ← INCPC(pc); GOTO 0. END SEQUENCE. END ARC_CONTROL_UNIT.

IR[30] IR[24] IR[31] CS0 CS3 HDL ARC D Q D Q D Q D Q 0 1 2 3 Circuit CLK

CS4 CS6 D Q D Q D Q D Q CS0 4 5 6 7 CS • The hardwired con- 5

trol section of the IR[21]

CS ARC: generation of CS10 11 D Q D Q CS9 D Q D Q 8 9 10 11 the control signals. CS8

CS13 CS14 D Q CS12 D Q D Q D Q CS15 12 13 14 15

CS19 CS16 CS17 D Q D Q D Q CS18 D Q 16 17 18 19

0 A[1] IR[24] CS3 CS2 CS IR[23] CS 0 4 CS CS5 IR[22] 1 IR[21] IR[13] 0 A[3] IR[21] CS6 CS CS

IR[19] ALU[0] 8 12 0 A[4] IR[20] IR[13] IR[22] IR[13] • Hardwired con- CS8 A[0] IR[19] CS10 CS13 trol section of CS15 A[2] CS14 CS IR[23] IR[24] CS16 18 CS18 Write CS CS 17 the ARC: sig- IR[20] 9 CS

CS8 7 CS0 IR[22] IR[21] IR[19] CS CS4 17 BMUX A[5] CS nals from the CS CS20 10 CS IR[13] 16 19 CS20 IR[13] IR[19] CS18 IR[20] ALU[1] data section of IR[21] C[2] CS IR[22] CS8 CS 3 13 CS CS CMUX CS19 15 9 the control unit CS14 CS12 C[1] IR[13] CS CS 9 to the IR[28] 8 AMUX IR[19] CS CS11 IR[27] CS 2 B[0] Z IR[20] CS12 4 CS datapath. IR[21] CS 1 IR[22] CS 3 CS IR[28] IR[28] 10 0 Read IR[27] CS19 CS IR[26] 12 C ALU[2] B[1] IR[28] C[0] IR[27] CS14 IR[26] CS 13 CS18 IR[25] N CS15 CS20 B[2] IR[28] CS17 CS16 C[3]

IR[27] IR[19]

IR[24] IR[23]

IR[26] IR[22] IR[20] CS9 IR[25] IR[21] B[3] C CS5 IR[24] CS CS6 11 CS9 CS C[4] CS8 7 IR[23] B[4] ALU[3] IR[22] CS13 IR[21] IR[19] CS15 IR[20] CS14 CS16 CS20 C[5] B[5] CS19 CS17

• The majority function. a) truth table, b) AND-OR implementation, c) black box representation.

Minterm ABC F ABC Index 0 0 0 0 0 ABC 1 0 0 1 0 2 0 1 0 0 A B C Majority 3 0 1 1 1 A B C Function 4 1 0 0 0 F

5 1 0 1 1 A B C 6 1 1 0 1 A B C F 7 1 1 1 1

a) b) c)

Interface specification for the majority component -- Interface entity MAJORITY is port (A_IN, B_IN, C_IN: in BIT F_OUT: out BIT); end MAJORITY;

Behavioral model for the majority component -- Body architecture LOGIC_SPEC of MAJORITY is begin -- compute the output using a Boolean expression F_OUT <= (not A_IN and B_IN and C_IN) or (A_IN and not B_IN and C_IN) or (A_IN and B_IN and not C_IN) or (A_IN and B_IN and C_IN) after 4 ns; end LOGIC_SPEC;

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring 6-35 Chapter 6: Datapath and Control VHDL Specification (cont’) -- Package declaration, in library WORK package LOGIC_GATES is component AND3 port (A, B, C : in BIT; X : out BIT); end component; component OR4 port (A, B, C, D : in BIT; X : out BIT); end component; component NOT1 port (A : in BIT; X : out BIT); end component;

-- Interface entity MAJORITY is port (A_IN, B_IN, C_IN: in BIT F_OUT: out BIT); end MAJORITY;

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring 6-36 Chapter 6: Datapath and Control VHDL Specification (cont’) -- Body -- Uses components declared in package LOGIC_GATES -- in the WORK library -- import all the components in WORK.LOGIC_GATES use WORK.LOGIC_GATES.all architecture LOGIC_SPEC of MAJORITY is -- declare signals used internally in MAJORITY signal A_BAR, B_BAR, C_BAR, I1, I2, I3, I4: BIT; begin -- connect the logic gates NOT_1 : NOT1 port map (A_IN, A_BAR); NOT_2 : NOT1 port map (B_IN, B_BAR); NOT_3 : NOT1 port map (C_IN, C_BAR); AND_1 : AND3 port map (A_BAR, B_IN, C_IN, I1); AND_2 : AND3 port map (A_IN, B_BAR, C_IN, I2); AND_3 : AND3 port map (A_IN, B_IN, C_BAR, I3); AND_4 : AND3 port map (A_IN, B_IN, C_IN, I4); OR_1 : OR3 port map (I1, I2, I3, I4, F_OUT); end LOGIC_SPEC;