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Principles of Computer Architecture Chapter 6: Datapath and Control 6-1 Chapter 6: Datapath and Control Principles of Computer Architecture Miles Murdocca and Vincent Heuring Chapter 6: Datapath and Control Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring 6-2 Chapter 6: Datapath and Control Chapter Contents 6.1 Basics of the Microarchitecture 6.2 A Microarchitecture for the ARC 6.3 Hardwired Control 6.4 Case Study: The VHDL Hardware Description Language Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring 6-3 Chapter 6: Datapath and Control The Fetch-Execute Cycle • The steps that the control unit carries out in executing a program are: (1) Fetch the next instruction to be executed from memory. (2) Decode the opcode. (3) Read operand(s) from main memory, if any. (4) Execute the instruction and store results. (5) Go to step 1. Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring 6-4 Chapter 6: Datapath and Control High Level View of Microarchitecture • The microarchitecture consists of the control unit and the pro- grammer-visible registers, functional units such as the ALU, and any additional registers that may be required by the con- trol unit. Registers Control Unit ALU Datapath Control Section (Data Section) SYSTEM BUS Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring 6-5 Chapter 6: Datapath and Control ARC Instruction Subset Mnemonic Meaning Memory ld Load a register from memory st Store a register into memory sethi Load the 22 most significant bits of a register andcc Bitwise logical AND Logic orcc Bitwise logical OR orncc Bitwise logical NOR srl Shift right (logical) Arithmetic addcc Add call Call subroutine jmpl Jump and link (return from subroutine call) be Branch if equal Control bneg Branch if negative bcs Branch on carry bvs Branch on overflow ba Branch always Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring 6-6 Chapter 6: Datapath and Control ARC Instruction Formats op 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 SETHI Format 00 rd op2 imm22 Branch Format 000 cond op2 disp22 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 CALL format 01 disp30 i 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 10 rd op3 rs1 0 00000000 rs2 Arithmetic Formats 10 rd op3 rs1 1 simm13 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 11 rd op3 rs1 0 00000000 rs2 Memory Formats 11 rd op3 rs1 1 simm13 op Format op2 Inst. op3 (op=10) op3 (op=11) cond branch 00 SETHI/Branch 010 branch 010000 addcc 000000 ld 0001 be 01 CALL 100 sethi 010001 andcc 000100 st 0101 bcs 10 Arithmetic 010010 orcc 0110 bneg 11 Memory 010110 orncc 0111 bvs 100110 srl 1000 ba 111000 jmpl 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PSR nzvc Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring 6-7 C bus A bus B bus Chapter 6: Datapath and Control a 0 %r0 38 0 A Decoder 1 %r1 a37 6 2 %r2 3 %r3 4 %r4 C c1 37 b 38 0 B Decoder 5 %r5 c Decoder 37 b %r6 37 6 6 6 %r7 7 From Control 8 %r8 Unit 9 %r9 CLOCK UNIT 10 %r10 . ARC Datapath . 30 %r30 %r31 32 31 32 %pc 64-to-32 %temp0 MUX 33 %temp1 C Bus 34 MUX 35%temp2 36%temp3 37 %ir MUX Control 32 32 24 Main Data To Line (From 32 Memory Control Unit) F0 F From 32 ALU 1 To Control F2 Control Address To F3 Unit Unit Main Memory Data From Main Memory Data 4 n, z, v, c Set Condition Codes (SCC) Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring 6-8 Chapter 6: Datapath and Control ARC ALU Operations F3 F2 F1 F0 Operation Changes Condition Codes 0 0 0 0 ANDCC (A, B) yes 0 0 0 1 ORCC (A, B) yes 0 0 1 0 NORCC (A, B) yes 0 0 1 1 ADDCC (A, B) yes 0 1 0 0 SRL (A, B) no 0 1 0 1 AND (A, B) no 0 1 1 0 OR (A, B) no 0 1 1 1 NOR (A, B) no 1 0 0 0 ADD (A, B) no 1 0 0 1 LSHIFT2 (A) no 1 0 1 0 LSHIFT10 (A) no 1 0 1 1 SIMM13 (A) no 1 1 0 0 SEXT13 (A) no 1 1 0 1 INC (A) no 1 1 1 0 INCPC (A) no 1 1 1 1 RSHIFT5 (A) no Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring 6-9 Chapter 6: Datapath and Control b31 a31 b30 a30 b1 a1 b0 a0 0 Block F0:3 . 4 ALU ALU ALU ALU Diagram LUT LUT LUT LUT 31 30 1 0 4 of ALU 2 carry 4 b0-4 z31 z30 z1 z0 BARREL Direction of Shift Barrel Shifter SHIFTER Shift Amount (SA) Control LUT 5 . F3 F2 V C N c31 c30 Z c1 c0 SCC: Set Condition Codes Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring 6-10 Chapter 6: Datapath and Control Gate-Level Layout of Barrel Shifter Bit 31 Bit 30 Bit 1 Bit 0 . Bit 3 Bit 2 Bit 29 Bit 28 . Shift Right SA1 . Bit 2 Bit 29 Shift Right SA0 . c31 c30 c1 c0 Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring 6-11 Chapter 6: Datapath and Control Truth Table for (Most of the) ALU LUTs F3 F2 F1 F0 Carry ai bi zi Carry In Out 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 1 0 0 0 0 ANDCC 0 0 0 0 1 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 1 0 1 0 1 0 0 0 0 1 0 1 1 1 0 0 0 0 1 1 0 0 0 0 ORCC 0 0 0 1 1 0 1 1 0 . Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring 6-12 Chapter 6: Datapath and Control Design of Register %r1 Data inputs from C Bus C31 C30 C0 . D Q D Q D Q CLK Write select (from c1 bit of C Decoder) . A bus enable (from a1 bit of A Decoder) . B bus enable (from b1 bit of B Decoder) A31 A30 A0 B31 B30 B0 Data outputs to A Bus Data outputs to B Bus Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring 6-13 Chapter 6: Datapath and Control Outputs to Control Unit from Register %ir Data inputs from C Bus C31 C0 Instruction Register %ir 313029282726252423222120191817161514131211109876543210 Instruction fields rdop2 rs1 rs2 op op3 bit 13 Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring 6-14 Chapter 6: Datapath and Control Data Section (Datapath) Control Section To A Decoder 6 Control Store Address Incrementer (CSAI) 8 A MUX Select MIR 11 100 To C 0, rs1 A field 11 00 = Next Decoder 01 = Jump 5 6 10 = Inst. Dec. 6 Next Decode Jump Microarch- Scratchpad To B Decoder CS Address MUX C MUX 6 11 MIR C field 0, rd B MUX Select 6 5 MIR itecture of 0, rs2 B field 2048 word × 41 bit Control Store Select %i Microcode r 5 6 %ir rd rs2 rs1 ops 41 Instruction A B C Register the ARC M M M (MIR) U U U RW AX BX C X D R ALU COND JUMP ADDR IR[13] CLOCK C bus UNIT 32 A bus B bus 2 IR[30,31,19-24] 32 32 1 64-to-32 MUX F 0 Control C Bus F1 3 ALU F2 4 branch MUX F 3 logic (CBL) 4 n, z, v, c 4 %psr Set Condition Codes Data In RD WR MAIN MEMORY Address 232 byte address Acknowledge (ACK) space Data Out Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring 6-15 Chapter 6: Datapath and Control Microword Format A B C M M M U U U RW AX BX C X D R ALU COND JUMP ADDR Principles of Computer Architecture by M.
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