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Instruction Set Assembly Guide for Armv7 and Earlier Arm® Architectures Version 2.0

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Instruction Set Assembly Guide for Armv7 and Earlier Arm® Architectures Version 2.0 Instruction Set Assembly Guide for Armv7 and earlier Arm® architectures Version 2.0 Reference Guide Copyright © 2018, 2019 Arm Limited or its affiliates. All rights reserved. 100076_0200_00_en Instruction Set Assembly Guide for Armv7 and earlier Arm® architectures Instruction Set Assembly Guide for Armv7 and earlier Arm® architectures Reference Guide Copyright © 2018, 2019 Arm Limited or its affiliates. All rights reserved. Release Information Document History Issue Date Confidentiality Change 0100-00 25 October 2018 Non-Confidential First Release 0200-00 09 October 2019 Non-Confidential Second Release. The title and scope of the document has changed. Non-Confidential Proprietary Notice This document is protected by copyright and other related rights and the practice or implementation of the information contained in this document may be protected by one or more patents or pending patent applications. No part of this document may be reproduced in any form by any means without the express prior written permission of Arm. No license, express or implied, by estoppel or otherwise to any intellectual property rights is granted by this document unless specifically stated. Your access to the information in this document is conditional upon your acceptance that you will not use or permit others to use the information for the purposes of determining whether implementations infringe any third party patents. THIS DOCUMENT IS PROVIDED “AS IS”. ARM PROVIDES NO REPRESENTATIONS AND NO WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, SATISFACTORY QUALITY, NON-INFRINGEMENT OR FITNESS FOR A PARTICULAR PURPOSE WITH RESPECT TO THE DOCUMENT. For the avoidance of doubt, Arm makes no representation with respect to, and has undertaken no analysis to identify or understand the scope and content of, third party patents, copyrights, trade secrets, or other rights. This document may include technical inaccuracies or typographical errors. TO THE EXTENT NOT PROHIBITED BY LAW, IN NO EVENT WILL ARM BE LIABLE FOR ANY DAMAGES, INCLUDING WITHOUT LIMITATION ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY, ARISING OUT OF ANY USE OF THIS DOCUMENT, EVEN IF ARM HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. This document consists solely of commercial items. You shall be responsible for ensuring that any use, duplication or disclosure of this document complies fully with any relevant export laws and regulations to assure that this document or any portion thereof is not exported, directly or indirectly, in violation of such export laws. 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Other brands and names mentioned in this document may be the trademarks of their respective owners. Please follow Arm’s trademark usage guidelines at http://www.arm.com/company/policies/ trademarks. Copyright © 2018, 2019 Arm Limited (or its affiliates). All rights reserved. Arm Limited. Company 02557590 registered in England. 110 Fulbourn Road, Cambridge, England CB1 9NJ. LES-PRE-20349 100076_0200_00_en Copyright © 2018, 2019 Arm Limited or its affiliates. All rights 2 reserved. Non-Confidential Instruction Set Assembly Guide for Armv7 and earlier Arm® architectures Confidentiality Status This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. Unrestricted Access is an Arm internal classification. Product Status The information in this document is Final, that is for a developed product. Web Address www.arm.com 100076_0200_00_en Copyright © 2018, 2019 Arm Limited or its affiliates. All rights 3 reserved. Non-Confidential Contents Instruction Set Assembly Guide for Armv7 and earlier Arm® architectures Reference Guide Preface About this book ..................................................... ..................................................... 20 Part A Instruction Set Overview Chapter A1 Overview of AArch32 state A1.1 Terminology ..................................................... ..................................................... A1-26 A1.2 Changing between A32 and T32 instruction set states .................... .................... A1-27 A1.3 Processor modes, and privileged and unprivileged software execution ....... ....... A1-28 A1.4 Processor modes in Armv6-M, Armv7-M, and Armv8-M ................... ................... A1-29 A1.5 Registers in AArch32 state .................................................................................... A1-30 A1.6 General-purpose registers in AArch32 state ............................ ............................ A1-32 A1.7 Register accesses in AArch32 state .................................. .................................. A1-33 A1.8 Predeclared core register names in AArch32 state ....................... ....................... A1-34 A1.9 Predeclared extension register names in AArch32 state ...................................... A1-35 A1.10 Program Counter in AArch32 state ................................... ................................... A1-36 A1.11 The Q flag in AArch32 state .................................................................................. A1-37 A1.12 Application Program Status Register .................................................................... A1-38 A1.13 Current Program Status Register in AArch32 state .............................................. A1-39 A1.14 Saved Program Status Registers in AArch32 state .............................................. A1-40 A1.15 A32 and T32 instruction set overview ................................. ................................. A1-41 100076_0200_00_en Copyright © 2018, 2019 Arm Limited or its affiliates. All rights 5 reserved. Non-Confidential A1.16 Access to the inline barrel shifter in AArch32 state ....................... ....................... A1-42 Part B Advanced SIMD and Floating-point Programming Chapter B1 Advanced SIMD Programming B1.1 Architecture support for Advanced SIMD .............................................................. B1-46 B1.2 Extension register bank mapping for Advanced SIMD in AArch32 state .............. B1-47 B1.3 Views of the Advanced SIMD register bank in AArch32 state .............................. B1-49 B1.4 Load values to Advanced SIMD registers .............................. .............................. B1-50 B1.5 Conditional execution of A32/T32 Advanced SIMD instructions ............. ............. B1-51 B1.6 Floating-point exceptions for Advanced SIMD in A32/T32 instructions ................ B1-52 B1.7 Advanced SIMD data types in A32/T32 instructions ...................... ...................... B1-53 B1.8 Polynomial arithmetic over {0,1} ............................................................................ B1-54 B1.9 Advanced SIMD vectors ........................................................................................ B1-55 B1.10 Normal, long, wide, and narrow Advanced SIMD instructions .............................. B1-56 B1.11 Saturating Advanced SIMD instructions ................................................................ B1-57 B1.12 Advanced SIMD scalars ........................................................................................ B1-58 B1.13 Extended notation extension for Advanced SIMD ........................ ........................ B1-59 B1.14 Advanced SIMD system registers in AArch32 state .............................................. B1-60 B1.15 Flush-to-zero mode in Advanced SIMD ................................................................ B1-61 B1.16 When to use flush-to-zero mode in Advanced SIMD ............................................ B1-62 B1.17 The effects of using flush-to-zero mode in Advanced SIMD ................ ................ B1-63 B1.18 Advanced SIMD operations not affected by flush-to-zero mode ............. ............. B1-64 Chapter B2 Floating-point Programming B2.1 Architecture support for floating-point ................................. ................................. B2-66 B2.2 Extension register bank mapping for floating-point in AArch32 state .................... B2-67 B2.3 Views of the floating-point extension register bank in AArch32 state ......... ......... B2-69 B2.4 Load values to floating-point registers .................................................................. B2-70 B2.5 Conditional execution of A32/T32 floating-point instructions ................................ B2-71 B2.6 Floating-point exceptions
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