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Family Tree Whirlwind I Whirlwind II AN/FSQ-7 MTC TX-1 (Not

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Family Tree Whirlwind I Whirlwind II AN/FSQ-7 MTC TX-1 (Not Family tree Whirlwind I PDP-1 (PDP-2,3) Whirlwind II MTC PDP-4 PDP-7,9,15 AN/FSQ-7 PDP-5 PDP-8,12 TX-1 (not built) PDP-6 PDP-10 TX-0 PDP-11 TX-2 PDP-1 Whirlwind I block diagram PERIPHERALS PRPC SS 11 16 11 STORAGE 16 IOR 16 STORAGE ELEMENT CS 5 AR 16 SC 5 CONTROL AC 16 BR 16 CONTROL ELEMENT ARITHMETIC ELEMENT Whirlwind I summary INSTRUCTION AC BR ARSAM C(x) 00000 SI SELECT IO UNIT 00001 ILLEGAL 00010 BI BLOCK IN x + n x first word 00011 RD READ IOR IOR 00100 BO BLOCK OUT x + n x 00101 RC RECORD 00110 SD SUM OF DIGITS AC ∨ C(x) C(x) 0 00111 CF CHANGE FIELDS 01000 TS TRANSFER TO STORAGE AC 01001 TD TRANSFER DIGITS C(x)0-4,AC5-15 01010 TA TRANSFER ADDRESS C(x)0-4,AR5-15 01011 CK CHECK 01100 AB ADD BR BR + C(x) C(x) 0 BR + C(x) 01101 EX EXCHANGE C(x) C(x) AC 01110 CP CONDITIONAL SP y+1 01111 SP SUBPROGRAM y+1 10000 CA CLEAR, ADD C(x) + SAM 0 C(x) 0 10001 CS CLEAR, SUBTRACT –C(x) + SAM 0 C(x) 0 10010 AD ADD AC + C(x) C(x) 0 10011 SU SUBTRACT AC – C(x) C(x) 0 10100 CM CLEAR, ADD MAG. |C(x)|+SAM 0 |C(x)| 0 10101 SA SPECIAL ADD AC + C(x) C(x) ±1 or 0 10110 AO ADD ONE C(x) + 1 C(x) 0 C(x) + 1 10111 DM DIFFERENCE OF MAG. |AC|–|C(x)| AC |C(x)| 0 11000 MR MULTIPLY, ROUND (AC × C(x))LT + r 0 |C(x)| 0 11001 MH MULTIPLY, HOLD AC × C(x) ← |C(x)| 0 11010 DV DIVIDE ±0 AC/C(x) |C(x)| 0 11011 0 SLR SHIFT LEFT, ROUND (AC:BR « n)LT + r 0 0 11011 1 SLH SHIFT LEFT, HOLD AC:BR « n ← 0 11100 0 SRR SHIFT RIGHT, ROUND (AC:BR » n)LT + r 0 0 11100 1 SRH SHIFT RIGHT, HOLD AC:BR » n ← 0 11101 SF SCALE FACTOR AC:BR « n ← n 0 n 11110 0 CLC CYCLE LEFT, CLEAR (AC:BR rot n)LT 0 11110 1 CLH CYCLE LEFT, HOLD AC:BR rot n ← 11111 MD MULTIPLY DIGITS AC ∧ C(x) –(final AC) MTC block diagram CONTROL CORE CS PC LRn CA AR AC BR 5 11 11 11 MEMORY 16 16 16 16 LR2 SC 5 MTC proposals March 1952 July 1952 M-1428 M-1562 4 operations 0 1 2 3 4 5 ts su 1: 10 digits 1: Clear 1: In cp AC io 0: 16 digits 1: Storage 1: Comp. AR 1: Display 8 operations 0: Out 0: tc cr 0: 0: Add td cp 1: cp 1: Alarm ad mr 1: Sub- su io program 0: sp 0: 0: No Storage 16 operations 1: PETR 1: punch 1: sr 1: Shift ts tc 0: td dc 0: 0: 0: cr 0: ad su cr sr sp cp mr lm qr qr* qd qh Final tc: ts, clear AC dc: td, clear AC 32 separate orders, similar to Whirlwind I TX-0 block diagram PC 16 MAR 16 CORE MEM IR 2 MBR 18 18 CONTROL PERIPHERALS AC 18 LR 18 TAC 18 TBR 18 2 3 9 10 11 12 13 14 15 16 17 TX-0 7 1958 1 1 8 4k memory CLL CLR 2 3 4 000 001 010 011 100 101 110 111 1 0 0 1 PEN 1 00 STO 0 1 TAC 01 ADD 1 0 1 10 TRN COM AMB 2 1 1 11 OPR - See other tables TBR 0 1 1 0 6 7 8 MBL LMB 000 001 010 011 100 101 110 111 4 5 3 00 NOP 01 EX0 EX1 EX2 EX3 EX4 EX5 EX6 EX7 1 0 1 10 R1L DIS R3L PNT P6H P7H SHR PAD 4 1 1 11 HLT CYR 1 7 CRY 2 3 9 10 11 12 13 14 15 16 17 TX-0 7 July 1960 1 1 8 8k memory CLL CLR 2 3 4 000 001 010 011 100 101 110 111 1 0 0 1 PEN 1 00 STO SLR 0 1 TAC 01 ADD LLR 1 0 1 10 TRN TRA COM AMB 2 1 1 11 OPR - See other tables TBR 0 1 1 0 6 7 8 MBL LMB 0 0 1 1 000 001 010 011 100 101 110 111 3 4 5 ORL COM 00 NOP 0 1 1 1 ANL COM 01 EX0 EX1 EX2 EX3 EX4 EX5 EX6 EX7 1 0 1 10 R1L DIS R3L PNT P6H P7H SHR PAD 4 1 1 11 HLT CYR 1 7 CRY 2 3 9 10 11 12 13 14 15 16 17 1 7 TX-0 AMB June 1961 1 8 8k memory CLA 2 3 4 000 001 010 011 100 101 110 111 1 0 1 2 COM 00 STO SLR 01 1 ORB 01 ADD LLR 3 11 1 10 TRN TRA ANB 10 X 10 X 4 11 OPR - See other tables MBL LMB 01 0 1 6 7 8 SHR PAD 000 001 010 011 100 101 110 111 11 0 4 5 5 CYR 00 NOP TAC TBR PEN SEL RPF SPF 01 EX0 EX1 EX2 EX3 EX4 EX5 EX6 EX7 1 7 10 CPY R1L DIS R3L PRT TYP P6H P7H CRY 11 HLT CLL CLR 2 3 9 10 11 12 13 14 15 16 17 1 7 TX-0 AMB September 1965 1 8 8k memory CLA 2 3 4 000 001 010 011 100 101 110 111 X0 1 1 0 1 2 XMB COM 00 STO STX SXA ADO SLRSLX STZ 01 1 ORB 01 ADD ADX LDX AUX LLR LLX LDA LAX 3 11 1 10 TRN TZE TAX TIX TRA TRX TLV (TPL) ANB 10 X 10 X 4 11 OPR - See other tables MBL LMB 1 5 6 7 8 PAD 000 001 010 011 100 101 110 111 01 0 4 5 SHR 6 00 NOP TAC TBR PEN SEL RPF SPF 11 0 CYR 01 EX0 EX1 EX2 EX3 EX4 EX5 EX6 EX7 1 7 10 CPY R1L DIS R3L PRT TYP P6H P7H CRY X0 1 8 11 HLT CLL CLR MBX PDP-1 block diagram TA 12 PC 12 MA 12 MEM IR 5 MB 18 18 CONTROL PERIPHERALS AC 18 IO 18 TW 18 PDP-1 summary SKIP GROUP 1 1 010 SKP SPI SZOSMA SPA SZA SZS SZF 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 MAIN INSTRUCTIONS 650000 SKP reverse SKIP condition SKIP OP I Y 642000 SPI IO0 = 0: SKIP SKIP ON PLUS IO 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 641000 SZO OV = 0: SKIP SKIP ON ZERO OV 640400 SMA AC0 = 1: SKIP SKIP ON MINUS AC 00 640200 SPA AC0 = 0: SKIP SKIP ON PLUS AC 02 AND AC ← AC ∧ C(Y) AND 640100 SZA AC = +0: SKIP SKIP ON ZERO AC 04 IOR AC ← AC ∨ C(Y) INCLUSIVE OR 6400X0 SZS SWn = 0: SKIP SKIP ON ZERO SWITCH 06 XOR AC -← AC ⊻ C(Y) EXCLUSIVE OR 64000X SZF Fn = 0: SKIP SKIP ON ZERO FLAG 10 XCT execute C(Y) EXECUTE 12 JFD JUMP TO FIELD 14 16 CAL JDA 100 CALL SHIFT GROUP 17 JDA C(Y) ← AC. AC ← PC. PC ← Y+1 JUMP, DEPOSIT AC 20 LAC AC ← C(Y) LOAD AC 1 1 110 RSFTIOAC N 22 LIO IO ← C(Y) LOAD IO 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 24 DAC C(Y) ← AC DEPOSIT AC SFT: 0: rotate (R__). 1: shift (S__) 26 DAP C(Y) ← AC DEPOSIT ADDR. PART 6-17 IO:AC: 01: AC (_A_) 30 DIP C(Y) ← AC DEPOSIT INST. PART 0-5 10: IO (_I_) 32 DIO ← DEPOSIT IO C(Y) IO 11: AC:IO (_C_) 34 DZM ← DEPOSIT ZERO C(Y) 0 R: 0: left (__L). 1: right (__R) 36 N: steps (number of 1's) 40 ADD AC ← AC + C(Y) ADD 42 SUB AC ← AC - C(Y) SUBTRACT 44 IDX C(Y), AC ← C(Y)+1 INDEX OPERATE GROUP 46 ISP IDX. AC ≥ 0: SKIP INDEX, SKIP IF POSITIVE 50 SAD AC ≠ C(Y): SKIP SKIP IF DIFFERENT STF 1 1 111 CLI LAT CMA HLT CLA F 52 SAS AC = C(Y): SKIP SKIP IF SAME CLF 54 MUS MULTIPLY STEP 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 56 DIS DIVIDE STEP 764000 CLI IO ← 0 CLEAR IO 60 JMP PC ← Y JUMP 762000 LAT AC ← AC ∨ TW LOAD AC FROM TW 62 JSP AC ← PC. PC ← Y JUMP, SAVE PC 761000 CMA CMA ← ~CMA COMPLEMENT AC 64 SKP SKIP GROUP 760400 HLT HALT HALT 66 SFT SHIFT GROUP 760200 CLA AC ← 0 CLEAR AC 70 LAW AC ← Y/~Y LOAD AC WITH 760100 LAP AC ← AC ∨ PC LOAD AC FROM PC 72 IOT IO TRANSFER 76000X CLF Fn←0 CLEAR FLAG 74 76001X STF Fn ← 1 SET FLAG 76 OPR OPERATE PDP-4 block diagram AS 13 PC 13 MA 13 MEM IR 4 MB 18 18 CONTROL L 1 AC 18 ACS 18 PDP-4 summary OPERATE GROUP 1 1 011 CLA CLL rot2 SKP SNL SZA SMA HLT RAR RALOASCMLCMA MAIN INSTRUCTIONS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 750000 CLA AC ← 0 CLEAR AC OP I Y 744000 CLL L ← 0 CLEAR L 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 741000 SKP reverse SKIP condition SKIP 00 CAL JMS 20 CALL 740400 SNL L ≠ 0: SKIP OR SKIP ON NON-ZERO L 04 DAC C(Y) ← AC DEPOSIT AC 740200 SZA AC = 0: SKIP SKIP ON ZERO AC 10 JMS C(Y) ← PC.
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