DOCSLIB.ORG

Torrenza and the Pareto Distribution

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Torrenza and the Pareto Distribution CoEHT Symposium February 16, 2007 Douglas O’Flaherty The Heterogeneous Processing Imperative ≤ 1981 Single16-bit 486 Core x8 By the end of Spreadsheets,the decade,6 word-processing homogenous PERF. So 2 multi-core1990s becomes increasingly inadequate f tw 32-bit a Single r e AMD64 Core E-mail, GUI, PowerPoint,C web browsers om p l Dual- ex i Opteron ty Java, XML, web a services CoE HT Symposia n C d PERF. D ore 2000s i ve 64-bit rsi 3D, digital mediat Single Core y ER/PERF. POW 64-bit ogeneous HD, DRM HomMulti-CPU essing DIVERSITY 2010s The End of “One Size Fits All” Computing Platform Co-Proc HeterogeneousCPU+xPU Industry Landscape: The Insight Gap Accelerators Devices optimized to enhance the performance on a particular function “The Insight Gap” Data Driven X86 PerformanceComputing Time 3 CoE HT Symposia Torrenza and the Pareto Distribution • New features are introduced in niche markets y Some features will never reach broad market appeal, but will have stable niche markets over time y The sum of those niche market opportunities is itself a considerable market opportunity • Features with broad market appeal are quickly moved up the value chain y FPGA to custom logic on add-in board y Custom logic integrated into chipset y For very high value features, chipset logic moves into processor • Our goals for Torrenza y Enable new markets by changing system economics with a standard platform y Evaluate new features for their potential in the mass market % of Target Market Value Migration Mass New Features Enter Market in Niches Market Niche Markets ◄ General Features Specialized Features ► 4 CoE HT Symposia Early vs. Late Market Entry Managing Risk and Cost Business Risk Cost of Entry Perfect Timing Market Starting to Buy Capability Capability Value Starting to React Cost and Risk Mature Venture Capital Markets and Start-ups Live Here Market Maturity and Size • New capabilities carry inherent business risk • Managing risk is a business philosophy y Venture Capital accepts high risk for potentially high returns y Most mature enterprises only accept low risk, but end up paying top-dollar for what are essentially new divisions • Torrenza gives the industry an early assessment of emerging capabilities 5 CoE HT Symposia Torrenza Platform Challenges End-Customers Barriers to Application Performance y Heterogeneous computing & application software y Synchronization & Communication overhead OEM & Channel Barriers to Support y Proliferation of SKUs y Economic challenges to differentiate Innovators Barriers of Entry y Inflexibility of legacy platforms y Need innovation roadmap from concept to deployment 6 CoE HT Symposia Torrenza Platform Challenges End-Customers Enrich the IT industry with AMD64 Barriers to Application Performance y Heterogeneoustechnology ascomputing the & application software y SynchronizationOPEN, STANDARDS & Communication BASED overhead Innovation Platform for our OEMcustomers & Channel and end users. Barriers to Support y Proliferation of SKUs • Freedom of Choice y Economic challenges to differentiate • Longevity and Stability Innovators Barriers• Differentiated of Entry and Upgradeable y Inflexibility of legacy platforms y Need innovation roadmap from concept to deployment 7 CoE HT Symposia Acceleration Adoption Model C C o o CPU r r HTX AMD AMD e e Opteron™ Opteron™ Chipset Processor Processor NB PCI-E AMD Opteron™ Socket Extensible System Bus Highly Integrated Solution Packaging is an Economic Option 8 CoE HT Symposia Continuum of Solutions “Fusion" "Torrenza" Accelerator Accelerator C CPU P U HTX Accelerator AMD NB Processor PCI-E Chipset Silicon level Package level integration Accelerator integration PCIe Accelerator (MCM) Add-in Chipset Accelerator Accelerated Processors Opteron Socket Fusion – AMD’s code name for: Accelerated "Stream" Socket Processors (integrated acceleration) general compatible Torrenza – AMD’s code name for: purpose GPU accelerator slot or socket based acceleration Stream – Specific example of a GPGPU Slot or Socket Acceleration accelerator under Torrenza 9 CoE HT Symposia Torrenza Initiative Elements Innovation Socket Platform Support y Propagating Freedom y Standards platform of Choice through support for technology sharing Innovation Socket accelerators Silicon Platform Enablement Support Silicon Enablement AMD Technology AMD y An ecosystem of Technology y Enhancing the silicon development platform & protocols and support for accelerators 10 CoE HT Symposia Torrenza 2006 Timeline AMDOEM Announcements Torrenza AMD Innovation Fusion Socket IBM Servers Cray XMT Cray DARPA June 2006 CTM: AMDPhase Stream 3 Torrenza 2-way & 4-way CloseThreadstorm™ to ProcessorAdaptive Launch With HTX slots The MetalProcessors Supercomputing TokyoUni. Institu Researchte HyperTransport™“Roadrunner” OpenFPGASC06 Demos of TechnologyProgram Technology COE AMD Opteron™ 5 HTX Boards Sun x64Altera, Servers Sun, U. Mannheim Cornerstone Processor & 2 Socket Fillers Xtreme Data (HT & cHT) Sponsor Clearspeed™ IBM Cell™ Blades Embedded Design 11 CoE HT Symposia Advancing AMD’s Torrenza Initiative Network Enterprise Processing SOA Java Technologies XML SMP Content Storage Security Offload FPGA IPTV g in s g s n ce i o d Media r o Math Enablement P c s n a I/O r T VoIP IMS Telco 12 CoE HT Symposia Reconfigurable Computing Commercial Implementations Center of Excellence HT, cHT & HTX Reference Designs Research Program Platform & Programming Support 13 CoE HT Symposia This presentation is an exploration, not a roadmap of a committed plan. On Acceleration Protocols 14 CoE HT Symposia Offload Model: Asynchronous (Survey of current accelerators) y Majority of current base – E.g. GPU, Ethernet NIC, Appliances y Have developed worked out latency hiding mechanisms – Large on-card memory enables buffering for large block transfers – Highly managed buffer & context techniques (e.g., HW multithreading) y DMA is key function – Includes one or more system memory copies y Driver techniques to address issue in market e.g. Chimney y Explicitly coded Communication Channels – Using available IO functions 15 CoE HT Symposia Co-Processing Model: Synchronous (Survey of accelerators) Significant number of new entrants & evolving solutions – Computational Offload y HPC, image processing, analytics, algorithm in chip – Reliable delivery at wire speed y Messaging, Classification, Security, Virtualization y Applicability of accelerator is dependant upon problem size & intensity – Acceleration must overcome start-up time (transfer latency & synchronization) – More synchronous communication between system thread and device processing y Compute efficiency requires moving data more often – Accelerators are taking less time to process and need to increase concurrency – Larger, more complex context increases memory footprint – Overlapping transfers hides latency and increases accelerator throughput y More random access to system memory – Increasing number of cores, threads & virtual machines within system – Many problems are not regularly ordered y Latency hiding is most effective on large, or highly predictable, work units Goal for auto-generated offload requires support of smaller work-unit granularity Need improved communications channels 16 CoE HT Symposia Accelerator Communication/Synchronization Models • Traditional approaches for I/O acceleration have typically been based on Asynchronous implementations – I/O device performance DMA for both inbound and outbound data transfers – Notification from I/O to host is by interrupt – Notification from host to I/O is typically via kernel-mode driver y These approaches are appropriate for many I/O-related functions, but are too restrictive for computational acceleration – An efficient Synchronous mode of operation makes fine-grain offloading much easier and more effective – Host processor “baby-sits” accelerator, performing command/control and some computation – Polling is appropriate – the accelerator is doing most of the work, so overlap is a bonus, not a requirement –Latency, Overhead, and Concurrency are critical attributes of the interconnect 17 CoE HT Symposia Sync Latency: Orders of Magnitude Short Message Latency Type of Connection (microseconds) (CPU Cycles) IP over WAN ~100,000 240,000,000 IP over LAN ~1,000 2,400,000 Unix Pipes in SMP >10 24,000 (SUSE 9.1 on 2-socket Opteron) Unix Sockets in SMP ~20 (TCP) 48,000 (SUSE 9.1 on 2-socket Opteron) ~15 (UDP) 36,000 User-mode Sockets in SMP ~2.5 6000 (Scali) Simple lock-free shared memory 0.21 - 0.25 (Opteron 4 socket) 500 - 600 producer/consumer handoff 0.15 - 0.18 (Opteron 2 socket) 350 - 430 0.095 - 0.135 (Opteron 4s) 225 – 325 Cache-to-cache intervention 0.065 - 0.095 (Opteron 2s) 150 – 225 One-way HT probe latency <0.025 <60 (per hop) On-Chip core-to-core latency ~0.0025 ~6 18 CoE HT Symposia Sync Latency: Orders of Magnitude Short Message Latency Type of Connection (microseconds) (CPU Cycles) IP over WAN ~100,000 240,000,000 IP over LAN ~1,000 2,400,000 Unix Pipes in SMP >10 24,000 (SUSE 9.1 on 2-socket Opteron) Unix Sockets in SMP ~20 (TCP) 48,000 (SUSE 9.1 on 2-socket Opteron) ~15 (UDP) 36,000 User-mode Sockets in SMP ~2.5 6000 (Scali) Simple lock-free shared memory 0.21 - 0.25 (Opteron 4 socket) 500 - 600 producer/consumer handoff 0.15 - 0.18 (Opteron 2 socket) 350 - 430 100x slower than hardware! 0.095 - 0.135 (Opteron 4s) 225 – 325 Cache-to-cache intervention 0.065 - 0.095 (Opteron 2s) 150 – 225 One-way HT probe latency <0.025 <60 (per hop) On-Chip core-to-core latency ~0.0025 ~6 19 CoE HT Symposia Why are Current Architectures so SLOW? •
Load more

Recommended publications
  • Exploring Weak Scalability for FEM Calculations on a GPU-Enhanced Cluster
    Exploring weak scalability for FEM calculations on a GPU-enhanced cluster Dominik G¨oddeke a,∗,1, Robert Strzodka b,2, Jamaludin Mohd-Yusof c, Patrick McCormick c,3, Sven H.M. Buijssen a, Matthias Grajewski a and Stefan Turek a aInstitute of Applied Mathematics, University of Dortmund bStanford University, Max Planck Center cComputer, Computational and Statistical Sciences Division, Los Alamos National Laboratory Abstract The first part of this paper surveys co-processor approaches for commodity based clusters in general, not only with respect to raw performance, but also in view of their system integration and power consumption. We then extend previous work on a small GPU cluster by exploring the heterogeneous hardware approach for a large-scale system with up to 160 nodes. Starting with a conventional commodity based cluster we leverage the high bandwidth of graphics processing units (GPUs) to increase the overall system bandwidth that is the decisive performance factor in this scenario. Thus, even the addition of low-end, out of date GPUs leads to improvements in both performance- and power-related metrics. Key words: graphics processors, heterogeneous computing, parallel multigrid solvers, commodity based clusters, Finite Elements PACS: 02.70.-c (Computational Techniques (Mathematics)), 02.70.Dc (Finite Element Analysis), 07.05.Bx (Computer Hardware and Languages), 89.20.Ff (Computer Science and Technology) ∗ Corresponding author. Address: Vogelpothsweg 87, 44227 Dortmund, Germany. Email: [email protected], phone: (+49) 231 755-7218, fax: -5933 1 Supported by the German Science Foundation (DFG), project TU102/22-1 2 Supported by a Max Planck Center for Visual Computing and Communication fellowship 3 Partially supported by the U.S.
    [Show full text]
  • Lewis University Dr. James Girard Summer Undergraduate Research Program 2021 Faculty Mentor - Project Application
    Lewis University Dr. James Girard Summer Undergraduate Research Program 2021 Faculty Mentor - Project Application Exploring the Use of High-level Parallel Abstractions and Parallel Computing for Functional and Gate-Level Simulation Acceleration Dr. Lucien Ngalamou Department of Engineering, Computing and Mathematical Sciences Abstract System-on-Chip (SoC) complexity growth has multiplied non-stop, and time-to- market pressure has driven demand for innovation in simulation performance. Logic simulation is the primary method to verify the correctness of such systems. Logic simulation is used heavily to verify the functional correctness of a design for a broad range of abstraction levels. In mainstream industry verification methodologies, typical setups coordinate the validation e↵ort of a complex digital system by distributing logic simulation tasks among vast server farms for months at a time. Yet, the performance of logic simulation is not sufficient to satisfy the demand, leading to incomplete validation processes, escaped functional bugs, and continuous pressure on the EDA1 industry to develop faster simulation solutions. In this research, we will explore a solution that uses high-level parallel abstractions and parallel computing to boost the performance of logic simulation. 1Electronic Design Automation 1 1 Project Description 1.1 Introduction and Background SoC complexity is increasing rapidly, driven by demands in the mobile market, and in- creasingly by the fast-growth of assisted- and autonomous-driving applications. SoC teams utilize many verification technologies to address their complexity and time-to-market chal- lenges; however, logic simulation continues to be the foundation for all verification flows, and continues to account for more than 90% [10] of all verification workloads.
    [Show full text]
  • Virtualization: Comparision of Windows and Linux
    VIRTUALIZATION: COMPARISION OF WINDOWS AND LINUX Ms. Pooja Sharma Lecturer (I.T) PCE, Jaipur Email:[email protected] Charnaksh Jain IV yr (I.T) PCE, Jaipur [email protected] Abstract Full-Virtualization, Para-Virtualization, hyper- visior(Hyper-V), Guest Operating System, Host Virtualization as a concept is not new; computational Operating System. environment virtualization has been around since the first mainframe systems. But recently, the term 1. Introduction "virtualization" has become ubiquitous, representing any type of process obfuscation where a process is Virtualization provides a set of tools for increasing somehow removed from its physical operating flexibility and lowering costs, things that are environment. Because of this ambiguity, important in every enterprise and Information virtualization can almost be applied to any and all Technology organization. Virtualization solutions are parts of an IT infrastructure. For example, mobile becoming increasingly available and rich in features. device emulators are a form of virtualization because the hardware platform normally required to run the Since virtualization can provide significant benefits mobile operating system has been emulated, to your organization in multiple areas, you should be removing the OS binding from the hardware it was establishing pilots, developing expertise and putting written for. But this is just one example of one type virtualization technology to work now. of virtualization; there are many definitions of the In essence, virtualization increases flexibility by term "virtualization" floating around in the current decoupling an operating system and the services and lexicon, and all (or at least most) of them are correct, applications supported by that system from a specific which can be quite confusing.
    [Show full text]
  • A Survey of Reconfigurable Processors
    Hindawi Publishing Corporation VLSI Design Volume 2013, Article ID 683615, 18 pages http://dx.doi.org/10.1155/2013/683615 Review Article Ingredients of Adaptability: A Survey of Reconfigurable Processors Anupam Chattopadhyay MPSoC Architectures, UMIC Research Centre, RWTH Aachen University, Mies-van-der-Rohe Strasse 15, 52074 Aachen, Germany Correspondence should be addressed to Anupam Chattopadhyay; [email protected] Received 18 December 2012; Revised 14 May 2013; Accepted 1 June 2013 Academic Editor: Yann Thoma Copyright © 2013 Anupam Chattopadhyay. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. For a design to survive unforeseen physical effects like aging, temperature variation, and/or emergence of new application standards, adaptability needs to be supported. Adaptability, in its complete strength, is present in reconfigurable processors, which makes it an important IP in modern System-on-Chips (SoCs). Reconfigurable processors have risen to prominence as a dominant computing platform across embedded, general-purpose, and high-performance application domains during the last decade. Significant advances have been made in many areas such as, identifying the advantages of reconfigurable platforms, their modeling, implementation flow and finally towards early commercial acceptance. This paper reviews these progresses from various perspectives with particular emphasis on fundamental challenges and their solutions. Empowered with the analysis of past, the future research roadmap is proposed. 1. Introduction Circuits (ASICs) in terms of flexibility and performance. Since this work, notable research has been done in accel- The changing technology landscape and fast evolution of erator design (application-specific processors), multicore application standards make it imperative for a design to homogeneous and heterogeneous System-on-Chip (SoC) be adaptable.
    [Show full text]
  • Introduction Hardware Acceleration Philosophy Popular Accelerators In
    Special Purpose Accelerators Special Purpose Accelerators Introduction Recap: General purpose processors excel at various jobs, but are no Theme: Towards Reconfigurable High-Performance Computing mathftch for acce lera tors w hen dea ling w ith spec ilidtialized tas ks Lecture 4 Objectives: Platforms II: Special Purpose Accelerators Define the role and purpose of modern accelerators Provide information about General Purpose GPU computing Andrzej Nowak Contents: CERN openlab (Geneva, Switzerland) Hardware accelerators GPUs and general purpose computing on GPUs Related hardware and software technologies Inverted CERN School of Computing, 3-5 March 2008 1 iCSC2008, Andrzej Nowak, CERN openlab 2 iCSC2008, Andrzej Nowak, CERN openlab Special Purpose Accelerators Special Purpose Accelerators Hardware acceleration philosophy Popular accelerators in general Floating point units Old CPUs were really slow Embedded CPUs often don’t have a hardware FPU 1980’s PCs – the FPU was an optional add on, separate sockets for the 8087 coprocessor Video and image processing MPEG decoders DV decoders HD decoders Digital signal processing (including audio) Sound Blaster Live and friends 3 iCSC2008, Andrzej Nowak, CERN openlab 4 iCSC2008, Andrzej Nowak, CERN openlab Towards Reconfigurable High-Performance Computing Lecture 4 iCSC 2008 3-5 March 2008, CERN Special Purpose Accelerators 1 Special Purpose Accelerators Special Purpose Accelerators Mainstream accelerators today Integrated FPUs Realtime graphics GiGaming car ds Gaming physics
    [Show full text]
  • What Every Programmer Should Know About Memory
    What Every Programmer Should Know About Memory Ulrich Drepper Red Hat, Inc. [email protected] November 21, 2007 Abstract As CPU cores become both faster and more numerous, the limiting factor for most programs is now, and will be for some time, memory access. Hardware designers have come up with ever more sophisticated memory handling and acceleration techniques–such as CPU caches–but these cannot work optimally without some help from the programmer. Unfortunately, neither the structure nor the cost of using the memory subsystem of a computer or the caches on CPUs is well understood by most programmers. This paper explains the structure of memory subsys- tems in use on modern commodity hardware, illustrating why CPU caches were developed, how they work, and what programs should do to achieve optimal performance by utilizing them. 1 Introduction day these changes mainly come in the following forms: In the early days computers were much simpler. The var- • RAM hardware design (speed and parallelism). ious components of a system, such as the CPU, memory, mass storage, and network interfaces, were developed to- • Memory controller designs. gether and, as a result, were quite balanced in their per- • CPU caches. formance. For example, the memory and network inter- faces were not (much) faster than the CPU at providing • Direct memory access (DMA) for devices. data. This situation changed once the basic structure of com- For the most part, this document will deal with CPU puters stabilized and hardware developers concentrated caches and some effects of memory controller design. on optimizing individual subsystems. Suddenly the per- In the process of exploring these topics, we will explore formance of some components of the computer fell sig- DMA and bring it into the larger picture.
    [Show full text]
  • The Amd Opteron Northbridge Architecture
    ..................................................................................................................................................................................................................................................... THE AMD OPTERON NORTHBRIDGE ARCHITECTURE ..................................................................................................................................................................................................................................................... TO INCREASE PERFORMANCE WHILE OPERATING WITHIN A FIXED POWER BUDGET, THE AMD OPTERON PROCESSOR INTEGRATES MULTIPLE X86-64 CORES WITH A ROUTER AND MEMORY CONTROLLER.AMD’S EXPERIENCE WITH BUILDING A WIDE VARIETY OF SYSTEM TOPOLOGIES USING OPTERON’S HYPERTRANSPORT-BASED PROCESSOR INTERFACE HAS PROVIDED USEFUL LESSONS THAT EXPOSE THE CHALLENGES TO BE ADDRESSED WHEN DESIGNING FUTURE SYSTEM INTERCONNECT, MEMORY HIERARCHY, AND I/O TO SCALE WITH BOTH THE NUMBER OF CORES AND SOCKETS IN FUTURE X86-64 CMP ARCHITECTURES. ...... In 2005, Advanced Micro Devices significant throughput improvements in introduced the industry’s first native 64-bit future products while operating within x86 chip multiprocessor (CMP) architec- a fixed power budget. AMD has also ture combining two independent processor launched an initiative to provide industry cores on a single silicon die. The dual-core access to the Direct Connect architecture. Opteron chip featuring AMD’s Direct The ‘‘Torrenza Initiative’’ sidebar sum- Connect architecture provided
    [Show full text]
  • FPGA-Acceleration on COTS X86 Platforms University of Mannheim, 16 Feb 2007
    FPGA-Acceleration on COTS x86 Platforms University of Mannheim, 16 Feb 2007 XtremeData, Inc.: Confidential Slide 1 Slide 1: XtremeData Inc.: Confidential Information TodayToday’’’’ss Agenda XtremeData Corporate & Team background Why FPGAs in COTS x86? Issues and XDI Solution FPGA acceleration markets FPGAs in HPC Summary XtremeData, Inc.: Confidential Slide 2 Slide 2: XtremeData Inc.: Confidential Information XtremeDataXtremeData:: Corporate HistoryHistory………… 2004 Incorporated 2003, Seed funds raised. Jan Market research & POC completed: target markets identified. Apr SeriesA raised and development started with two teams: Jul hardware in Chicago and software in Bangalore, India. Oct System architecture defined: commodity hardware platform, Jan accelerator and database engine. Apr Jul FPGA Module offered as a stand-alone product, press releases; 2006 2005 strategic partnerships made, shipments started… Oct Jan Apr SeriesB fund raise closing Jan 2007 for Go-To-Market financing 2007 XtremeData, Inc.: Confidential Slide 3 Slide 3: XtremeData Inc.: Confidential Information Team Background Ravi Chandran , CEO BE Electronics, India, MS EE, University of Texas, Arlington, MBA, Kellogg School, Northwestern University, IL President, Binary Machines, Inc., Schaumburg, IL COO, VP of Engineering., Bio-Imaging Research, Inc., Lincolnshire, IL (www.bio-imaging.com) 20+ years of product development & design services in medical & industrial (NDT) imaging markets. 20+ years experience with Toshiba Medical Systems – 20% of worldwide CT scanner installed
    [Show full text]
  • Embedded Computing Design Resource Guide
    RSC# @ www.embedded-computing.com/rsc RSC# @ www.embedded-computing.com/rsc www.embedded-computing.com VOLUME 4 • NUMBER 6 A U G U S T 2 0 0 6 COLUMNS RESOURCE GUIDE 7 Editor’s Foreword Federation of Associations 27 Middleware: The last roadblock to distributed By Jerry Gipper systems development By Dr. Stan Schneider, RTI 8 Embedded Perspective Ab fabless deals 29 BIOS, firmware, middleware By Don Dingee 33 FPGAs, reconfigurable computing 10 Embedded Technology in Europe Embedded devices for those with disabilities By Hermann Strass 52 High-performance computing 14 Eclipse Perspective and News ALF and 10 questions every QA team should ask 61 Why automate testing? By Tracy Ragan By Kingston Duffie, Fanfare 63 Integrated development environment FEATURES 67 Intellectual Property cores SPECIAL: Custom solutions and short design cycles 17 Customization for the masses 70 Mezzanine cards By Jerry Gipper PCI Express: Software/Firmware 84 Microprocessors, microcontrollers 23 Advanced functional verification and debug of PCI Express-based designs By Chris Browy, Avery Design Systems 89 Improving code migration and reuse By Robert Day, LynuxWorks DEPARTMENTS 94 Operating systems – embedded 30, 138 Editor’s Choice Products 102 Packaging By Jerry Gipper 105 Techniques to shrink embedded system E-CASTS design cycles RapidIO System Architecture: What Designers Need to Know By Rodger H. Hosking, Pentek August 24, 2 p.m. EST 108 Single board computers and blades www.opensystems-publishing.com/ecast OpenSystems 137 Storage solutions E-LETTER Publishing™ August: www.embedded-computing.com/eletter 143 It’s all just plumbing, isn’t it? Mobile phone security – in your face OpenSystems By Victor Menasce, AMCC By Seiji Inoue, Oki Electric Publishing™ 148 Switch network fabrics 153 System-on-Chip (SoC) Published by: OpenSystems OpenSystems 157 Using assertions to track functional coverage Publishing™Publishing™ By Kelly D.
    [Show full text]
  • REPORT the World's Best Process Company
    GILDER August 2006 / Vol. XI No. 8 TECHNOLOGY The World’s Best REPORT Process Company scending into life-after-television with its superior liquid crystal displays (LCDs), exotic green lasers, last-mile fiber webs and cable A triplays is Corning (GLW). With virtually 100 percent of the world still trapped in a copper cage, with growing demand for movie-and-game- ready mobile displays, and with high-definition video and flat-panel televi- sions just beginning long, global market runs, Corning’s future glitters like Steuben glass. For Corning, LCD Driven by displays that range from cell phones to notebook computers and desk- top monitors to televisions, global demand for LCD glass is expected to swell from glass could well 800 million square feet last year to 1,400 million square feet in 2007, with Corning hoping to outgrow the total market. Most notable is the anticipated ascent of LCD repeat the 30-plus television from 5 percent in 2004 and 11 percent in 2005 to 20 percent this year and 30 percent next with average screen size reaching 27 inches. year run of cathode At which point we’ll have only just begun. ray tubes. If you (CONTINUED ON PAGE 3) don’t own Corning, FEATURED COMPANY: Broadwing (BWNG) Broad Wings now is the time If you watched Tiger Woods’s emotional win at the British Open on ABC, you were watching con- tent transported on Broadwing’s (BWNG) media network. Ditto for the World Cup in high definition on to board the great ESPN or ABC. The carrier is also capturing major league baseball in most venues, transporting game content from stadiums without compression so that the production facility sees it as it came out of glass boat.
    [Show full text]
  • Corporate Overview
    AMD CPU Roadmap Justin Boggs Sr. Developer Relations Engineer Sunnyvale, CA, USA July 2007 Table of Contents AMD-At-a-Glance Roadmaps and Technologies 2 AMD At-a-Glance The New AMD: Capabilities Server Workstation Desktop Game Notebook DTV Handheld Segments consoles Geography Greater Latin Europe North Korea Japan Strengths China America America Customers/ Distribution PC OEM Retail Digital ODM Consumer Partners Handheld Media Microprocessors Customer Best-in- Chipset Graphics & Media Products Focus Class Products Processors 64-bit Multi- Hyper- Tech-Centric CrossFire Avivo Low H.264 Tech Core Transport Culture Power MFG Fabs and Process Technology Foundry Partnerships Blending world-class knowledge, cultures and people 4 The New AMD: Capabilities 5 A New Level of Choice: Customer-Centric, Open PC Platforms Commercial Gaming & Media Mobile Devices Emerging Client Computing Markets • Stable image • Best-in-class • Optimized and • Development for the Windows® scalable of integrated enterprise Media Center multimedia CPU-GPU Edition processing •Best platform platform solutions for • Accelerated support for experience better time-to- new business Windows market for and Vista™ OEMs deployment models • Longer battery life with no compromise in performance 6 The Next Major x86 Inflection Point 1981 1990’s 2000’s 2010’s Legacy Processing Era Single Core CPUs/GPUs Traditionally Optimized Platforms Multi-Core CPUs/GPUs Accelerated Processing Era Platform Level Silicon Level The Era of Accelerated Computing is coming, and AMD is again leading the
    [Show full text]
  • Introducing AMD Phenom™ Processors
    AMD CPU Roadmap Justin Boggs Sr. Developer Relations Engineer Sunnyvale, CA, USA July 2007 The New AMD: Capabilities Server Workstation Desktop Game Notebook DTV Handheld Segments consoles Geography Greater Latin Europe North Korea Japan Strengths China America America Customers/ Distribution PC OEM Retail Digital ODM Consumer Partners Handheld Media Microprocessors Customer Best-in- Chipset Graphics & Media Products Focus Class Products Processors 64-bit Multi- Hyper- Tech-Centric CrossFire Avivo Low H.264 Tech Core Transport Culture Power MFG Fabs and Process Technology Foundry Partnerships Blending world-class knowledge, cultures and people 4 The Next Major x86 Inflection Point 1981 1990’s 2000’s 2010’s Legacy Processing Era Single Core CPUs/GPUs Traditionally Optimized Platforms Multi-Core CPUs/GPUs Accelerated Processing Era Platform Level Silicon Level The Era of Accelerated Computing is coming, and AMD is again leading the way 7 Continuum of Solutions Accelerated Computing “Fusion" "Torrenza" Accelerator Accelerator C CPU P U HTX Accelerator AMD NB Processor PCI-E Chipset Silicon level Package level integration Accelerator integration PCIe Accelerator (MCM) Add-in Chipset Accelerator Accelerated Processors Opteron Socket Fusion – AMD’s code name for: Accelerated "Stream" Socket Processors (integrated acceleration) general compatible Torrenza – AMD’s code name for: purpose GPU accelerator slot or socket based acceleration Stream – Specific example of a GPGPU Slot or Socket Acceleration accelerator under Torrenza 8 First AMD Accelerated
    [Show full text]