DOCSLIB.ORG

Introducing AMD Phenom™ Processors

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text

Load more

AMD CPU Roadmap Justin Boggs Sr. Developer Relations Engineer Sunnyvale, CA, USA July 2007 The New AMD: Capabilities Server Workstation Desktop Game Notebook DTV Handheld Segments consoles Geography Greater Latin Europe North Korea Japan Strengths China America America Customers/ Distribution PC OEM Retail Digital ODM Consumer Partners Handheld Media Microprocessors Customer Best-in- Chipset Graphics & Media Products Focus Class Products Processors 64-bit Multi- Hyper- Tech-Centric CrossFire Avivo Low H.264 Tech Core Transport Culture Power MFG Fabs and Process Technology Foundry Partnerships Blending world-class knowledge, cultures and people 4 The Next Major x86 Inflection Point 1981 1990’s 2000’s 2010’s Legacy Processing Era Single Core CPUs/GPUs Traditionally Optimized Platforms Multi-Core CPUs/GPUs Accelerated Processing Era Platform Level Silicon Level The Era of Accelerated Computing is coming, and AMD is again leading the way 7 Continuum of Solutions Accelerated Computing “Fusion" "Torrenza" Accelerator Accelerator C CPU P U HTX Accelerator AMD NB Processor PCI-E Chipset Silicon level Package level integration Accelerator integration PCIe Accelerator (MCM) Add-in Chipset Accelerator Accelerated Processors Opteron Socket Fusion – AMD’s code name for: Accelerated "Stream" Socket Processors (integrated acceleration) general compatible Torrenza – AMD’s code name for: purpose GPU accelerator slot or socket based acceleration Stream – Specific example of a GPGPU Slot or Socket Acceleration accelerator under Torrenza 8 First AMD Accelerated Processor Combining CPU and GPU Create the optimal computing experience for an increasingly mobile, graphics- and Fusion media-centric world Vision Deliver step-function improvements in microprocessor performance-per-watt-per- dollar over today’s CPU-only architectures 9 A New Level of Innovation Fab 36 Fab 38 Build/Own • High value capture in mfg • Process Foundry innovation high •Design •Design innovation high innovation high Risk • Process innovation New York* moderate Reward * Potential AMD Fab facility 10 Manufacturing: Continuing to Set the Standard - AMD Dresden Fab 36 Fab 30 / Fab 38 y 300mm microprocessor Fab y 200mm microprocessor Fab with y Output continues to increase 300mm transition to Fab38 started in 1H07 y 65nm volume production underway y New “Bump and Test” facility y Reached full 65nm conversion in completed Q107 mid-2007 y Ramped 65nm at mature yields with extremely low defect densities y First 65nm production wafers left Fab36 in October 2006 11 Quad-Core AMD Opteron™ Advantage More than just four cores y Significant CPU Core Enhancements y Significant Cache Enhancements World-class performance y Native Quad-Core – Faster data sharing between cores y Enhanced AMD-V™ – Nested paging acceleration for virtual environments Reducing total cost of ownership y Performance/Watt leadership – Consistent 95W thermal design point – Low power 68W solutions y Drop-in upgrade – Socket F compatibility – BIOS upgrade – Leverage existing platform infrastructure y Common Core Architecture – One core technology top-to-bottom – Top-to-bottom platform feature consistency 13 AMD Desktop Platform Roadmap 2006 2007 2008 Processor Dual Core, Quad Core Dual Core HT 1.0/2.0 DDR2/DDR3 Shared L3 Cache HT 3.0 Socket AM2/AM3 Dual Core, Single Core Quad Core Dual Single Core HT 1.0/2.0 L2 Cache, HT 3.0 Core Single Core Platform 125W/89W/76W/65W/62W/45W DDR2 Memory Technology DDR2/DDR23 HyperTransport™ Technology (HT) 1.0/2.0 HT 3.0 Chipsets CrossFireTM dual-graphics, HD audio CrossFire dual-graphics, HT 3.0 PCIe Gen 2 DirectX10 integrated graphics DirectX9 integrated graphics, HD audio PCIe Gen 2, HT 3.0 14 Introducing AMD Phenom™ Processors May 14, 2007, we announced our vision and strategy for true quad-core client technology with the unveiling of the AMD Phenom™ processor family Next-generation AMD Phenom processors allow users to… experience the Phenomenal Native, true multi-core capability for an experience that is Exquisitely powerful True dual to quad-core architecture in an elegant design for ultimate performance with extreme bandwidth and a hair-trigger response Intensely visual Immersive and media-rich compute experiences to help users realize new possibilities and find new inspiration Strikingly Efficient Intelligent use of energy and system resources – stable, reliable, virtualization-ready and energy astute Based on AMD’s next-generation processor architecture 15 AMD Desktop Products 2H’07 AMD Phenom™ FX processors AM2+ Package,Ultimate Shared Performance L3 Cache, 128-bit FPU True Quad-core AMD Phenom™ X4 and X2 processors AM2+ Package,Phenomenal Shared L3Experience Cache, 128-bit FPU True Quad- and Dual-core AMD Athlon™ X2 processors AM2 Package,Do More L2 In Cache, Less Time 64-bit FPU Dual-core AMD Sempron™ processors AM2 Package,Everyday L2 ComputingCache, 64-bit FPU Single-core 16 AMD Mobile Platform Roadmap 2006 2007 2008 Processor AMD TurionTM 64 X2 Mobile Technology, Dual-Core, 90nm125 “Hawk” “Griffin” Mobile AMD Sempron Processor 65nm 65nm Single-Core, 90nm Platform Hybrid Disk Drives Hybrid Graphics “Fusion” 802.11a/b/g 802.11a/b/g/Draft-n 802.11a/b/g/n WWAN Chipsets DX9 DX10 DVI HDMI DisplayPort UVD PCI-E Gen I PCI-E Gen II DDR-2 Memory Technology HyperTransport™ Technology 1.0 HT 3.0 “Kite” “Kite” Refresh “Puma” 17.
Recommended publications
  • GPTPU: Accelerating Applications Using Edge Tensor Processing Units Kuan-Chieh Hsu and Hung-Wei Tseng University of California, Riverside {Khsu037, Htseng}@Ucr.Edu

    GPTPU: Accelerating Applications Using Edge Tensor Processing Units Kuan-Chieh Hsu and Hung-Wei Tseng University of California, Riverside {Khsu037, Htseng}@Ucr.Edu

    GPTPU: Accelerating Applications using Edge Tensor Processing Units Kuan-Chieh Hsu and Hung-Wei Tseng University of California, Riverside {khsu037, htseng}@ucr.edu This paper is a pre-print of a paper in the 2021 SC, the Interna- Two decades ago, graphics processing units (GPUs) were just tional Conference for High Performance Computing, Networking, domain-specific accelerators used for shading and rendering. But Storage and Analysis. Please refer to the conference proceedings intensive research into high-performance algorithms, architectures, for the most complete version. systems, and compilers [3–12] and the availability of frameworks like CUDA [13] and OpenCL [14], have revolutionized GPUs and ABSTRACT transformed them into high-performance, general-purpose vector Neural network (NN) accelerators have been integrated into a wide- processors. We expect a similar revolution to take place with NN spectrum of computer systems to accommodate the rapidly growing accelerators—a revolution that will create general-purpose matrix demands for artificial intelligence (AI) and machine learning (ML) processors for a broader spectrum of applications. However, de- applications. NN accelerators share the idea of providing native mocratizing these NN accelerators for non-AI/ML workloads will hardware support for operations on multidimensional tensor data. require the system framework and the programmer to tackle the Therefore, NN accelerators are theoretically tensor processors that following issues: can improve system performance for any problem that uses ten- (1) The microarchitectures and instructions of NN accelerators sors as inputs/outputs. Unfortunately, commercially available NN are optimized for NN workloads, instead of general matrix/tensor accelerators only expose computation capabilities through AI/ML- algebra.
  • AMD's Llano Fusion

    AMD's Llano Fusion

    AMD’S “LLANO” FUSION APU Denis Foley, Maurice Steinman, Alex Branover, Greg Smaus, Antonio Asaro, Swamy Punyamurtula, Ljubisa Bajic Hot Chips 23, 19th August 2011 TODAY’S TOPICS . APU Architecture and floorplan . CPU Core Features . Graphics Features . Unified Video decoder Features . Display and I/O Capabilities . Power Gating . Turbo Core . Performance 2 | LLANO HOT CHIPS | August 19th, 2011 ARCHITECTURE AND FLOORPLAN A-SERIES ARCHITECTURE • Up to 4 Stars-32nm x86 Cores • 1MB L2 cache/core • Integrated Northbridge • 2 Chan of DDR3-1866 memory • 24 Lanes of PCIe® Gen2 • x4 UMI (Unified Media Interface) • x4 GPP (General Purpose Ports) • x16 Graphics expansion or display • 2 x4 Lanes dedicated display • 2 Head Display Controller • UVD (Unified Video Decoder) • 400 AMD Radeon™ Compute Units • GMC (Graphics Memory Controller) • FCL (Fusion Control Link) • RMB (AMD Radeon™ Memory Bus) • 227mm2, 32nm SOI • 1.45BN transistors 4 | LLANO HOT CHIPS | August 19th, 2011 INTERNAL BUS . Fusion Control Link (FCL) – 128b (each direction) path for IO access to memory – Variable clock based on throughput (LCLK) – GPU access to coherent memory space – CPU access to dedicated GPU framebuffer . AMD Radeon™ Memory Bus (RMB) – 256b (each direction) for each channel for GMC access to memory – Runs on Northbridge clock (NCLK) – Provides full bandwidth path for Graphics access to system memory – DRAM friendly stream of reads and write – Bypasses coherency mechanism 5 | LLANO HOT CHIPS | August 19th, 2011 Dual-channel DDR3 Unified Video DDR3 UVD Decoder NB CPU CPU Graphics SIMD Integrated Integrated GPU, Display Northbridge Array Controller I/O Controllers L2 Display L2 I/OMultimedia Controllers L2 PCI Express I/O - 24 lanes, optional 1 MB L2 cache L2 I/O per core digital display interfaces CPU CPU Digital display interfaces 4 Stars-32nm PCIe CPU cores PPL Display PCIe PCIe Display 6 | LLANO HOT CHIPS | August 19th, 2011 CPU, GPU, UVD AND IO FEATURES STARS-32nm CPU CORE FEATURES .
  • Amd Filed: February 24, 2009 (Period: December 27, 2008)

    Amd Filed: February 24, 2009 (Period: December 27, 2008)

    FORM 10-K ADVANCED MICRO DEVICES INC - amd Filed: February 24, 2009 (period: December 27, 2008) Annual report which provides a comprehensive overview of the company for the past year Table of Contents 10-K - FORM 10-K PART I ITEM 1. 1 PART I ITEM 1. BUSINESS ITEM 1A. RISK FACTORS ITEM 1B. UNRESOLVED STAFF COMMENTS ITEM 2. PROPERTIES ITEM 3. LEGAL PROCEEDINGS ITEM 4. SUBMISSION OF MATTERS TO A VOTE OF SECURITY HOLDERS PART II ITEM 5. MARKET FOR REGISTRANT S COMMON EQUITY, RELATED STOCKHOLDER MATTERS AND ISSUER PURCHASES OF EQUITY SECURITIES ITEM 6. SELECTED FINANCIAL DATA ITEM 7. MANAGEMENT S DISCUSSION AND ANALYSIS OF FINANCIAL CONDITION AND RESULTS OF OPERATIONS ITEM 7A. QUANTITATIVE AND QUALITATIVE DISCLOSURE ABOUT MARKET RISK ITEM 8. FINANCIAL STATEMENTS AND SUPPLEMENTARY DATA ITEM 9. CHANGES IN AND DISAGREEMENTS WITH ACCOUNTANTS ON ACCOUNTING AND FINANCIAL DISCLOSURE ITEM 9A. CONTROLS AND PROCEDURES ITEM 9B. OTHER INFORMATION PART III ITEM 10. DIRECTORS, EXECUTIVE OFFICERS AND CORPORATE GOVERNANCE ITEM 11. EXECUTIVE COMPENSATION ITEM 12. SECURITY OWNERSHIP OF CERTAIN BENEFICIAL OWNERS AND MANAGEMENT AND RELATED STOCKHOLDER MATTERS ITEM 13. CERTAIN RELATIONSHIPS AND RELATED TRANSACTIONS AND DIRECTOR INDEPENDENCE ITEM 14. PRINCIPAL ACCOUNTANT FEES AND SERVICES PART IV ITEM 15. EXHIBITS, FINANCIAL STATEMENT SCHEDULES SIGNATURES EX-10.5(A) (OUTSIDE DIRECTOR EQUITY COMPENSATION POLICY) EX-10.19 (SEPARATION AGREEMENT AND GENERAL RELEASE) EX-21 (LIST OF AMD SUBSIDIARIES) EX-23.A (CONSENT OF ERNST YOUNG LLP - ADVANCED MICRO DEVICES) EX-23.B
  • Exploring Weak Scalability for FEM Calculations on a GPU-Enhanced Cluster

    Exploring Weak Scalability for FEM Calculations on a GPU-Enhanced Cluster

    Exploring weak scalability for FEM calculations on a GPU-enhanced cluster Dominik G¨oddeke a,∗,1, Robert Strzodka b,2, Jamaludin Mohd-Yusof c, Patrick McCormick c,3, Sven H.M. Buijssen a, Matthias Grajewski a and Stefan Turek a aInstitute of Applied Mathematics, University of Dortmund bStanford University, Max Planck Center cComputer, Computational and Statistical Sciences Division, Los Alamos National Laboratory Abstract The first part of this paper surveys co-processor approaches for commodity based clusters in general, not only with respect to raw performance, but also in view of their system integration and power consumption. We then extend previous work on a small GPU cluster by exploring the heterogeneous hardware approach for a large-scale system with up to 160 nodes. Starting with a conventional commodity based cluster we leverage the high bandwidth of graphics processing units (GPUs) to increase the overall system bandwidth that is the decisive performance factor in this scenario. Thus, even the addition of low-end, out of date GPUs leads to improvements in both performance- and power-related metrics. Key words: graphics processors, heterogeneous computing, parallel multigrid solvers, commodity based clusters, Finite Elements PACS: 02.70.-c (Computational Techniques (Mathematics)), 02.70.Dc (Finite Element Analysis), 07.05.Bx (Computer Hardware and Languages), 89.20.Ff (Computer Science and Technology) ∗ Corresponding author. Address: Vogelpothsweg 87, 44227 Dortmund, Germany. Email: [email protected], phone: (+49) 231 755-7218, fax: -5933 1 Supported by the German Science Foundation (DFG), project TU102/22-1 2 Supported by a Max Planck Center for Visual Computing and Communication fellowship 3 Partially supported by the U.S.
  • MX690E2 Radeon X1250 for Gaming Applications

    MX690E2 Radeon X1250 for Gaming Applications

    Industrial Motherboards AMD® RS690E Mini ITX with Integrated MX690E2 Radeon X1250 for Gaming Applications Audio 2 USB KB + Mouse Features 2 USB + LAN DVI + VGA COM1, COM2 • AMD® Socket AM2/AM2+ Supports Athlon 64, Athlon 64 x2, Sempron with 2000 MHz Hyper Transport • AMD® RS690E/SB600 Chipset Amplifi er ATX • Up to 4 GB DDR2 533/667/800 MHz SO-DIMM Sys- LVDS tem Memory PCIe x16 • ATI® Radeon Xpress1250 Graphic Engine RS690E • Dual Display: DVI-D, LVDS, VGA • 1 Gigabit LAN, HD Audio, Amplifi er Socket AM2 • 1 PCI, 1 Mini PCIe, Compact Flash SB600 • 2 SATA, 4 COM, 6 USB, 8-bit GPIO 2 SATA • TPM 1.2 Supported DIO • ATX Power COM3 COM4 • Mini ITX (6.7” x 6.7”) Mini PCIe CF (back) IDE 2 USB Front Panel 2 SO-DIMMs up to 4 GB Specifi cation ATX Power DDR2 SDRAM System Audio CPU Supports AMD® Socket AM2 support Athlon 64, Athlon 64 X AC’97 Codec Realtek® ALC888/ALC886 Audio Codec 2, Sempron with FSB 2000MHz Hyper Transport support with Audio Amplifer TPA3005D2 Stereo 5Watt per channel 200/400/600/800/1000 MHz Chipsets AMD® RS690E + SB600 Ethernet System Memory Two 200-pin SO-DIMM supports up to 4 GB DDR2 SDRAM LAN 1 Realtek® RTL8111B (1000Base-T Fast Ethernet) 400/533/667/800 MHz BIOS SPI Award 8 Mb BIOS Mechanical and Environment Expansion Interface 1 x PCI 1 x CF Power Requirement 42W (Max). ( 3.3V, 3.08A , 5V 0.817A, 5VSB 0.387A, 12V 2.18A) 1 x Mini PCIe Operating Temperature 0~60°C TPM TPM1.2 (Infi neon® TPM chip 9635 TT 1.2 on board) Operating Humidity 5%~90% relative humidity, non-condensing Watchdog Timer Reset: 1 sec.~255 min.
  • Quad-Core Catamount and R&D in Multi-Core Lightweight Kernels

    Quad-Core Catamount and R&D in Multi-Core Lightweight Kernels

    Quad-core Catamount and R&D in Multi-core Lightweight Kernels Salishan Conference on High-Speed Computing Gleneden Beach, Oregon April 21-24, 2008 Kevin Pedretti Senior Member of Technical Staff Scalable System Software, Dept. 1423 [email protected] SAND Number: 2008-1725A Sandia is a multiprogram laboratory operated by Sandia Corporation, a Lockheed Martin Company, for the United States Department of Energy's National Nuclear Security Administration under contract DE-AC04-94AL85000. Outline • Introduction • Quad-core Catamount LWK results • Open-source LWK • Research directions • Conclusion Going on Four Decades of UNIX Operating System = Collection of software and APIs Users care about environment, not implementation details LWK is about getting details right for scalability LWK Overview Basic Architecture Memory Management … … Policy n 1 n N tio tio Page 3 Page 3 Maker ca ca i l Libc.a Libc.a (PCT) pp ppli Page 2 Page 2 A libmpi.a A libmpi.a Page 1 Page 1 Policy Enforcer/HAL (QK) Page 0 Page 0 Privileged Hardware Physical Application Memory Virtual • POSIX-like environment Memory • Inverted resource management • Very low noise OS noise/jitter • Straight-forward network stack (e.g., no pinning) • Simplicity leads to reliability Nov 2007 Top500 Top 10 System Lightweight Kernel Compute Processors: Timeline 82% run a LWK 1990 – Sandia/UNM OS (SUNMOS), nCube-2 1991 – Linux 0.02 1993 – SUNMOS ported to Intel Paragon (1800 nodes) 1993 – SUNMOS experience used to design Puma First implementation of Portals communication architecture 1994
  • AMD Socket AM2 with AMD M690T Chipset Reference Schematic D D

    AMD Socket AM2 with AMD M690T Chipset Reference Schematic D D

    5 4 3 2 1 AMD Socket AM2 with AMD M690T Chipset Reference Schematic D D NOTES: Page Index Page Index ------- -------------------------------------------- ------- -------------------------------------------- 1) This schematic supports the AMD Socket AM2 CPU devices. 1 Cover Page 17 SB600 PCIe, PCI, LPC, Straps, & CPU Control 2) These are "Reference Schematics" and as such they have 2 Revision History 18 SB600 ACPI, GPIO, USB, and Audio Interfaces not been verified by an actual board build. 3 Block Diagram 19 SB SATA, IDE, SPI, and HW Management Interfaces 3) This reference schematic supports AMD M960T revision 4 Clock Structure 20 SB600 Power A12 or later. If A12 or later revision is not used, please 5 Power Configuration (1) 21 CRT Connector see your customer support representative for the 6 Power Configuration (2) 22 Broadcom Ethernet Controller necessary application notes for workarounds. 7 Reset & Voltage Sequence 23 Realtek Audio Codec C 4) This reference schematic supports SB600 revision 8 Socket AM2 HT Interface 24 LPC BIOS C A21 or later. If A21 or later revision is not used, please 9 Socket AM2 DDRII Memory Interface 25 USB Power and Connectors see your customer support representative for the 10 Socket AM2 Control & Debug 26 Power Main System, SB600 PCIe, & Other necessary application notes for workarounds. 11 Socket AM2 Power & Ground 27 Standby Power & Powergood 5) Unless otherwise specified, resistors have 5% tolerance. 12 SODIMM DDR2 28 Power for CPU Core 13 M690T HT, PCI, PCIe(R), PCIe Graphics Port 29 Power for DDR2 Memory and Interface 6) Unless otherwise specified, capacitors have 20% tolerance. 14 M690T PLL and Video Interface 30 Power M690T Core, PCIe Interface 15 M690T Power and Side Port Memory Interface 31 Unused Interfaces 16 Clock Generator IMPORTANT NOTICE: B 1.
  • Family 12H AMD Sempron Processor Product Data Sheet

    Family 12H AMD Sempron Processor Product Data Sheet

    Family 12h AMD Sempron™ Processor Product Data Sheet Publication # 50321 Revision: 3.00 Issue Date: December 2011 Advanced Micro Devices © 2011 Advanced Micro Devices, Inc. All rights reserved. The contents of this document are provided in connection with Advanced Micro Devices, Inc. (“AMD”) products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. The information contained herein may be of a preliminary or advance nature and is subject to change without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. Except as set forth in AMD’s Standard Terms and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. AMD’s products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of AMD’s product could create a situation where personal injury, death, or severe property or environmental damage may occur. AMD reserves the right to discontinue or make changes to its products at any time without notice. Trademarks AMD, the AMD Arrow logo, AMD PowerNow!, 3DNow!, AMD Virtualization, AMD-V, Sempron, and combinations thereof are trademarks of Advanced Micro Devices, Inc.
  • Cray XT and Cray XE Y Y System Overview

    Cray XT and Cray XE Y Y System Overview

    Crayyy XT and Cray XE System Overview Customer Documentation and Training Overview Topics • System Overview – Cabinets, Chassis, and Blades – Compute and Service Nodes – Components of a Node Opteron Processor SeaStar ASIC • Portals API Design Gemini ASIC • System Networks • Interconnection Topologies 10/18/2010 Cray Private 2 Cray XT System 10/18/2010 Cray Private 3 System Overview Y Z GigE X 10 GigE GigE SMW Fibre Channels RAID Subsystem Compute node Login node Network node Boot /Syslog/Database nodes 10/18/2010 Cray Private I/O and Metadata nodes 4 Cabinet – The cabinet contains three chassis, a blower for cooling, a power distribution unit (PDU), a control system (CRMS), and the compute and service blades (modules) – All components of the system are air cooled A blower in the bottom of the cabinet cools the blades within the cabinet • Other rack-mounted devices within the cabinet have their own internal fans for cooling – The PDU is located behind the blower in the back of the cabinet 10/18/2010 Cray Private 5 Liquid Cooled Cabinets Heat exchanger Heat exchanger (XT5-HE LC only) (LC cabinets only) 48Vdc flexible Cage 2 buses Cage 2 Cage 1 Cage 1 Cage VRMs Cage 0 Cage 0 backplane assembly Cage ID controller Interconnect 01234567 Heat exchanger network cable Cage inlet (LC cabinets only) connection air temp sensor Airflow Heat exchanger (slot 3 rail) conditioner 48Vdc shelf 3 (XT5-HE LC only) 48Vdc shelf 2 L1 controller 48Vdc shelf 1 Blower speed controller (VFD) Blooewer PDU line filter XDP temperature XDP interface & humidity sensor
  • ADVANCED MICRO DEVICES, INC. (Exact Name of Registrant As Specified in Its Charter)

    ADVANCED MICRO DEVICES, INC. (Exact Name of Registrant As Specified in Its Charter)

    UNITED STATES SECURITIES AND EXCHANGE COMMISSION Washington, D.C. 20549 FORM 8-K CURRENT REPORT Pursuant to Section 13 or 15(d) of the Securities Exchange Act of 1934 July 19, 2007 Date of Report (Date of earliest event reported) ADVANCED MICRO DEVICES, INC. (Exact name of registrant as specified in its charter) Delaware 001-07882 94-1692300 (State of Incorporation) (Commission File Number) (IRS Employer Identification Number) One AMD Place P.O. Box 3453 Sunnyvale, California 94088-3453 (Address of principal executive offices) (Zip Code) (408) 749-4000 (Registrant’s telephone number, including area code) N/A (Former Name or Former Address, if Changed Since Last Report) Check the appropriate box below if the Form 8-K filing is intended to simultaneously satisfy the filing obligation of the registrant under any of the following provisions: ¨ Written communications pursuant to Rule 425 under the Securities Act (17 CFR 230.425) ¨ Soliciting material pursuant to Rule 14a-12 under the Exchange Act (17 CFR 240.14a-12) ¨ Pre-commencement communications pursuant to Rule 14d-2(b) under the Exchange Act (17 CFR 240.14d-2(b)) ¨ Pre-commencement communications pursuant to Rule 13e-4(c) under the Exchange Act (17 CFR 240.13e-4(c)) Item 2.02 Results of Operations and Financial Condition. Item 7.01 Regulation FD Disclosure. The information in this Report, including the Exhibit 99.1 attached hereto, is furnished pursuant to Item 2.02 and Item 7.01 of this Form 8-K. Consequently, it is not deemed “filed” for the purposes of Section 18 of the Securities and Exchange Act of 1934, as amended, or otherwise subject to the liabilities of that section.
  • Communication Theory II

    Communication Theory II

    Microprocessor (COM 9323) Lecture 2: Review on Intel Family Ahmed Elnakib, PhD Assistant Professor, Mansoura University, Egypt Feb 17th, 2016 1 Text Book/References Textbook: 1. The Intel Microprocessors, Architecture, Programming and Interfacing, 8th edition, Barry B. Brey, Prentice Hall, 2009 2. Assembly Language for x86 processors, 6th edition, K. R. Irvine, Prentice Hall, 2011 References: 1. Computer Architecture: A Quantitative Approach, 5th edition, J. Hennessy, D. Patterson, Elsevier, 2012. 2. The 80x86 Family, Design, Programming and Interfacing, 3rd edition, Prentice Hall, 2002 3. The 80x86 IBM PC and Compatible Computers, Assembly Language, Design, and Interfacing, 4th edition, M.A. Mazidi and J.G. Mazidi, Prentice Hall, 2003 2 Lecture Objectives 1. Provide an overview of the various 80X86 and Pentium family members 2. Define the contents of the memory system in the personal computer 3. Convert between binary, decimal, and hexadecimal numbers 4. Differentiate and represent numeric and alphabetic information as integers, floating-point, BCD, and ASCII data 5. Understand basic computer terminology (bit, byte, data, real memory system, protected mode memory system, Windows, DOS, I/O) 3 Brief History of the Computers o1946 The first generation of Computer ENIAC (Electrical and Numerical Integrator and Calculator) was started to be used based on the vacuum tube technology, University of Pennsylvania o1970s entire CPU was put in a single chip. (1971 the first microprocessor of Intel 4004 (4-bit data bus and 2300 transistors and 45 instructions) 4 Brief History of the Computers (cont’d) oLate 1970s Intel 8080/85 appeared with 8-bit data bus and 16-bit address bus and used from traffic light controllers to homemade computers (8085: 246 instruction set, RISC*) o1981 First PC was introduced by IBM with Intel 8088 (CISC**: over 20,000 instructions) microprocessor oMotorola emerged with 6800.
  • SCAPP Package Spectrum CUDA Access for Parallel Programming

    SCAPP Package Spectrum CUDA Access for Parallel Programming

    SCAPP Package Spectrum CUDA Access for Parallel Programming for M4i and M2p cards, English version April 12, 2019 SPECTRUM INSTRUMENTATION GMBH · AHRENSFELDER WEG 13-17 · 22927 GROSSHANSDORF · GERMANY PHONE: +49 (0)4102-6956-0 · FAX: +49 (0)4102-6956-66 · E-MAIL: [email protected] · INTERNET: www.spectrum-instrumentation.com (c) SPECTRUM INSTRUMENTATION GMBH AHRENSFELDER WEG 13-17, 22927 GROSSHANSDORF, GERMANY SBench, digitizerNETBOX and generatorNETBOX are registered trademarks of Spectrum Instrumentation GmbH. Microsoft, Visual C++, Windows, Windows 98, Windows NT, Windows 2000, Windows XP, Windows Vista, Windows 7, Windows 8, Windows 10 and Windows Server are trademarks/registered trademarks of Microsoft Corporation. LabVIEW, DASYLab, Diadem and LabWindows/CVI are trademarks/registered trademarks of National Instruments Corporation. MATLAB is a trademark/registered trademark of The Mathworks, Inc. Delphi and C++Builder are trademarks or registered trademarks of Embarcadero Technologies, Inc. Keysight VEE, VEE Pro and VEE OneLab are trademarks/registered trademarks of Keysight Technologies, Inc. FlexPro is a registered trademark of Weisang GmbH & Co. KG. PCIe, PCI Express, PCI-X and PCI-SIG are trademarks of PCI-SIG. PICMG and CompactPCI are trademarks of the PCI Industrial Computation Manufacturers Group. PXI is a trademark of the PXI Systems Alliance. LXI is a registered trademark of the LXI Consortium. IVI is a registered trademark of the IVI Foundation Oracle and Java are registered trademarks of Oracle and/or its affiliates. Intel and Intel Core i3, Core i5, Core i7, Core i9 and Xeon are trademarks and/or registered trademarks of Intel Corporation. AMD, Opteron, Sempron, Phenom, FX, Ryzen and EPYC are trademarks and/or registered trademarks of Advanced Micro Devices.