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N-MOSFET Schematic Stanford University N-MOSFET Schematic Four structural masks: Field,,, Gate, Contact, Metal. Reverse doping polarities for pMOSFET in N-well. 3-4 H.-S. Philip Wong EE 316 Department of Electrical Engineering Stanford University N-MOSFET Schematic polysilicon gate gate V g oxide . Source terminal: Ground Vds potential. Gate voltage: Vgs . Drain voltage: V z ds . Substrate bias voltage: Vbs (Vsb) 0 y L Do you remember + + what is quasi- n source n drain Fermi level? x Depletion (x,y): Band bending at depletion region edge any point (x,y). inversion region V(y): Quasi-Fermi channel potential along the p-type substrate channel. W Boun dar y con di ti on s: -Vbs V(y=0) = 0, V(y=L) = Vds. 3-5 H.-S. Philip Wong EE 316 Department of Electrical Engineering Stanford University Long Channel Behavior . The electric field in the channel is essentiall y one - dimensional (normal to the semiconductor polysilicon surface) gate gate V g oxide . Mathematically: Ex >> Ey Vds Silicon surface z VDS 0 y L Ec n+ source n+ drain E q()x g E q q i E s B E fp x (> 0) f depletion E v inversion region E fn channel Oxide p-type silicon pptype-type substrate W x -Vbs 3-7 H.-S. Philip Wong EE 316 Department of Electrical Engineering Stanford University Drain Current Model n 2 Electron concentration: n(x) i eq( V )/ kT N a Electric field: 2 2 2 d 2kTNa q / kkT q ni qV / kkT q / kkT q E (x, y) e 1 2 e (e 1) dx si kT Na kT CditifCondition for sur face invers ion: V (y) plays the role of the reverse bias (0, y) V ( y) 2 B in a MOS capacitor under non - equilibrium Maximum depletion layer width at inversion: 22siVy() B Wydm() qNa 3-8 H.-S. Philip Wong EE 316 Department of Electrical Engineering Stanford University Current Density Equation drift diffusion dn J q nE qD n n n dy 2 q( V ) ni kT kT n e ; n Dn N A q dn q d dV n dy kT dy dy Current density equation (both drift and diffusion): dV()y Quasi- J (x, y) q n(x, y) nndy Fermi level 3-9 H.-S. Philip Wong EE 316 Department of Electrical Engineering Stanford University Gradual Channel Approximation Assumes that vertical field (Ex) is stronger than lateral field (Ey) in the channel region, thus 2-D Poisson’s equation can be solved in terms of 1-D vertical slices. Current density equation (both drift and diffusion): dV( y) Quasi- J (,)x y qn (,)x y Fermi level nndy Integrate in x- and z-directions, dV dV I ()y W Q ()y W QV () ds effdy i effdy i xi where Qy i () q nxydx (,) is the inversion charge per unit area. 0 Current continuity requires Ids independent of y, integration with respect to y from 0 to L yields W Vds Ids effQ i (V )dV L 0 3-10 H.-S. Philip Wong EE 316 Department of Electrical Engineering Stanford University H. C. Pao and C. T. Sah, “Effects of diffusion current on characteristics Pao-Sah’s Double Integral of metal-oxide (insulator)-semiconductor transistors,” Solid-State Elec tron., vol. 9, no. 10, pp. 927–937, Oc t. 1966. Change variable from (x,y) to (,V), n 2 nxy( , ) n(,V ) i eq( V )/kT Na 2 q( V )/ kT B dx s (ni / Na )e Qi (V ) q n( ,V ) d q d s d B E( ,V ) Substituting into the current expression, 2 q( V )/ kT V W ds s (ni / Na )e Ids qeff d dV 0 B L E( ,V ) How do you get this approximation? (see Lecture Notes p. 2-12 and 2-22 where (V) is solved by the gate voltage eq. for a and make s approximations) vertical slice of the MOSFET: 2 12/ Q 2 sikTN a q n s siqVkT()/ s VVgfbs V fb s 2 e CoxC ox kT N a 3-11 H.-S. Philip Wong EE 316 Department of Electrical Engineering Stanford University Example of ψs vs VG Relationship R. van Langevelde, F.M. Klaassen / Solid-State Electronics 44 (2000) 409 - 418 3-12 H.-S. Philip Wong EE 316 Department of Electrical Engineering Stanford University Charge Sheet Approximation Assumes that all the inversion charges are located at the silicon surface like a sheet of charge and that there is no pottildtential drop across thithe invers ion layer. After the onset of inversion, the surface potential is pinned at s =2= 2B + V(y). Depletion charge: Qd qNaWd max 2 siqNa (2 B V ) . Total charge: QCsoxgfbsoxgfbB ()(V V C V V 2 V ) . Inv. charge: QQQisd CVV oxgfbB()() 222 V siaB qN V W Vds Substituting in I ds eff QV i () dV and integrate: L 0 W Vds 22 siqN a 32// 32 ICds eff ox VVg fbB2 Vds ()()22BdsV B L 2 3Cox J.R. Brews, “A charge-sheet model of the MOSFET,” Solid-State Electronics, Volume 21, Issue 2, February 1978, Pages 345-355 3-13 H.-S. Philip Wong EE 316 Department of Electrical Engineering Stanford University Linear Region I-V Characteristics For Vds << Vg , W 4qN W ICVV 2 si a B VC ()VVV ds eff ox g fb B ds eff ox g t ds L Cox L 4siqN a B where VV tfbB 2 is the MOSFET threshold voltage. Cox 1E+0 080.8 65 nm technology 1E-2 0.6 scale) scale) yy yy 1E-4 0.4 1E-6 ds I ds I ( ) (arbitrar ar (arbitrar gg 0.2 Lo 1E-8 Line 1E-10 0 0 050.5 1 151.5 2 252.5 3 P. Bai et al., “A 65nm Logic Technology Featuring 35nm Gate V Lengths, Enhanced Channel 8 Cu Interconnect Layers, Low-k ILD Gate Voltage, g (V) 2 and 0.57 μm SRAM Cell,” IEDM, p. 657 (2004). VonVt 3-14 H.-S. Philip Wong EE 316 Department of Electrical Engineering Stanford University Experimental Determination of the Threshold Voltage . Linear e xtrapolation (LE) at the ma xim um G m point . Constant current (CC) method Often used in industry . Transconductance change (TC) method Used for modeling of devices D.K. Schroeder Semiconductor material and device characterization, 2nd ed, Wiley, New York (1998). 3-15 H.-S. Philip Wong EE 316 Department of Electrical Engineering Stanford University Example Id (and Gm) vs VGS curves R. van Langevelde, F.M. Klaassen / Solid-State Electronics 44 (2000) 409 - 418 3-16 H.-S. Philip Wong EE 316 Department of Electrical Engineering Stanford University Example log(Id) vs VGS curves R. van Langevelde, F.M. Klaassen / Solid-State Electronics 44 (2000) 409 - 418 3-17 H.-S. Philip Wong EE 316 Department of Electrical Engineering Stanford University Threshold Voltage Extraction Method Illustration H.S. Wong, M.H. White, T.J. Krutsick and R.V. Booth, Modeling of transconductance degradation and extraction of threshold voltage in thin oxide MOSFET's. Solid State Electron 30 (1987), p. 953. 3-18 H.-S. Philip Wong EE 316 Department of Electrical Engineering Stanford University 2 2 Example ∂Id / ∂VGS and ∂ Id / ∂VGS vs VGS curves R. van Langevelde, F.M. Klaassen / Solid-State Electronics 44 (2000) 409 - 418 3-19 H.-S. Philip Wong EE 316 Department of Electrical Engineering Stanford University Saturation Region I-V Characteristics W Vds 22 siqN a 32// 32 ICds eff oxVV g fb2 B Vds ()()22BdsV B L 2 3Cox W m 2 Keeping the 2nd order terms in V : ICds eff ox()VVV g t dsV ds ds L 2 qN / 4 C 3t where m 1 si a B 11 dm ox is the body-effect coefficient Cox Cox Wdm (Vdsat, Idsat) Vg4 Non-physical part (V V )2 W gt ofthf the Ids equation IIds dsat eff C ox for Vds > Vdsat L 2m Vg3 when in Current in aa V Vds = Vdsat = (Vg Vt)/m Dr g2 Vg1 Typically, m 1.2 Drain Voltage 3-21 H.-S. Philip Wong EE 316 Department of Electrical Engineering Stanford University Pinch-off Condition From inversion charge density point of view, Qioxgt()V C (V V mV ) W Vds while Ids effQV i () dV L 0 Qi(V) At Vds = Vdsat = (Vg Vt)/m, Qi = 0 and Ids = max. CVox ( g Vt ) Integrated area under the curve (shaded area) Ids 0 Vds Vdtdsat V Source Drain VV gt m 3-22 H.-S. Philip Wong EE 316 Department of Electrical Engineering Stanford University Beyond Pinch-off Channel length modulation 3-23 H.-S. Philip Wong EE 316 Department of Electrical Engineering Stanford University Saturation Characteristics – Experimental Example 65 nm technology CML DIBL Slope due to: . Channel length modulation (CLM) . Drain induced barrier lowering (DIBL) – to be discusse d la ter P. Bai et al., “A 65nm Logic Technology Featuring 35nm Gate Lengths, Enhanced Channel 8 Cu Interconnect Layers, Low-k ILD and 0.57 μm2 SRAM Cell,” IEDM, p. 657 (2004). 3-24 H.-S. Philip Wong EE 316 Department of Electrical Engineering Stanford University Subthreshold Region dn J q nE qD n n n dy V V 1E+0 V gt ds Low Drain Vds m 1E-1 Bias 1E-2 ry units) ry SiSaturation aa 1E-3 Diffusion region Component Sub- 1E-4 threshold region 1E-5 Current (arbitr Current Linear 1E-6 Drift region s Drain Drain Component 1E-7 y 1E-8 Vt Vg 00.511.52 Gate Voltage (V) 3-25 H.-S.
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