Stanford University

N-MOSFET Schematic

 Four structural masks: Field,,, Gate, Contact, Metal.  Reverse doping polarities for pMOSFET in N-well.

3-4 H.-S. Philip Wong EE 316 Department of Electrical Engineering Stanford University

N-MOSFET Schematic polysilicon gate gate V g oxide . Source terminal: Ground Vds potential. . Gate voltage: Vgs . Drain voltage: V z ds . Substrate bias voltage: Vbs

(Vsb) 0 y L Do you remember + + what is quasi- n source n drain Fermi level?

x Depletion (x,y): Band bending at depletion region edge any point (x,y). inversion region V(y): Quasi-Fermi channel potential along the p-type substrate channel. W Boun dar y con di ti on s: -Vbs V(y=0) = 0, V(y=L) = Vds.

3-5 H.-S. Philip Wong EE 316 Department of Electrical Engineering Stanford University

Long Channel Behavior

. The electric field in the channel is essentiall y one - dimensional (normal to the semiconductor polysilicon surface) gate gate V g oxide

. Mathematically: Ex >> Ey Vds Silicon surface z

VDS 0 y L Ec n+ source n+ drain E q()x g E q q i E s B E fp x (> 0) f depletion E v inversion region E fn channel Oxide p-type silicon pptype-type substrate W x -Vbs

3-7 H.-S. Philip Wong EE 316 Department of Electrical Engineering Stanford University

Drain Current Model n 2 Electron concentration: n(x)  i eq( V )/ kT N a Electric field: 2 2 2  d  2kTNa  q / kkT q  ni  qV / kkT q / kkT q  E (x, y)     e  1  2 e (e 1)    dx   si  kT  Na  kT 

CditifCondition for sur face invers ion: V (y) plays the role of the reverse bias  (0, y)  V ( y)  2 B in a MOS capacitor under non - equilibrium Maximum depletion layer width at inversion:

22siVy() B  Wydm() qNa

3-8 H.-S. Philip Wong EE 316 Department of Electrical Engineering Stanford University

Current Density Equation drift diffusion

dn J  q nE  qD n n n dy 2 q( V ) ni kT kT n  e ; n  Dn N A q dn q  d dV   n   dy kT  dy dy  Current density equation (both drift and diffusion):

dV()y Quasi- J (x, y)  q n(x, y) nndy Fermi level

3-9 H.-S. Philip Wong EE 316 Department of Electrical Engineering Stanford University Gradual Channel Approximation

Assumes that vertical field (Ex) is stronger than lateral field (Ey) in the channel region, thus 2-D Poisson’s equation can be solved in terms of 1 -D vertical slices.

Current density equation (both drift and diffusion): dV( y) Quasi- J (,)x y  qn (,)x y Fermi level nndy Integrate in x- and z-directions, dV dV I ()y   W Q ()y   W QV () ds effdy i effdy i xi where Qy i ()  q nxydx (,) is the inversion charge per unit area. 0

Current continuity requires Ids independent of y, integration with respect to y from 0 to L yields W Vds Ids  effQ i (V )dV L 0

3-10 H.-S. Philip Wong EE 316 Department of Electrical Engineering Stanford University

H. C. Pao and C. T. Sah, “Effects of diffusion current on characteristics Pao-Sah’s Double Integral of metal-oxide (insulator)-semiconductor transistors,” Solid-State Elec tron., vol. 9, no. 10, pp. 927–937, Oc t. 1966.  Change variable from (x,y) to (,V), n 2 nxy( , )  n(,V )  i eq( V )/kT Na 2 q( V )/ kT  B dx s (ni / Na )e Qi (V )  q n( ,V ) d  q d  s d  B E( ,V ) Substituting into the current expression, 2 q( V )/ kT V  W ds s (ni / Na )e  Ids  qeff d dV 0   B L  E( ,V)  How do you get this approximation? (see Lecture Notes p. 2-12 and 2-22 where  (V) is solved by the gate voltage eq. for a and make s approximations) vertical slice of the MOSFET:

2 12/ Q 2 sikTN a q n  s siqVkT()/ s  VVgfbs V fb s  2 e  CoxC ox  kT N a  

3-11 H.-S. Philip Wong EE 316 Department of Electrical Engineering Stanford University

Example of ψs vs VG Relationship

R. van Langevelde, F.M. Klaassen / Solid-State Electronics 44 (2000) 409 - 418

3-12 H.-S. Philip Wong EE 316 Department of Electrical Engineering Stanford University Charge Sheet Approximation

Assumes that all the inversion charges are located at the silicon surface like a sheet of charge and that there is no pottildtential drop across thithe invers ion layer.

After the onset of inversion, the surface potential is pinned at

s =2= 2B + V(y). 

. Depletion charge: Qd  qNaWd max   2 siqNa (2 B V )

. Total charge: QCsoxgfbsoxgfbB  ()(V V   C V V  2 V )

. Inv. charge: QQQisd CVV oxgfbB()() 222  V siaB qN  V

W Vds Substituting in I ds   eff  QV i ()  dV and integrate: L 0   W  Vds  22siqN a 32// 32  ICds eff ox VVg fbB2 Vds ()()22BdsV B L  2  3Cox  J.R. Brews, “A charge-sheet model of the MOSFET,” Solid-State Electronics, Volume 21, Issue 2, February 1978, Pages 345-355

3-13 H.-S. Philip Wong EE 316 Department of Electrical Engineering 

 Stanford University Linear Region I-V Characteristics

For Vds << Vg , W  4 qN  W ICVV 2 si a B VC()VVV ds eff ox g fb B  ds eff ox g t ds L  Cox  L

4 siqN a B where VV tfbB  2    is the MOSFET threshold voltage. Cox 1E+0 080.8

65 nm technology  1E-2 0.6 scale) scale) yy yy 1E-4 0.4

1E-6 ds I ds I ( ) (arbitrar ar (arbitrar gg 0.2 Lo 1E-8 Line

1E-10 0 0 050.5 1 151.5 2 252.5 3 P. Bai et al., “A 65nm Logic Technology Featuring 35nm Gate V Lengths, Enhanced Channel 8 Cu Interconnect Layers, Low-k ILD Gate Voltage, g (V) 2 and 0.57 μm SRAM Cell,” IEDM, p. 657 (2004). VonVt

3-14 H.-S. Philip Wong EE 316 Department of Electrical Engineering Stanford University

Experimental Determination of the Threshold Voltage

. Linear e xtrapolation (LE) at the ma xim um G m point . Constant current (CC) method Often used in industry

. Transconductance change (TC) method Used for modeling of devices

D.K. Schroeder Semiconductor material and device characterization, 2nd ed, Wiley, New York (1998). 3-15 H.-S. Philip Wong EE 316 Department of Electrical Engineering Stanford University

Example Id (and Gm) vs VGS curves

R. van Langevelde, F.M. Klaassen / Solid-State Electronics 44 (2000) 409 - 418

3-16 H.-S. Philip Wong EE 316 Department of Electrical Engineering Stanford University

Example log(Id) vs VGS curves

R. van Langevelde, F.M. Klaassen / Solid-State Electronics 44 (2000) 409 - 418

3-17 H.-S. Philip Wong EE 316 Department of Electrical Engineering Stanford University Threshold Voltage Extraction Method Illustration

H.S. Wong, M.H. White, T.J. Krutsick and R.V. Booth, Modeling of transconductance degradation and extraction of threshold voltage in thin oxide MOSFET's. Solid State Electron 30 (1987), p. 953.

3-18 H.-S. Philip Wong EE 316 Department of Electrical Engineering Stanford University

2 2 Example ∂Id / ∂VGS and ∂ Id / ∂VGS vs VGS curves

R. van Langevelde, F.M. Klaassen / Solid-State Electronics 44 (2000) 409 - 418

3-19 H.-S. Philip Wong EE 316 Department of Electrical Engineering Stanford University Saturation Region I-V Characteristics   W  Vds  22 siqN a 32// 32  ICds eff oxVV g fb2 B Vds ()()22BdsV B L  2  3Cox  W  m 2  Keeping the 2nd order terms in V : ICds eff ox()VVV g t dsV ds ds L  2   qN / 4 C 3t where m  1 si a B  11 dm  ox is the body-effect coefficient Cox Cox Wdm

(Vdsat, Idsat)

Vg4

Non-physical part (V  V )2 W gt ofthf the Ids equation IIds dsat eff C ox for Vds > Vdsat L 2m Vg3 when in Current in aa V Vds = Vdsat = (Vg  Vt)/m Dr g2

Vg1

Typically, m  1.2 Drain Voltage

3-21 H.-S. Philip Wong EE 316 Department of Electrical Engineering Stanford University Pinch-off Condition

From inversion charge density point of view,

Qioxgt()V  C (V V  mV )

W Vds while Ids effQV i () dV L 0

Qi(V) At Vds = Vdsat = (Vg  Vt)/m, Qi = 0 and Ids = max.

CVox ( g  Vt ) Integrated area under the curve (shaded area)  Ids

0 Vds Vdtdsat V Source Drain VV  gt m

3-22 H.-S. Philip Wong EE 316 Department of Electrical Engineering Stanford University

Beyond Pinch-off

Channel length modulation

3-23 H.-S. Philip Wong EE 316 Department of Electrical Engineering Stanford University Saturation Characteristics – Experimental Example

65 nm technology

CML DIBL

Slope due to: . Channel length modulation (CLM) . Drain induced barrier lowering (DIBL) – to be discusse d la ter

P. Bai et al., “A 65nm Logic Technology Featuring 35nm Gate Lengths, Enhanced Channel 8 Cu Interconnect Layers, Low-k ILD and 0.57 μm2 SRAM Cell,” IEDM, p. 657 (2004).

3-24 H.-S. Philip Wong EE 316 Department of Electrical Engineering Stanford University

Subthreshold Region dn J  q nE  qD n n n dy

V V 1E+0 V  gt ds Low Drain Vds m 1E-1 Bias 1E-2 ry units) ry SiSaturation aa 1E-3 Diffusion region Component Sub- 1E-4 threshold region 1E-5 Current (arbitr Current Linear 1E-6 Drift  region s Drain Drain Component  1E-7 y 1E-8 Vt Vg 00.511.52 Gate Voltage (V)

3-25 H.-S. Philip Wong EE 316 Department of Electrical Engineering Stanford University Subthreshold Currents  1/ 2  2  q s ni q( s V )/ kT  Qs  siEs  2 sikTNa   2 e   kT Na 

PiPower series expans i1ttion: 1st term Qd, 2dt2nd term Qi, 2     siqN a kT ni qVkT()/ s  Qi    e W Vds 2 s q Na Ids eff Q i (V )dV    L 0 2 2     W siqN a kT n i qkT sds// qVkT  Ids  eff     ee1 Solving for  using  s  L 2 s  q   N a  1/ 2 2 sikTN a q  V  V   s g fb s   2 Cox  kT  W  kT  qV()/ V mkT or, IC ()m 11  eegt  qVds / kT ds eff ox L  q  Inverse subthreshold slope: ln10 1  d(log I )  mkT kT  C  ln(10)kT / q1  60 mV / dec S  ds  23.. 23 1 dm      dVg  q q  Cox  at 300K

3-26 H.-S. Philip Wong EE 316 Department of Electrical Engineering Stanford University log(I ) Subthreshold I D Slope (S) on MOSFET

1 decade Ioff S

VG 0 VT VDD 1  d log ID  VG ΨS  Cdm  kT S      1  ln(10)  dVG  ΨS  log ID  Cox  q

GtGate t o ch annel pot enti tilal 60 m V/dec iMOSFETdin MOSFETs due t o coupling: >1 in MOSFETs Fermi-Dirac distribution

3-27 H.-S. Philip Wong EE 316 Department of Electrical Engineering Stanford University

Qti?Questions?

3-28 H.-S. Philip Wong EE 316 Department of Electrical Engineering Stanford University

Bodyyp Effect: Dependence of Threshold Volta ge on Substrate Bias You can either 1. Start with the Poisson’s

equation solution for Qs, Qd, Qi with the quasi-Fermi levels of the holes and electrons separated by the substrate

bias Vbs, or 2. Keep the substrate at zero (as the reference) and shift the source , drain, and gate

biases by Vbs

3-29 H.-S. Philip Wong EE 316 Department of Electrical Engineering Stanford University

Bodyyp Effect: Dependence of Threshold Volta ge on Substrate Bias You can either 1. Start with the Poisson’s equation solution for Qs, Qd, Qi with the quasi-Fermi levels of the holes and electrons separated by the substrate bias V , or If V  0, bs bs 2. Keep the substrate at zero (as the reference) and

shift the source , drain, and gate biases by Vbs   W  Vds  22siqN a 32// 32  ICds eff oxVV g fb2 B Vds ()()22BbsdsVV Bbs V  L  2  3Cox  1.8

 tox=200 Å Applied bias  Vbs 1.6 16 3  Na=10 cm Vfb=0 (V) 2 qN (2 V ) t si a B bs V 1.4  VVtfbB2  Cox 1.2 15 3  ld Voltage, Na=310 cm oo 1

dVt siqN a/(22 B V bs )  Thresh 0.8 dVbs Cox 0.6 qN / 4 C 3t 0246810 m 1 si a B 11dm  ox Cox Cox Wdm Substrate Bias Voltage, V bs (V) 3-30 H.-S. Philip Wong EE 316 Department of Electrical Engineering Stanford University Bodyyg Biasing for Low Power

3-31 H.-S. Philip Wong EE 316 Department of Electrical Engineering Stanford University

Application of Body Bias for Controlling Variations

3-32 H.-S. Philip Wong EE 316 Department of Electrical Engineering Stanford University Dependence of Threshold Voltage on Temperature

4 siqN a B VVtfbB2  Cox + For n poly gated nMOSFET, Vfb =  (Eg /2q)  B

Eg 4 siqN a B  Vt  B  2q Cox

dV 1 dE   qN /   d 1 dE d t g 1  sia B B g ()21m  B dT2 q dT C dT2 q dT dT  ox  See Taur & Ning p. 167-     168 for dVt k N cvN 3 m  1 dE g derivation  ()ln21m        steps dT q   N a  2  q dT

4 1/2 From Table 2. 1, dEg/dT  272.710 eV/K and ( NcNv)  2.41019 cm3. Note: Operating temperature is specified at 85 ○C for 16 3 For Na  10 cm and m  1.1, microprocessors and 150 ○CforC for dVt /dT is typically 1 mV/K. automotive applications

3-33 H.-S. Philip Wong EE 316 Department of Electrical Engineering Stanford University

Carrier Transport and Gate Capacitance

Linear Region: W I   C (V V )V ds eff ox L g t ds

Saturation Region:

W (V  V )2 II C gt ds dsat eff ox L 2m

Will come back to a more elaborate discussion later in the course about carrier transport.

Let’s first digress briefly abou t the gate capacitance Cox and the effective mobility µeff right now (we will return to them later again)

3-34 H.-S. Philip Wong EE 316 Department of Electrical Engineering Stanford University

MOSFET Channel Mobility Weighted average

xi with inversion carrier nnxdx() 0 density  eff  x i n(x)dx 0

It was empirically found that when eff is plotted against an effective normal field Eeff, there exists a “universal relationship” independent of the substrate bias, doping concentration, and gate oxide thickness (Sabnis and Clemens, IEDM 1979). 1  1  Here Eeff   Qd  Qi   si  2 

Since QqNCVVdsiaBoxtfbB42 () and QiCox(Vg  Vt),

Vt V fb  2 B Vg Vt  Eeff   3tox 6tox V V + Vt  0.2 g t For n poly gated nMOSFET, Eeff   3tox 6tox

3-35 H.-S. Philip Wong EE 316 Department of Electrical Engineering Stanford University

Electron Mobility . Low field region (low electron density): Limited by impurity or Coulomb scattering (screened at high electron densities).

. Intermediate field region: Limited by phonon scattering, 1/3 eff  32500E

. High field region (> 1 MV/cm): Limited by surface roughness scattering (less temp. dependence).

3-36 H.-S. Philip Wong EE 316 Department of Electrical Engineering Stanford University

Temperature Dependence of MOSFET Current

Note: Operating temperature is specified at 85 ○C for microprocessors and 150 ○C for automotive applications

3-37 H.-S. Philip Wong EE 316 Department of Electrical Engineering Stanford University

Hole Mobility

1  1  Eeff   Qd  Qi  si  3 

In general, pMOSFET mobility does not exhibit “universal” behavior as well as nMOSFET.

3-38 H.-S. Philip Wong EE 316 Department of Electrical Engineering Stanford University

Gate to body Intrinsic MOSFET Capacitance capacitance 1  11  Subthreshold region: CWLgd   WLC  CoxC d  What is the gate  Linear region: CWLCgox Gate to to source and gate to drain channel capacitance in  Saturation region: capacitance subthreshold?

y Qi ( y) Cox (VVg  t ) 1 L What i s th e gat e to body capacitance in the 2 linear region?  CWLC gox3

See Taur & Ning p. 131 for derivation steps

3-39 H.-S. Philip Wong EE 316 Department of Electrical Engineering