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Advancedmemorybufferc USOO7487428B2 (12) United States Patent (10) Patent No.: US 7487,428 B2 Co et al. (45) Date of Patent: Feb. 3, 2009 (54) FULLY-BUFFERED MEMORY-MODULE 7,010,642 B2 3/2006 Perego et al. .................. 711/5 WITH ERROR-CORRECTION CODE (ECC) 7,020,825 B2 * 3/2006 Watanabe et al. ..... ... 714,763 CONTROLLER IN SERALIZING 7,032,158 B2 4/2006 Alvarez, II et al. .......... 714/763 ADVANCEDMEMORYBUFFERCAMB).THAT EN E Erm7:6ey et al. .. - - - SSNN.THERBOARD 2006,0047899 A1 3/2006 Ilda et al. .................... T11 113 2006, OO75282 A1 4/2006 Borkenhagen et al. ......... 714/5 2006/0090112 A1 4/2006 Cochran et al. ............. 714/737 (75) Inventors: Ray s E. cy. 2006/0095592 A1 5/2006 Borkenhagen ................. 710/2 ; JaVId Sun, IrV1ne, * cited by examiner (73) Assignee: Kingston Technology Corp., Fountain Valley, CA (US) Primary Examiner Guy J Lamarre (74) Attorney, Agent, or Firm—Stuart T. Auvinen; g Patent (*) Notice: Subject to any disclaimer, the term of this LLC patent is extended or adjusted under 35 U.S.C. 154(b) by 417 days. (57) ABSTRACT (21) Appl. No.: 11/309.298 An error-correcting fully-buffered memory module can detect and correct some errors in data read from memory (22) Filed: Jul. 24, 2006 chips. An error correction code ECC controller is added to the Advanced Memory Buffer (AMB) on the memory module (65) Prior Publication Data that fully buffers memory requests sent as serial packets. The error correction controller generates ECC bits for write data, US 2008/0022186 A1 Jan. 24, 2008 and both the ECC bits and the write data are written to the (51) Int. Cl memory chips by a DRAM controller in the AMB. During Gii C 29/00 (2006.01) reads, an ECC checker generates a syndrome and can activate 52) U.S. C 714/763 an error corrector to correct data or signal a non-correctable (52) ir grgrrr. error. The corrected data is formed into serial packets sent (58) Field of Classification Search ............... 714/763 back to the motherboard by the AMB. Configuration data for See application file for complete search history. the ECC controller could be first programmed into a serial (56) References Cited presence-detect electrically-erasable programmable read only memory (SPD-EEPROM) on the memory module, and U.S. PATENT DOCUMENTS then copied to error-correction configuration registers on the 5,612,964 A 3, 1997 Haraszti ..................... T14f763 AMB during power-up. 6,345,374 B1* 2/2002 Tsuda ... 714,746 7,007,130 B1 2/2006 Holman ......................... 71 1/5 22 Claims, 8 Drawing Sheets TOIFROM DRAM'S 700 ECC CONTROLLER 100 SERIALIZER DESERIALIZER 304 (SERDES) SMBUS SBLANES INOUT NBLANES INFOUT 192 U.S. Patent Feb. 3, 2009 Sheet 1 of 8 US 7487,428 B2 S. SBLANES IN NBLANES OUT TO/FROM DRAM'S yN RE-TIME 8 RE-SYNC 66 YN SB LANES OUT FIG. 2 NBLANES IN PRIOR ART U.S. Patent Feb. 3, 2009 Sheet 2 of 8 US 7487,428 B2 MOTHERBOARD 28 DRAM DRAM 4 102 10 4 7 DRAM DRAM 7 102 104 7 DRAM DRAM Z. 102 104 7 DRAM DRAM PRIOR ART FIG. 3 U.S. Patent Feb. 3, 2009 Sheet 3 of 8 US 7487,428 B2 TO/FROM DRAM'S 700 ECC CONTROLLER 100 SERIALIZER DESERIALIZER 504 (SERDES) 1 1 SMBUS SBLANES IN/OUT NBLANES IN/OUT 192 FIG. 4 U.S. Patent Feb. 3, 2009 Sheet 4 of 8 US 7487,428 B2 SBLANES IN NBLANES OUT TO/FROM DRAM'S ECC CONFIG REGS SB LANES OUT NBLANES IN SPD 130 EEPROM ECC FIG. 5 CONFIG 132 U.S. Patent US 7487,428 B2 FIXERROR FIG. 6 U.S. Patent Feb. 3, 2009 Sheet 6 of 8 US 7487,428 B2 X9 X9 DRAM DRAM 602 602 630 x8636 x8 X8 X8 X8 ECC DRAM DRAM DRAM DRAM DRAM 632 632 632 632 U.S. Patent Feb. 3, 2009 Sheet 7 of 8 US 7487,428 B2 35 MEM ck BIST 30 MOTHERBOARD CTLR ------------- CTLR 28 ERROR FIG. 8 US 7487,428 B2 1. 2 FULLYBUFFERED MEMORY MODULE AMB 24. AMB 24 sends addresses and read signals to WITH ERROR-CORRECTION CODE (ECC) DRAM chips 22 to read the requested data, and packages the CONTROLLER IN SERALIZING data into external frames that are transmitted from AMB 24 ADVANCED-MEMORY BUFFER (AMB) THAT over metal contact pads 12 to other memory modules and ISTRANSPARENT TO MOTHERBOARD 5 eventually to the host processor. MEMORY CONTROLLER Memory module 10 is known as a fully-buffered memory module since AMB 24 buffers data from DRAM chips 22 to FIELD OF THE INVENTION metal contact pads 12. DRAM chips 22 do not send and receive data directly from metal contact pads 12 as in many This invention relates to memory modules, and more par 10 prior memory module standards. Since DRAM chips 22 do ticularly to memory modules with error-correction code not directly communicate data with metal contact pads 12, (ECC). signals on metal contact pads 12 can operate at very high data rates. BACKGROUND OF THE INVENTION FIG. 2 shows detail of an advanced memory buffer on a 15 fully-buffered memory module. AMB 24 contains DRAM Servers, personal computers (PCs), and other electronic controller 50, which generates DRAM control signals to read systems often use small printed-circuitboard (PCB) daughter and write data to and from DRAM chips 22 on memory cards known as memory modules instead of directly mount module 10. Data is temporarily stored in FIFO 58 during ing individual memory chips on a motherboard. The memory transfers. modules are built to meet specifications set by industry stan The data from FIFO 58 is encapsulated in frames that are dards, thus ensuring a wide potential market. High-volume sent over differential lines in metal contact pads 12. Rather production and competition have driven module costs down than being sent directly to the host central processing unit dramatically, benefiting the PC buyer. (CPU), the frames are passed from one memory module to the Memory modules are made in many different sizes and next memory module until the frame reaches the host CPU. capacities, such as older 30-pin and 72-pin single-inline 25 Differential data lines in the direction toward the host CPU memory modules (SIMMs) and newer 168-pin, 184-pin, and are known as northbound lanes, while differential data lines 240-pin dual inline memory modules (DIMMs). The “pins' from the CPU toward the memory modules are known as were originally pins extending from the module’s edge, but Southbound lanes. now most modules are leadless, having metal contact pads or When a frame is sent from the host CPU toward a memory leads. The modules are small in size, being about 3-5 inches 30 module, the frame is sent over the southbound lanes toward long and about an inch to an inch and a half in height. one of the memory modules in the daisy chain. Each memory The modules contain a small printed-circuit board Sub module passes the frame along to the next memory module in strate, typically a multi-layer board with alternating lami the daisy chain. Southbound lanes that are input to a memory nated layers of fiberglass insulation and foil or metal inter module are buffered by its AMB 24 using re-timing and connect layers. Surface mounted components such as DRAM 35 re-synchronizing buffers 54. Re-timing and re-synchronizing chips and capacitors are soldered onto one or both surfaces of buffers 54 restore the timing of the differential signals prior to the substrate. retransmission. Input buffers 52 and output buffers 56 contain FIG. 1 shows a fully-buffered memory module. Memory differential receivers and transmitters for the southbound module 10 contains a Substrate Such as a multi-layer printed lanes that are buffered by re-timing and re-synchronizing circuit board (PCB) with surface-mounted DRAM chips 22 40 buffers 54. mounted to the front surface or side of the substrate, as shown Frames that are destined for the current memory module in FIG. 1, while more DRAM chips 22 are mounted to the are copied into FIFO 58 and processed by AMB 24. For back side or surface of the substrate (not shown). Memory example, for a write frame, the data from FIFO 58 is written module 10 is a fully-buffered dual-inline memory module to DRAM chips 22 on the memory module by AMB 24. For (FB-DIMM) that is fully buffered by Advanced Memory 45 a read, the data read from DRAM chips 22 is stored in FIFO Buffer (AMB) 24 on memory module 10. 58. AMB 24 forms a frame and sends the frame to northbound Metal contact pads 12 are positioned along the bottom edge re-timing and re-synchronizing buffers 64 and out over the of the module on both front and back surfaces. Metal contact northbound lanes from differential output buffer 62. Input pads 12 mate with pads on a module socket to electrically buffers 66 and output buffers 62 contain differential receivers connect the module to a PC's motherboard. Holes 16 are 50 and transmitters for the northbound lanes that are buffered by present on Some kinds of modules to ensure that the module is re-timing and re-synchronizing buffers 64. correctly positioned in the socket. Notches 14 also ensure Self-testing of the memory module is supported by built-in correct insertion of the module. Capacitors or other discrete self-test (BIST) controller 60. BIST controller 60 may sup components are Surface-mounted on the Substrate to filter port a variety of self-test features such as a mode to test noise from the DRAM chips 22.
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