DDR ECC Reference Design to Improve Memory Reliability in 66Ak2gx-Based Systems

TI Designs: TIDEP-0070 DDR ECC Reference Design to Improve Memory Reliability in 66AK2Gx-Based Systems

TI Designs Features This reference design describes system considerations • 32-bit DDR3L Interface With Optional 4-bit ECC for for the DDR-SDRAM memory interface with Error High-Reliability System Designs Correcting Code (ECC) support in high-reliability • Flexible System Configurations With DDR ECC applications based on the 66AK2Gx Multicore DSP + ® • Built-In Read-Modify-Write (RMW) Hardware ARM System-on-Chip (SoC). System interfaces, Supporting ECC Operation With Non-Aligned board hardware, software, throughput performance, Access and diagnostic procedures, are discussed. Detailed description about the DDR interface is available in the • Minimum Performance Impact device Technical Reference Manual (TRM). • Implemented and tested on EVMK2G Hardware and Supported in Processor SDK for K2G Design Resources Applications TIDEP0070 Design Folder • Automotive Audio Amplifiers 66AK2G02 Product Folder • Home Audio 66AK2G12 Product Folder K2G General Purpose • Professional Audio EVM Tool Folder EVM • Power Protection Processor SDK for K2G Download Software • Industrial Communications and Controls

ASK Our E2E Experts

66AK2G

DDREMIF

Control Address Data

Device_0

… …

Device_n

Device_ECC

An IMPORTANT NOTICE at the end of this TI reference design addresses authorized use, intellectual property matters and other important disclaimers and information.

TIDUBO4B–April 2016–Revised June 2018 DDR ECC Reference Design to Improve Memory Reliability in 66AK2Gx- 1 Submit Documentation Feedback Based Systems Copyright © 2016–2018, Texas Instruments Incorporated Introduction www.ti.com 1 Introduction The 66AK2Gx SoC supports the following features: • Processor Cores and Memory – Arm® Cortex-A15 up to 1000 MHz • 32 KB L1D, 32 KB L1P, 512 KB L2 cache – C66x DSP up to 1000 MHz • 32 KB L1D, 32 KB L1P, 1 MB L2 cache or RAM – 1MB of Shared L2 MSMC SRAM – ECC on all memory • Industrial and Control Peripherals – 2 Industrial Communication Subsystems enable cut through, real-time and low-latency Industrial Ethernet protocols – Programmable real-time I/O enables versatile field bus and control interfaces – PCIe for connection to an FPGA or ASIC that provides industrial network connections, backplane communication or connection to another 66AK2Gx device • Security and Crypto – Standard secure boot with customer programmable OTP keys – Crypto Engine hardware accelerator and TRNG – Package • 21 x 21 mm, 0.8 mm pitch BGA 625 pins The 66AK2Gx SoC is suited for applications such as Industrial PLC and Protection Relay as shown in Figure 1 and Figure 2. In these systems ECC on the memory is required for achieving reliability requirements. Device reliability requires managing failures that can cause the device not to function correctly at any point during its expected lifetime.

66AK2G02

DDR3 ARM® C66x Cortex-A15 DSP USB Flash Drive

USB2/3 SD Card Connectivity SD/MMC

Display SPI I2C Subsystem 2x PCIe UART PRU- ICSS GPMC CAN UART GbE

Optional Simple LCD Display Industrial Field- Level EPHY 100Mb Industrial Industrial EPHY Ethernet

Gb Control - Level Industrial EPHY 100Mb EPHY Industrial Ethernet Industrial or Custom EPHY Backplane Ethernet Service Port 1 Copyright © 2016, Texas Instruments Incorporated Figure 1. Industrial PLC System Block Diagram

2 DDR ECC Reference Design to Improve Memory Reliability in 66AK2Gx- TIDUBO4B–April 2016–Revised June 2018 Based Systems Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated www.ti.com Introduction

66AK2G02

DDR3 C66x ARM® C66x Cortex-A15 DSPDSP (Control, Comms) (Analytics, Metering) (Analytics, Metering)

USB2/3 Connectivity SD/MMC

SPI Display PCIe I2C Subsystem UART 2x GbE GPMC UART PRU - ICSS CAN

Simple LCD Display

Ethernet Industrial EPHY

Ethernet Industrial IEC61850 or EPHY

Ethernet Industrial EPHY

Gb Ethernet Industrial EPHY IEC61850 to SCADAEPHY

Error Correcting Code (ECC) memory is commonly used in server and communications infrastructure systems today and has significantly improved system reliability. In embedded systems, a similar trend is observed, where ECC memory is required for a variety of applications, such as: • Safety-critical industrial and factory automation systems • Harsh operating environment such as extreme temperature, pressure or radiation environment • Always-on systems with extended duty hours

TIDUBO4B–April 2016–Revised June 2018 DDR ECC Reference Design to Improve Memory Reliability in 66AK2Gx- 3 Submit Documentation Feedback Based Systems Copyright © 2016–2018, Texas Instruments Incorporated Introduction www.ti.com Figure 3 shows the relative failure rate reduction when ECC is used.

1.5% Non-ECC ECC 1.25% 1.16%

1% 0.93% 0.83% 0.75%

0.53% Failure Rate Failure 0.5%

0.25% 0.19%

0% 0 2011 2012 2013 Non-Ecc Failure Rates (Year) D001 Figure 3. Memory Failure Rate Reduction With ECC

The 66AK2Gx SoC supports various methods of ECC in its internal memory and external memory interfaces. Namely, ECC is supported on: • Processor core memory blocks • Internal Multicore Shared Memory Controller (MSMC) SRAM • Embedded SRAM memory blocks in other subsystems • DDR3L memory interface Except for the L1P in the A15 processor core, all ECC functions listed above implement Single Error Correction and Double Error Detection (SECDED) method using Hamming Code. This design guide focuses on the DDR interface design with ECC in systems where high reliability is required. The DDR3L memory interface supports standard 32-bit DDR3L interface up to 800MT/s. Additional 4-bit data is available to support optional Error Correcting Code (ECC). ECC is performed on 32-bit quanta based on the SECDED algorithm. When the DDREMIF is used as 16-bit interface, no ECC is supported.

4 DDR ECC Reference Design to Improve Memory Reliability in 66AK2Gx- TIDUBO4B–April 2016–Revised June 2018 Based Systems Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated www.ti.com System Overview 2 System Overview The DDR3L interface consists of the following subsystems: • DDREMIF controller — digital interface, FIFOs, and ECC module • DDR3LPHY — consists of DDR3L PHY macros and system interface logic Figure 4 shows the interconnect of the sub-modules in the 66AK2Gx SoC.

66AK2G

ARM DSP A15 C66

MSMC

DDREMIF to CBASS

DDR3LPHY

Figure 4. DDREMIF and DDR3L PHY Subsystems in 66AK2Gx Devices

The ECC block is connected in front of the data and command FIFOs within the DDREMIF controller, as shown in Figure 5. The ECC block enables the Read-Modify-Write (RMW) feature that is not available in some earlier KeyStone™ II devices. The RMW block allows data write that is not aligned to a 32-bit boundary, by first read, the full quanta data from the DDR device merges with the non-aligned data, recalculates ECC, and writes back to DDR. This procedure incurs extra write latency.

DDREMIF (only shown RMW ECC and FIFOs)

Read Modify Write Command/Data Command/Data To DDR 3L To MSMC ECC FIFOs Schedulers SDRAM

TIDUBO4B–April 2016–Revised June 2018 DDR ECC Reference Design to Improve Memory Reliability in 66AK2Gx- 5 Submit Documentation Feedback Based Systems Copyright © 2016–2018, Texas Instruments Incorporated System Specifications www.ti.com 3 System Specifications Table 1 lists different DDR configurations depending on the required DDR interface for the device.

NOTE: The 4-bit devices are not supported unless the device is used as an ECC device.

Table 1. DDR Configurations for 66AK2Gx-Based Systems

CONFIGURATION DDR WIDTH DDR DEVICES ECC 1 16-bit DDR3L with no ECC 2 × 8b – 2 16-bit DDR3L with no ECC 1 × 16b – 3 32-bit DDR3L with no ECC 4 × 8b – 4 32-bit DDR3L with no ECC 2 × 16b – 5 32-bit DDR3L with 4-bit ECC 4 × 8b 1 × 4b 6 32-bit DDR3L with 4-bit ECC 4 × 8b 1 ×8b (tie-off upper 4-bit) 7 32-bit DDR3L with 4-bit ECC 2 × 16b 1 × 4b 8 32-bit DDR3L with 4-bit ECC 2 × 16b 1x8b (tie-off upper 4-bit) 9 No DDR – –

6 DDR ECC Reference Design to Improve Memory Reliability in 66AK2Gx- TIDUBO4B–April 2016–Revised June 2018 Based Systems Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated www.ti.com System Specifications Figure 6 shows an example system interconnection between 66AK2Gx and five 8-bit external devices.

DDR 3L DDR 3RESETz RESET Device 0 DDR 3RASz RAS DDR 3CASz CAS DDR 3WEz WE DDR 3CKE 0 CKE DDR 3CE 0 CS DDR 3CLKOUT 0p/n CK DDR 3A[15 :0] DDR 3A[15 :0] DDR 3BA [2:0] DDR 3BA [2:0] DDR 3DQS 0p/n DQSp /n DDR 3D [7:0] DQ [7:0] DDR 3CE 1 DDR 3CLKOUT 1p/n RESET Device 1 RAS CAS WE CKE CS CK DDR 3A[15 :0] DDR 3BA [2:0] DDR 3DQS 1p/n DQSp/n DDR 3D [15 :8] DQ [7:0]

RESET Device 2 RAS CAS WE CKE CS CK DDR 3A[15 :0] DDR 3BA [2:0] DDR 3DQS 1p/n DQSp /n DDR 3D [23:16 ] DQ [7:0]

RESET Device 3 RAS CAS WE CKE CS CK DDR 3A[15 :0] DDR 3BA [2:0] DDR 3DQS 1p/n DQSp /n DDR 3D [31 :24 ] DQ [7:0]

RESET Device ECC RAS CAS WE CKE CS CK 3CBDQSp CBDQSp DDR 3A [15 :0] DDR 3BA [2:0] DDR 3CBDQSp/n DQSp /n DDR 3DQM [3:0] DQ [3:0]

Figure 6. Signal Interconnect of 4 × 8 + 1 × 8 32-bit DDR configuration with ECC

TIDUBO4B–April 2016–Revised June 2018 DDR ECC Reference Design to Improve Memory Reliability in 66AK2Gx- 7 Submit Documentation Feedback Based Systems Copyright © 2016–2018, Texas Instruments Incorporated System Specifications www.ti.com Figure 7 shows the DDR3L device placement relative to the 66AK2Gx device on the EVMK2G board.

C129 R301

R258

R268 R287 R856 R344

R307 R214 R256 R212 R213 R211 R209 R206 R207 R215 R306 R333 U29 R279 R208 R230 U40 C146 U127 R237 R217 R309 R216 R241 U27 R285 TP106 R339 R295

R299

R286

R260 R305 R210 C113 R271 R308 R265 R701 R247 R318 U38 R321 R233 R698

R292

R269 R281 C147 R261 R315

U39

TP115

C171 C170

TP124 R814 C177 R815 TP141 U135 TP143 R870

R368 R369 TP131

C710

U64

R490 U45 TP135 TP142 R491

R385 U112 R386

R365 R366 C785 C786 TP125 R912 R812 TP123 C172 R784 R373 TP133

R379 C784

R376 R377 R378 U59 R913

R387 R388 TP140 R737 C182 RA6

TP139 R869 R328 R407 TP136

C187

C178 C185 C179 R415 R401 R423 C794 U49 C557 R413 R396 C795 R398 R439 R823 TP126 C227 R394 R434 R816

C668 C669 R817 R425 C209 R422 R410 R416 C208 R473 R482 R430 C605 C598 R468 R451 C203 R454 R460 R447 TP153 R477 U1 R418 R421

C610 R820 U52 TP128 TP155 C202 R432 R419 R452 R436 R441 R427 TP154 R462 R437 R424

C677 C603 R431 C678 C224 C225 R761 U123 R443 C264 C229 C758 C231 R446

C759 R833 C233 R449 R450 C756 C239 R453 C238 C236 R445 R832 C757 C240

C259 FB27 U122 C255 TP159 TP145

C258

C261

C250 C268 R475 R896 RA7

FB26 R803

R804

C274 C266 R465

R466

R467 R464 C778 R463

R461

C254 R514 R511 R512 R513 R474 FB31

C272

C273 TP132 TP158 R857 U56 R478 U60 R479 C262 C265 C269 C777 C271 R483 R891 U50 C278 R890 U67 R498 C206 U47 R24 C532 C277 R485 TP127 U62 R23 Y7

Figure 8 shows the DDR devices on the EVMK2G.

DDR+ ECC

Figure 8. DDR Devices on the EVMK2G

8 DDR ECC Reference Design to Improve Memory Reliability in 66AK2Gx- TIDUBO4B–April 2016–Revised June 2018 Based Systems Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated www.ti.com Software 4 Software The processor SDK supports configuration, initialization, and testing on the DDR ECC, for systems using the feature.

4.1 Initialization ECC and RMW options are controlled by memory mapped registers. Refer to the device datasheet (SPRSP07) for the exact register address and assignment. The RMW feature is always enabled whenever ECC is enabled. The following steps are involved to enable ECC: 1. Enable bit[35:32] of the PHY macro (including leveling and training) 2. Enable ECC + RMW 3. Read back control register and verify ECC+RMW is enabled 4. Initialize DDR memory to validate ECC syndrome

NOTE: The entire ECC enabled DDR space must be initialized before any of the ECC memory region is used. Otherwise, due to RMW operations, a non-aligned write operation may invoke the DDREMIF to read back an incorrect ECC syndrome and thus cause ECC error.

Figure 9 shows an example GEL script to enable ECC. ddr3A_setup(int ECC_Enable, int DUAL_RANK) { ……

if(ECC_Enable == 0) { read_val = DDR3A_DATX8_4; DDR3A_DATX8_4 = read_val & 0xFFFFFFFE; //Disable ECC byte lane } ……

if(ECC_Enable==1) { //Enable ECC //0xB0000000: ECC_EN=1, ECC_VERIFY_EN=1, RMW_EN=1 //0x50000000: ECC_EN=1, ECC_VERIFY_EN=0, RMW_EN=1 DDR3A_ECC_CTRL = 0xB0000000; read_val = DDR3A_ECC_CTRL; if(read_val!=0xB0000000){ GEL_TextOut("\nIncorrect data written to DDR3A_ECC_CTRL.."); }

} Figure 9. GEL Script to Enable ECC and RMW

TIDUBO4B–April 2016–Revised June 2018 DDR ECC Reference Design to Improve Memory Reliability in 66AK2Gx- 9 Submit Documentation Feedback Based Systems Copyright © 2016–2018, Texas Instruments Incorporated Software www.ti.com 4.2 Verification and Diagnostics Frequently, it may be required to verify the proper operation of the ECC, especially when the final product is presented to an independent safety compliance assessment body. A simple technique to prove out the proper operation of ECC may be: 1. Enable ECC, write a set of data to DDR. The data could be a combination of aligned and non-aligned bytes. 2. Read and verify these data matched to originals. 3. Disable the ECC by changing the control register. 4. Write a modified data set to the same address, modified means some data has 1 bit errors and some data has 2 or more bits of errors. 5. Reenable ECC. 6. Read back these data and compare with original, verify that single bit error counter increased when accessing single bit modified data, and a kernel panic happened when more than one bit modified data is accessed. This procedure must be performed to ensure that no other DDR access is present. A real-life random memory bit error may be generated in a laboratory where the device is running under bombardment of high-energy particles such as a high-energy physics accelerator facility.

4.3 ECC Error Handling Kernels of operating systems typically handle ECC error interrupts. Single-bit errors are automatically corrected when the data is presented to the host, however, data stored in the memory is not corrected. To reduce the probability of another single-bit error from happening in the same quanta block,perform software scrubbing where a scrubbing software performs periodic access to ECC-protected DDR space. When a single-bit error occurs, the scrubbing software first reads, and then writes back the correct data so the memory content is correct. Current K2G Processor SDK Linux® kernel does not perform scrubbing. For a 1-bit ECC error, no direct interrupt will be generated, instead the EMIF can be programmed with a threshold to its ECC Error Count Register. An interrupt will be generated so the host software can re-write memory addresses containing error bits. The 2-bit ECC will immediately trigger an interrupt to the host, typically causes a kernel panic and subsequently causes a device reset.

4.4 Processor SDK Software Support Both Linux and RTOS branch of the Processor SDK support initialization, verification and error handing of the ECC. Table II lists sub-modules in each branch related to ECC functions. ECC and RMW are enabled by default in both Processor SDK Linux and Processor SDK TI-RTOS to match to K2G GP EVM hardware. But can be disabled if not required by customer systems. Table 2 lists software support for DDR ECC.

Table 2. Software Support for DDR ECC

OPERATIONS DESCRIPTION PROCSDK-RTOS PROCSDK-Linux Enablement / Enable data macros, leveling and training GEL file scripts u-boot Initialization Memory Initialization Initialize memory for correct syndrome Yes u-boot Kernel Handling – Frequently scrub memory to correct No (user software) No (user software) Scrubbing single-bit errors in memory device Kernel Handling – Cause kernel panic if double-bit error is Not supported (user Kernel Panic Unrecoverable encountered software) Verification / Example code (user Utility or example to verify ECC support Linux Utility (user software) Diagnostics software)

10 DDR ECC Reference Design to Improve Memory Reliability in 66AK2Gx- TIDUBO4B–April 2016–Revised June 2018 Based Systems Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated www.ti.com Test Data 5 Test Data For DDR access 8-byte aligned addresses, the ECC is transparently read and verified by the hardware controller. Therefore no impact on latency or memory throughput is expected. Table 3 lists measured block data transfers from the C66x L2 memory to the DDR space, with- and without- ECC enabled in the controller.

Table 3. Throughput Comparison of DDR ECC With and Without ECC Enabled

TEST SOURCE DESTINATION ACNT BCNT BIT LENGTH THROUGHPUT 1 DSP L2 DDR3L 16384 1 131072 98.27% 2 DSP L2 DDR3L 32768 1 262144 99.13% 3 DSP L2 DDR3L 1 32768 262144 99.19% 5 DSP L2 DDR3L 2 32768 524288 99.59% 6 DSP L2 DDR3L 4 32768 1048576 99.65% 7 DSP L2 DDR3L 8 32768 131072 98.27%

In cases where non-aligned write access made to the DDR, the RMW procedure will be performed, where the DDREMIF controller first read the aligned data from the DDR, merge with requested write bytes, re- calculate ECC error correction code, then write to the DDR memory. Latency due to RMW operation is dependent on the background simultaneous access to the DDR, and the DDR command and data FIFO fill levels.

6 Design Files The design files for the K2G General Purpose EVM may be found at http://www.ti.com/tool/evmk2gx.

7 Related Documentation

1. Keystone II Architecture DDR3 Memory Controller User's Guide (SPRUHN7) 2. Hardware Design Guide for KeyStone II Devices (SPRABV0) 3. DDR3 Design Requirements for KeyStone Devices (SPRABI1) 4. Advantages of ECC Memory, https://www.pugetsystems.com/labs/articles/Advantages-of-ECC- Memory-520/ 5. 66AK2Gx Multicore DSP + ARM KeyStone II System-on-Chip (SoC) Technical Reference Manual (SPRUHY8)

7.1 Trademarks KeyStone is a trademark of Texas Instruments. Arm is a registered trademark of ARM Limited. Linux is a registered trademark of Linus Torvalds.

TIDUBO4B–April 2016–Revised June 2018 DDR ECC Reference Design to Improve Memory Reliability in 66AK2Gx- 11 Submit Documentation Feedback Based Systems Copyright © 2016–2018, Texas Instruments Incorporated About the Author www.ti.com 8 About the Author DR. JIAN WANG is a Chip Architect with the Catalog Processor Group. Dr. Wang joined TI in 2006 as a Video Systems Engineer, working on Davinci family of digital media processors. His recent roles focus on SOC system architecture for machine vision and next-generation industrial applications.

12 DDR ECC Reference Design to Improve Memory Reliability in 66AK2Gx- TIDUBO4B–April 2016–Revised June 2018 Based Systems Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated www.ti.com Revision History

Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Original (April 2016) to B Revision ...... Page

• Changed document title to "66AK2Gx"...... 1 • Added 66AK2G12 Product Folder ...... 1 • Changed EVM Tool Folder to EVMK2G (1GHz version)...... 1 • Changed "at 600 MHz" to "up to 1000 MHz" for both Cortex-A15 and C66x ...... 2 • Added MSMC subsystem details...... 2 • Changed datasheet URL to 66AK2G12 version (SPRSP07)...... 9

Texas Instruments Incorporated (‘TI”) technical, application or other design advice, services or information, including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to assist designers who are developing applications that incorporate TI products; by downloading, accessing or using any particular TI Resource in any way, you (individually or, if you are acting on behalf of a company, your company) agree to use it solely for this purpose and subject to the terms of this Notice. TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections, enhancements, improvements and other changes to its TI Resources. You understand and agree that you remain responsible for using your independent analysis, evaluation and judgment in designing your applications and that you have full and exclusive responsibility to assure the safety of your applications and compliance of your applications (and of all TI products used in or for your applications) with all applicable regulations, laws and other applicable requirements. You represent that, with respect to your applications, you have all the necessary expertise to create and implement safeguards that (1) anticipate dangerous consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and take appropriate actions. You agree that prior to using or distributing any applications that include TI products, you will thoroughly test such applications and the functionality of such TI products as used in such applications. TI has not conducted any testing other than that specifically described in the published documentation for a particular TI Resource. You are authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING TI RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY YOU AGAINST ANY CLAIM, INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL, DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. You agree to fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of your non- compliance with the terms and provisions of this Notice. This Notice applies to TI Resources. Additional terms apply to the use and purchase of certain types of materials, TI products and services. These include; without limitation, TI’s standard terms for semiconductor products http://www.ti.com/sc/docs/stdterms.htm), evaluation modules, and samples (http://www.ti.com/sc/docs/sampterms.htm).