DOCSLIB.ORG

Securing Intel Sgx Against Side-Channel Attacks Via Load-Time Synthesis

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Securing Intel Sgx Against Side-Channel Attacks Via Load-Time Synthesis SECURING INTEL SGX AGAINST SIDE-CHANNEL ATTACKS VIA LOAD-TIME SYNTHESIS A Dissertation Presented to The Academic Faculty By Ming-Wei Shih In Partial Fulfillment of the Requirements for the Degree Doctor of Philosophy in the School of Georgia Institute of Technology Georgia Institute of Technology December 2019 Copyright © Ming-Wei Shih 2019 SECURING INTEL SGX AGAINST SIDE-CHANNEL ATTACKS VIA LOAD-TIME SYNTHESIS Approved by: Dr. Taesoo Kim, Advisor Dr. Michael Steiner School of Computer Science Security and Privacy Research Georgia Institute of Technology Group Intel Labs Dr. Wenke Lee School of Computer Science Dr. Brendan Saltaformaggio Georgia Institute of Technology School of Computer Science Georgia Institute of Technology Dr. Marcus Peinado Cloud and Infrastructure Security Date Approved: Octobor 23, 2019 Group Microsoft Research To my dear wife, Tiffany, and my family. ACKNOWLEDGEMENTS Foremost, I would like to express my sincere gratitude to my advisor Dr. Taesoo Kim for all the support and guidance he provided to me throughout my Ph.D. study. He has taught me how to conduct research in system security since my first year—when I literally know nothing about how to do so. His solid technical background and logical, critical thinking have always inspired me. I would also like to thank Dr. Marcus Peinado for always providing constructive comments when we collaborated on T-SGX and SGX-Armor. I have learned a lot from working with him. Besides, I would like to thank the rest of my thesis committee: Dr. Wenke Lee, Dr. Michael Steiner, and Dr. Brendan Saltaformaggio for their insightful comments that helped me improve this thesis. I would like to express my special thanks to Dr. Sangho Lee for the fruitful discussions and the help when we collaborated on T-SGX and PRIDWEN. Additionally, I would like to thank my colleagues at SSLab: Sanidhya, Meng, Insu, Ren, Wen, Jinho, Soyeon, Fan, Seulbae, Hanqing, and former members, Steffen and Mohan for all the discussions and the good time spent together. Last but not least, I would like to thank my family: my wife, Tiffany, my parents, and my brothers for supporting me spiritually throughout writing this thesis and my life in general. Finally, I thank my God for letting me through all the difficulties. I have experienced Your guidance day by day. You are the one who brought me here and let me finish my degree. I will keep on trusting You for my future. iv TABLE OF CONTENTS Acknowledgments . iv List of Tables . x List of Figures . xii Chapter 1: Introduction . 1 1.1 Research Objectives . 2 1.1.1 Retrofitting Existing Side-Channel Defenses . .3 1.1.2 Designing New Side-Channel Defenses . 3 1.1.3 Developing a General Side-Channel Defense Framework . 4 1.2 Thesis Contributions . 5 1.3 Outline of the Thesis . 6 Chapter 2: Background . 7 2.1 Intel Software Guard Extensions (SGX) . 7 2.2 Exceptions in Software Guard Extensions (SGX) . 8 2.3 Side-Channel Attacks (Side-Channel Attacks (SCAs)) . 9 2.4 Address Space Layout Randomization (ASLR) . 10 2.5 Intel Transactional Synchronization Extension (TSX) . 11 v 2.6 WebAssembly (Wasm) . 13 Chapter 3: Securing ASLR on SGX against Multifaceted Side-channel Attacks . 15 3.1 Introduction . 15 3.2 Threat Model . 19 3.2.1 System Model . 19 3.2.2 ASLR Model . 20 3.2.3 Adversary Model . 22 3.3 New Attacks against ASLR . 24 3.3.1 Attacks on Randomized Layout Generation . 24 3.3.2 Attack on ASLR at Runtime . 26 3.4 Mitigation against Attacks on Layout Generation . 31 3.4.1 Secure Layout Generation . 31 3.5 Implementation . 36 3.5.1 Automated Attack Analysis Framework . 36 3.5.2 Attacks against SGX-Shield . 37 3.5.3 SGX-Armor Prototype . 40 3.6 Evaluation . 41 3.6.1 Attacking Layout Generation . 42 3.6.2 Attacking Runtime Randomization . 44 3.6.3 Overhead of SGX-Armor . 46 3.7 Discussion: Mitigation against Runtime Attacks . 47 3.8 Related Work . 49 vi Chapter 4: Eradicating Controlled-Channel Attacks against Enclave Programs . 52 4.1 Introduction . 52 4.2 Controlled-channel Attack Revisited . 56 4.2.1 Threat Model . 56 4.2.2 Controlled-channel Attack . 57 4.2.3 Known Countermeasures . 58 4.2.4 Overwriting Exit Reason . 58 4.3 System Model . 59 4.4 Design . 61 4.4.1 Overview of the TSX-based Design . 61 4.4.2 The Springboard . 62 4.4.3 Execution Blocks . 65 4.4.4 Transaction Constraints . 65 4.4.5 Optimization Techniques . 67 4.4.6 Abort Sequence . 69 4.4.7 Preventing Reruns . 70 4.4.8 External calls . 71 4.4.9 Illegal instructions . 71 4.5 Implementation . 71 4.6 Security Analysis . 72 4.7 Evaluation . 74 4.7.1 Application Binaries . 75 vii 4.7.2 Run-time Performance . 77 4.8 Discussion . 81 4.8.1 Limitations . 81 4.8.2 Other Side-channel Attacks . 82 4.9 Related Work . 83 Chapter 5: Securing SGX Programs against Side-Channel Attacks via Load-Time Synthesis . 86 5.1 Introduction . 86 5.2 Threat Model . 90 5.3 PRIDWEN Design . 91 5.3.1 Goals . 91 5.3.2 Overview . 92 5.3.3 User-mode Hardware Probing . 93 5.3.4 Pass Manager . 94 5.3.5 Load-time Synthesis . 96 5.3.6 Post-synthesis Validation . 100 5.4 Case Study . 100 5.4.1 Fine-grained ASLR . 101 5.4.2 T-SGX . 102 5.4.3 Varys . 103 5.4.4 QSpectre . 105 5.4.5 Pass Integration . 106 5.4.6 Security Analysis . 107 viii 5.5 Implementation . 108 5.6 Evaluation . 109 5.6.1 Performance Characteristics of the PRIDWEN Loader . 110 5.6.2 Faithfulness of Execution . 113 5.6.3 Performance of Synthesized Binaries . 114 5.7 Discussion . 118 5.8 Related Work . 119 Chapter 6: Conclusion and Future Work . 121 References . 141 ix LIST OF TABLES 3.1 The summary of published fine-grained ASLR systems. Level represents the granularity of the randomization. A: base address. F: function. P: page. B: basic block. I: instruction. 20 3.2 The results of initial layout attacks on target applications. 43 3.3 The entropy averaged on the three target applications under different ASLR schemes. base: baseline entropy. loading, relocation, runtime: entropy left after each of the corresponding attack. 43 3.4 The results of the runtime attack on target applications. 44 3.5 The load-time performance of SGX-Armor. 46 3.6 The results of running nbench SGX-Armor. 46 4.1 Benchmark programs (top) and applications (bottom) used to evaluate T-SGX. 75 4.2 Run-time overhead of TSX-basic and T-SGX over baseline. 78 4.3 Rate and type of transaction aborts for the nbench applications for T-SGX. 79 4.4 Distribution of the number of times a transaction aborts before it succeeds. 80 5.1 Side-channel attacks against SGX and countermeasures. Hyper-Threading Technology (HT), L1 Terminal Fault (L1TF), and Microarchitectural Data Sampling (MDS). 87 5.2 The APIs for the instrumentation (top) and validation (bottom) support. CCTX: CompilerContext. MI: MachineInstr. MCTX: MachineContext. MB: MachineBasicBlock. ............................. 95 x 5.3 Attack surfaces and software-only or hardware-assisted mitigation schemes PRIDWEN implements. Central Processing Units (CPUs) with recent mi- crocode update do not have some of the attack surfaces. 101 5.4 Comparison of lines of code and binary size between PRIDWEN and LLVM backends. ..
Load more

Recommended publications
  • Inside Intel® Core™ Microarchitecture Setting New Standards for Energy-Efficient Performance
    White Paper Inside Intel® Core™ Microarchitecture Setting New Standards for Energy-Efficient Performance Ofri Wechsler Intel Fellow, Mobility Group Director, Mobility Microprocessor Architecture Intel Corporation White Paper Inside Intel®Core™ Microarchitecture Introduction Introduction 2 The Intel® Core™ microarchitecture is a new foundation for Intel®Core™ Microarchitecture Design Goals 3 Intel® architecture-based desktop, mobile, and mainstream server multi-core processors. This state-of-the-art multi-core optimized Delivering Energy-Efficient Performance 4 and power-efficient microarchitecture is designed to deliver Intel®Core™ Microarchitecture Innovations 5 increased performance and performance-per-watt—thus increasing Intel® Wide Dynamic Execution 6 overall energy efficiency. This new microarchitecture extends the energy efficient philosophy first delivered in Intel's mobile Intel® Intelligent Power Capability 8 microarchitecture found in the Intel® Pentium® M processor, and Intel® Advanced Smart Cache 8 greatly enhances it with many new and leading edge microar- Intel® Smart Memory Access 9 chitectural innovations as well as existing Intel NetBurst® microarchitecture features. What’s more, it incorporates many Intel® Advanced Digital Media Boost 10 new and significant innovations designed to optimize the Intel®Core™ Microarchitecture and Software 11 power, performance, and scalability of multi-core processors. Summary 12 The Intel Core microarchitecture shows Intel’s continued Learn More 12 innovation by delivering both greater energy efficiency Author Biographies 12 and compute capability required for the new workloads and usage models now making their way across computing. With its higher performance and low power, the new Intel Core microarchitecture will be the basis for many new solutions and form factors. In the home, these include higher performing, ultra-quiet, sleek and low-power computer designs, and new advances in more sophisticated, user-friendly entertainment systems.
    [Show full text]
  • Deciding Memory Safety for Single-Pass Heap-Manipulating Programs
    Deciding Memory Safety for Single-Pass Heap-Manipulating Programs UMANG MATHUR, University of Illinois, Urbana-Champaign, USA ADITHYA MURALI, University of Illinois, Urbana-Champaign, USA PAUL KROGMEIER, University of Illinois, Urbana-Champaign, USA P. MADHUSUDAN, University of Illinois, Urbana-Champaign, USA MAHESH VISWANATHAN, University of Illinois, Urbana-Champaign, USA We investigate the decidability of automatic program verification for programs that manipulate heaps, andin particular, decision procedures for proving memory safety for them. We extend recent work that identified a decidable subclass of uninterpreted programs to a class of alias-aware programs that can update maps. We 35 apply this theory to develop verification algorithms for memory safetyÐ determining if a heap-manipulating program that allocates and frees memory locations and manipulates heap pointers does not dereference an unallocated memory location. We show that this problem is decidable when the initial allocated heap forms a forest data-structure and when programs are streaming-coherent, which intuitively restricts programs to make a single pass over a data-structure. Our experimental evaluation on a set of library routines that manipulate forest data-structures shows that common single-pass algorithms on data-structures often fall in the decidable class, and that our decision procedure is efficient in verifying them. CCS Concepts: • Theory of computation → Logic and verification; Automated reasoning. Additional Key Words and Phrases: Memory Safety, Program Verification, Aliasing, Decidability, Uninterpreted Programs, Streaming-Coherence, Forest Data-Structures ACM Reference Format: Umang Mathur, Adithya Murali, Paul Krogmeier, P. Madhusudan, and Mahesh Viswanathan. 2020. Deciding Memory Safety for Single-Pass Heap-Manipulating Programs. Proc. ACM Program.
    [Show full text]
  • System Programming Guide
    Special Edition for CSEDU12 Students Students TOUCH -N-PASS EXAM CRAM GUIDE SERIES SYSTEM PROGRAMMING Prepared By Sharafat Ibn Mollah Mosharraf CSE, DU 12 th Batch (2005-2006) TABLE OF CONTENTS APIS AT A GLANCE ....................................................................................................................................................................... 1 CHAPTER 1: ASSEMBLER, LINKER & LOADER ................................................................................................................................ 4 CHAPTER 2: KERNEL ..................................................................................................................................................................... 9 CHAPTER 3: UNIX ELF FILE FORMAT ............................................................................................................................................ 11 CHAPTER 4: DEVICE DRIVERS ...................................................................................................................................................... 16 CHAPTER 5: INTERRUPT .............................................................................................................................................................. 20 CHAPTER 6: SYSTEM CALL ........................................................................................................................................................... 24 CHAPTER 7: FILE APIS ................................................................................................................................................................
    [Show full text]
  • Sgxometer: Open and Modular Benchmarking for Intel SGX
    SGXoMeter: Open and Modular Benchmarking for Intel SGX Mohammad Mahhouk Nico Weichbrodt Rüdiger Kapitza TU Braunschweig, Germany TU Braunschweig, Germany TU Braunschweig, Germany ABSTRACT mobile devices like phones and tablets. Also, personal computers, Intel’s Software Guard Extensions (SGX) are currently the most laptops and servers can be secured using AMD Secure Encrypted wide-spread commodity trusted execution environment, which Virtualisation [22, 23], and Intel SGX [24, 27]. provides integrity and confidentiality of sensitive code and data. Intel SGX promises with its isolated memory regions, so called Thereby, it offers protection even against privileged attackers and enclaves, both confidentiality and integrity protection of the sen- various forms of physical attacks. As a technology that only be- sitive data and code running inside them against malicious and came available in late 2015, it has received massive interest and privileged software. It also provides local and remote attestation undergone a rapid evolution. Despite first ad-hoc attempts, there is mechanisms [21] to ensure the authenticity and integrity of the so far no standardised approach to benchmark the SGX hardware, running enclaves, adding protection against forging attempts. Thus, its associated environment, and techniques that were designed to the utilisation of SGX in cloud services can considerably reduce harden SGX-based applications. the customers’ reluctance of using them. Furthermore, Intel has re- In this paper, we present SGXoMeter, an open and modular leased a Software Development Kit (SDK)[18] to ease programming framework designed to benchmark different SGX-aware CPUs, with SGX. It introduces wrappers for low-level instructions and `code revisions, SDK versions and extensions to mitigate side- provides a high-level interface that offers multiple functionalities, channel attacks.
    [Show full text]
  • A Superscalar Out-Of-Order X86 Soft Processor for FPGA
    A Superscalar Out-of-Order x86 Soft Processor for FPGA Henry Wong University of Toronto, Intel [email protected] June 5, 2019 Stanford University EE380 1 Hi! ● CPU architect, Intel Hillsboro ● Ph.D., University of Toronto ● Today: x86 OoO processor for FPGA (Ph.D. work) – Motivation – High-level design and results – Microarchitecture details and some circuits 2 FPGA: Field-Programmable Gate Array ● Is a digital circuit (logic gates and wires) ● Is field-programmable (at power-on, not in the fab) ● Pre-fab everything you’ll ever need – 20x area, 20x delay cost – Circuit building blocks are somewhat bigger than logic gates 6-LUT6-LUT 6-LUT6-LUT 3 6-LUT 6-LUT FPGA: Field-Programmable Gate Array ● Is a digital circuit (logic gates and wires) ● Is field-programmable (at power-on, not in the fab) ● Pre-fab everything you’ll ever need – 20x area, 20x delay cost – Circuit building blocks are somewhat bigger than logic gates 6-LUT 6-LUT 6-LUT 6-LUT 4 6-LUT 6-LUT FPGA Soft Processors ● FPGA systems often have software components – Often running on a soft processor ● Need more performance? – Parallel code and hardware accelerators need effort – Less effort if soft processors got faster 5 FPGA Soft Processors ● FPGA systems often have software components – Often running on a soft processor ● Need more performance? – Parallel code and hardware accelerators need effort – Less effort if soft processors got faster 6 FPGA Soft Processors ● FPGA systems often have software components – Often running on a soft processor ● Need more performance? – Parallel
    [Show full text]
  • Intra-Unikernel Isolation with Intel Memory Protection Keys
    Intra-Unikernel Isolation with Intel Memory Protection Keys Mincheol Sung Pierre Olivier∗ Virginia Tech, USA The University of Manchester, United Kingdom [email protected] [email protected] Stefan Lankes Binoy Ravindran RWTH Aachen University, Germany Virginia Tech, USA [email protected] [email protected] Abstract ACM Reference Format: Mincheol Sung, Pierre Olivier, Stefan Lankes, and Binoy Ravin- Unikernels are minimal, single-purpose virtual machines. dran. 2020. Intra-Unikernel Isolation with Intel Memory Protec- This new operating system model promises numerous bene- tion Keys. In 16th ACM SIGPLAN/SIGOPS International Conference fits within many application domains in terms of lightweight- on Virtual Execution Environments (VEE ’20), March 17, 2020, Lau- ness, performance, and security. Although the isolation be- sanne, Switzerland. ACM, New York, NY, USA, 14 pages. https: tween unikernels is generally recognized as strong, there //doi.org/10.1145/3381052.3381326 is no isolation within a unikernel itself. This is due to the use of a single, unprotected address space, a basic principle 1 Introduction of unikernels that provide their lightweightness and perfor- Unikernels have gained attention in the academic research mance benefits. In this paper, we propose a new design that community, offering multiple benefits in terms of improved brings memory isolation inside a unikernel instance while performance, increased security, reduced costs, etc. As a keeping a single address space. We leverage Intel’s Memory result,
    [Show full text]
  • “Sok: Eternal War in Memory”
    “SoK: Eternal War in Memory” Presented by Mengjia Yan MIT 6.888 Fall 2020 Overview • Discuss the paper “SoK: Eternal War in Memory” with concrete examples • Recent progress on memory safety • With a focus on hardware/architecture 2 Motivation • C/C++ is unsafe • EveryboDy runs C/C++ coDe • They surely have exploitable vulnerabilities 3 Low-level Language Basics (C/C++/Assembly) 0x00..0000 • Programmers have more control + Efficient OS memory - Bugs - Programming productivity TEXT (code) Global/Static • Pointers DATA • Address of variables (uint64): index of memory location where variable is stored Heap • Programmers need to do pointer check, e.g. NULL, out-of-bound, use-after-free Stack 0xFF..FFFF 4 Low-level Language Basics 0x00..0000 TEXT (code) Heap Stack 0xFF..FFFF 5 Low-level Language Basics TEXT (code) stack 6 Attacks Code Injection Attack Example TEXT (code) int func (char *str) { Shell code: char buffer[12]; strncpy(buffer, str, len(str)); PUSH “/bin/sh” CALL system stack return 1; } int main() { …. func (input); … } 8 Code Injection Attack TEXT (code) TEXT (code) stack stack buffer Shell code … … Return addr Return addr 9 Attacks 10 Return-Oriented Programming (ROP) int func (char *str) { TEXT (code) TEXT (code) char buffer[12]; strncpy(buffer, str, len(str)); stack stack return 1; } …. int main() { buffer …. … … func (input); Return addr Return addr … } 11 Attacks 12 HeartBleed Vulnerability • Publicly DiscloseD in April 2014 • Bug in the OpenSSL cryptographic software library heartbeat extension • Missing a bound check 13 Attacks
    [Show full text]
  • Assembly Language Programming for X86 Processors Pdf
    Assembly language programming for x86 processors pdf Continue The x86, 7e collection language is for use in undergraduate programming courses in a speaking language and introductory courses in computer systems and computer architecture. This name is also suitable for built-in systems of programmers and engineers, communications specialists, game programmers and graphic programmers. It is recommended to know another programming language, preferably Java, C or C. Written specifically for the 32- and 64-bit Intel/Windows platform, this complete and complete learning of the acoustics language teaches students to write and fine-tune programs at the machine level. This text simplifies and demystiifies concepts that students need to understand before they laugh at more advanced courses in computer architecture and operating systems. Students practice theory using machine-level software, creating an unforgettable experience that gives them confidence to work in any OS/machine-oriented environment. Additional learning and learning tools are available on the author's website in where both teachers and students can access chapter goals, debugging tools, additional files, starting work with the MASM and Visual Studio 2012 tutorial, and more. Learning and Learning Experience This program represents the best learning and learning experience for you and your students. This will help: Teach Effective Design Techniques: Top-Down Demonstration Design Program and Explanation allows students to apply techniques for multiple programming courses. Put Theory into practice: Students will write software at machine level, preparing them to work in any OS/machine oriented environment. Tailor text to fit your course: Instructors can cover additional chapter themes in different order and depth.
    [Show full text]
  • MPTEE: Bringing Flexible and Efficient Memory Protection to Intel
    MPTEE: Bringing Flexible and Efficient Memory Protection to Intel SGX Wenjia Zhao Kangjie Lu* Yong Qi* Saiyu Qi Xi’an Jiaotong University University of Minnesota Xi’an Jiaotong University Xidian University University of Minnesota Abstract code, emerge in today’s market. In particular, Intel has pro- Intel Software Guard eXtensions (SGX), a hardware-based vided SGX in its commodity processors, which supports a se- Trusted Execution Environment (TEE), has become a promis- cure region, namely enclave, to protect the internally loaded ing solution to stopping critical threats such as insider attacks code and data. Given its important and practical protection, and remote exploits. SGX has recently drawn extensive re- SGX has been extensively studied and used in practice. For search in two directions—using it to protect the confidentiality example, SCONE [1] uses it to effectively enhance the secu- and integrity of sensitive data, and protecting itself from at- rity of containers with low overhead. JITGuard [17] leverages tacks. Both the applications and defense mechanisms of SGX it to protect the security-critical just-in-time compiler oper- have a fundamental need—flexible memory protection that ations. SGXCrypter[49] utilizes it to securely unpack and updates memory-page permissions dynamically and enforces execute Windows binaries. There are many other useful appli- the least-privilege principle. Unfortunately, SGX does not pro- cations [35], [34], [31],[6], which confirm the practical and vide such a memory-protection mechanism due to the lack of promising applications of SGX. hardware support and the untrustedness of operating systems. Another line of research is to protect SGX itself from at- This paper proposes MPTEE, a memory-protection mech- tacks.
    [Show full text]
  • Hiding Process Memory Via Anti-Forensic Techniques
    DIGITAL FORENSIC RESEARCH CONFERENCE Hiding Process Memory via Anti-Forensic Techniques By: Frank Block (Friedrich-Alexander Universität Erlangen-Nürnberg (FAU) and ERNW Research GmbH) and Ralph Palutke (Friedrich-Alexander Universität Erlangen-Nürnberg) From the proceedings of The Digital Forensic Research Conference DFRWS USA 2020 July 20 - 24, 2020 DFRWS is dedicated to the sharing of knowledge and ideas about digital forensics research. Ever since it organized the first open workshop devoted to digital forensics in 2001, DFRWS continues to bring academics and practitioners together in an informal environment. As a non-profit, volunteer organization, DFRWS sponsors technical working groups, annual conferences and challenges to help drive the direction of research and development. https://dfrws.org Forensic Science International: Digital Investigation 33 (2020) 301012 Contents lists available at ScienceDirect Forensic Science International: Digital Investigation journal homepage: www.elsevier.com/locate/fsidi DFRWS 2020 USA d Proceedings of the Twentieth Annual DFRWS USA Hiding Process Memory Via Anti-Forensic Techniques Ralph Palutke a, **, 1, Frank Block a, b, *, 1, Patrick Reichenberger a, Dominik Stripeika a a Friedrich-Alexander Universitat€ Erlangen-Nürnberg (FAU), Germany b ERNW Research GmbH, Heidelberg, Germany article info abstract Article history: Nowadays, security practitioners typically use memory acquisition or live forensics to detect and analyze sophisticated malware samples. Subsequently, malware authors began to incorporate anti-forensic techniques that subvert the analysis process by hiding malicious memory areas. Those techniques Keywords: typically modify characteristics, such as access permissions, or place malicious data near legitimate one, Memory subversion in order to prevent the memory from being identified by analysis tools while still remaining accessible.
    [Show full text]
  • SOM-5992 COM Express R3.0 Type 7 Module
    Intel Xeon Processor D-1500 SOM-5992 COM Express R3.0 Type 7 Module NEW Features Intel® Xeon® Processor D-1500 Product Family COM Express R3.0 Basic Module Type 7 pin out 2~16 core processor, with max. TDP 45W Dual-CH DDR4 2400 w/ECC, max. 128GB High speed Ethernet (dual 10GBASE-KR interfaces, one GbE) Abundant expansion. (PCIe x16, PCIe x8, 8 PCIe x1) Supports iManager, Embedded Software APIs and Wise-PaaS/RMM Software APIs: Utilities: Specifications Form Factor COM Express Basic Module Form Factor Pin-out Type COM Express R3.0 Type 7 compatible Xeon Xeon Xeon Xeon Xeon Pentium Pentium Xeon Xeon Pentium CPU D-1577 D-1548 D-1537 D-1528 D-1527 D1517 D1508 D-1559 D-1539 D1519 Base Frequency 1.3 GHz 2.0 GHz 1.7 GHz 1.9 GHz 2.2 GHz 1.6 GHz 2.2 GHz 1.5 GHz 1.6 GHz 1.5 GHz Max Single Core Turbo 2.1 GHz 2.6 GHz 2.3 GHz 2.5 GHz 2.7 GHz 2.2 GHz 2.6 GHz 2.1 GHz 2.2 GHz 2.1 GHz Processor System Frequency Cores 16 8 8 6 4 4 2 12 8 4 LLC 24MB 12MB 12MB 9MB 6MB 6MB 3MB 18MB 12MB 6MB CPU TDP 45W 45W 35W 35W 35W 25W 25W 45W 35W 25W BIOS AMI UEFI 128Mbit Technology DDR4 1866/2133/2400MHz Max. Frequency 2133 MHz 2400 MHz 2133 MHz 2133 MHz 2133 MHz 2133 MHz 1866 MHz 2133 MHz 2133 MHz 2133 MHz Memory ECC Support ECC and non-ECC Max.
    [Show full text]
  • Intel® Xeon® E3-1200 V5 Processor Family
    Intel® Xeon® E3-1200 v5 Processor Family Specification Update May 2020 Revision 033 Reference Number: 333133-033US Intel technologies’ features and benefits depend on system configuration and may require enabled hardware, software or service activation. Learn more at Intel.com, or from the OEM or retailer. No computer system can be absolutely secure. Intel does not assume any liability for lost or stolen data or systems or any damages resulting from such losses. You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein. No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document. The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade. Intel® Turbo Boost Technology requires a PC with a processor with Intel Turbo Boost Technology capability. Intel Turbo Boost Technology performance varies depending on hardware, software and overall system configuration. Check with your PC manufacturer on whether your system delivers Intel Turbo Boost Technology. For more information, see http://www.intel.com/ content/www/us/en/architecture-and-technology/turbo-boost/turbo-boost-technology.html Copies of documents which have an order number and are referenced in this document may be obtained by calling 1-800-548- 4725 or by visiting www.intel.com/design/literature.htm.
    [Show full text]