DOCSLIB.ORG

Sok: Hardware Security Support for Trustworthy Execution

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Sok: Hardware Security Support for Trustworthy Execution SoK: Hardware Security Support for Trustworthy Execution Lianying Zhao1, He Shuang2, Shengjie Xu2, Wei Huang2, Rongzhen Cui2, Pushkar Bettadpur2, and David Lie2 1Carleton Universityz, Ottawa, ON, Canada 2University of Toronto, Toronto, ON, Canada Abstract—In recent years, there have emerged many new hard- contribute to lowering power consumption, which is critical ware mechanisms for improving the security of our computer for resource-constrained devices. systems. Hardware offers many advantages over pure software Furthermore, hardware is the Root of Trust (RoT) [48], as approaches: immutability of mechanisms to software attacks, better execution and power efficiency and a smaller interface it bridges the physical world (where human users reside) and allowing it to better maintain secrets. This has given birth to the digital world (where tasks run as software). To securely a plethora of hardware mechanisms providing trusted execution perform a task or store a secret, the user trusts at least part of environments (TEEs), support for integrity checking and memory the computer hardware. safety and widespread uses of hardware roots of trust. Dedicated hardware security support has seen its prolif- In this paper, we systematize these approaches through the lens eration since the early days of computers. It can take a of abstraction. Abstraction is key to computing systems, and the interface between hardware and software contains many abstrac- straightforward form as discrete components to assist the tions. We find that these abstractions, when poorly designed, can CPU, ranging from the industrial-grade tamper-responding both obscure information that is needed for security enforcement, IBM Cryptocards (e.g., 4758 [37]), Apple’s proprietary secure as well as reveal information that needs to be kept secret, leading enclave processor (SEP [84]) for consumer electronics, to the to vulnerabilities. We summarize such vulnerabilities and discuss more open Trusted Platform Module (TPM), smart cards and several research trends of this area. Index Terms—Hardware Security Primitives, Trusted Execu- other security tokens. Meanwhile, architectural enhancements tion Environments are being introduced to the CPU, as well as its chipset, such as Trusted Execution Environments (TEEs, see Section III), the NX-bit, Intel MPX, MPK, etc. I. INTRODUCTION Driven by demand over the few decades, hardware is being The trustworthiness of a computer system entails that the “patched” cumulatively, as reflected in the increase of the system can correctly fulfill tasks as intended by the user. x86 ISA extensions (according to Baumann [10], hardware This can include user tasks (e.g., applications) and system is becoming the new software). The added complexity and tasks (e.g., a system integrity monitor). Enabling techniques interaction between hardware features has led to numerous for trustworthy execution can be implemented in software, problems, which has motivated us to reflect on the role of hardware or both. For instance, there exist proposals for both hardware in security, and what key features make a good software-based [17] and hardware-based [26] solutions for hardware security mechanism. Control-Flow Integrity (CFI); and likewise, isolation for code Most hardware security features achieve their purpose by can be achieved with either software (e.g., containerization and hiding information or access from an entity, and/or exposing sandboxing) or hardware components [109]. a new/reduced interface to it. For instance, memory protection Nonetheless, there exists a common belief in hardware’s between processes is implemented by virtual memory, which arXiv:1910.04957v1 [cs.CR] 11 Oct 2019 advantages over software in consideration of the following prevents processes from accessing each other’s memory by aspects: 1) Relative immutability. Tampering with hardware is presenting each process with its own virtual address space. non-trivial and requires physical access. This makes hardware The design of virtual memory can be considered an instance support a necessity in mitigation techniques under a strong of “abstraction” [22], [72], which 1) removes or attenuates adversarial model, e.g., rootkit-level threats [76] and hyper- information (by hiding the true implementation of memory) visor threats [66]. 2) Efficiency. Contrary to software that and 2) creates new semantics (such as page tables), which introduces a layer of architectural abstraction, direct hardware are also called “abstractions”. Hence there is a relationship implementation can save redundant processing cycles (e.g., between security and abstraction, which is particularly impor- instruction decode). This allows for better efficiency for cer- tant considering the heavy use of abstractions in computer tain iterative/repetitive operations (e.g., consider how DSPs hardware to separate its implementation from that of the outperform regular CPUs for signal processing). It can further software it runs. We propose to use abstraction (Section II-A) as a lens zThe work was started when the first author was at the University of through which the workings of hardware security support Toronto. and various related issues are examined. Specifically, we find that: 1) beyond the commonly perceived immutability A. Abstraction and efficiency, the properties of hardware security support In computer science, an abstraction can be thought of as a can be explained as mechanisms that hide/expose something; model of a concrete artifact that retains the artifact’s essential 2) certain low-level attacks can be attributed to insufficient properties while eliding details of its implementation [72]. Ab- (SectionIV) or excess (SectionV) abstraction.; and 3) many straction is used heavily across the interface of components to proposals seek to leverage abstractions to increase security reduce the complexity of interactions across those components. (SectionVI) or propose new abstractions to increase the Thus, it is quite natural that abstraction is heavily used at flow of information between hardware and software for better the interface between hardware and software, one of the most security (Section VII). complex interfaces in modern computing. Some key properties While traditionally Trusted Computing [91] emphasizes of an abstraction, which is the interface created when one merely the protection for initial integrity and isolation during abstracts a concrete implementation, are 1) the attenuation of execution, we expand the scope to be more holistic and to information and 2) the creation of new semantics. For example, ensure the eventual correct execution outcome. This includes consider the implementation of modern processor caches: run-time dynamic aspects such as control/data flow integrity of 1) Attenuation of information: Explicit access to and control the running program and secure input/output. We also include of cache memories is hidden, only revealing faster code firmware in the processor, system chipset and peripheral execution. devices, which while they do not execute trusted application 2) New semantics: Caches expose the abstraction of a cache software, are still nonetheless part of the trusted computing line, the size of the cache memory, a mapping function base of much of that software. We examine how hardware- between cache lines and memory and certain instruc- enforced abstraction affects execution within this entire scope. tions (e.g., WBINVD/PREFETCH/CLFLUSH), which in- It is not our intention to focus on improper implementation fluence cache behavior. that fails to properly implement a specification. However, a hardware-related fault may not clearly be attributable to either From this example, we can see that abstraction both hides a design flaw or an implementation error. We will not try to and exposes information. Depending on the components in- draw a boundary (which might be difficult to do in any case). volved, what can be hidden is the existence of resources or metadata. Other examples of hardware-software abstractions Contributions. include the processor ISA, which exposes the semantics of 1) We develop a general model for hardware security sup- an instruction for software to utilize hardware resources, but port based on the notion of abstraction, and examine hides implementation details such as pipelining, out-of-order- various Trusted Execution Environments (TEEs) along execution and speculation. several key properties of the abstractions the TEEs pro- We distinguish abstraction from isolation because while vide. both reduce the flow of information, total isolation as clas- 2) We associate the extent of abstraction (excessive/insuffi- sically defined by Lampson [74] means that there is no infor- cient) with the root cause of a series of vulnerabilities, mation flow at all, while abstraction merely attenuates it, still represented by side channels on one hand and insufficient allowing information to flow over the new semantics it defines. information flow on the other. Namely, when the abstrac- Similarly, virtualization is a particular instance of abstraction, tion specification does not hide all that is supposed to which seeks to maintain one abstraction with a vastly different be hidden, leaked information leads to attacks. On the implementation (i.e. backing RAM memories with disk). other hand, when such leakage is inevitable, too much The security concern with abstraction is that as hardware hiding across components also hinders effective reference has become a critical piece of security for software, hardware monitoring,
Load more

Recommended publications
  • How to Hack a Turned-Off Computer Or Running Unsigned
    HOW TO HACK A TURNED-OFF COMPUTER, OR RUNNING UNSIGNED CODE IN INTEL ME Contents Contents ................................................................................................................................ 2 1. Introduction ...................................................................................................................... 3 1.1. Intel Management Engine 11 overview ............................................................................. 4 1.2. Published vulnerabilities in Intel ME .................................................................................. 5 1.2.1. Ring-3 rootkits.......................................................................................................... 5 1.2.2. Zero-Touch Provisioning ........................................................................................... 5 1.2.3. Silent Bob is Silent .................................................................................................... 5 2. Potential attack vectors ...................................................................................................... 6 2.1. HECI ............................................................................................................................... 6 2.2. Network (vPro only)......................................................................................................... 6 2.3. Hardware attack on SPI interface ..................................................................................... 6 2.4. Internal file system .........................................................................................................
    [Show full text]
  • Deciding Memory Safety for Single-Pass Heap-Manipulating Programs
    Deciding Memory Safety for Single-Pass Heap-Manipulating Programs UMANG MATHUR, University of Illinois, Urbana-Champaign, USA ADITHYA MURALI, University of Illinois, Urbana-Champaign, USA PAUL KROGMEIER, University of Illinois, Urbana-Champaign, USA P. MADHUSUDAN, University of Illinois, Urbana-Champaign, USA MAHESH VISWANATHAN, University of Illinois, Urbana-Champaign, USA We investigate the decidability of automatic program verification for programs that manipulate heaps, andin particular, decision procedures for proving memory safety for them. We extend recent work that identified a decidable subclass of uninterpreted programs to a class of alias-aware programs that can update maps. We 35 apply this theory to develop verification algorithms for memory safetyÐ determining if a heap-manipulating program that allocates and frees memory locations and manipulates heap pointers does not dereference an unallocated memory location. We show that this problem is decidable when the initial allocated heap forms a forest data-structure and when programs are streaming-coherent, which intuitively restricts programs to make a single pass over a data-structure. Our experimental evaluation on a set of library routines that manipulate forest data-structures shows that common single-pass algorithms on data-structures often fall in the decidable class, and that our decision procedure is efficient in verifying them. CCS Concepts: • Theory of computation → Logic and verification; Automated reasoning. Additional Key Words and Phrases: Memory Safety, Program Verification, Aliasing, Decidability, Uninterpreted Programs, Streaming-Coherence, Forest Data-Structures ACM Reference Format: Umang Mathur, Adithya Murali, Paul Krogmeier, P. Madhusudan, and Mahesh Viswanathan. 2020. Deciding Memory Safety for Single-Pass Heap-Manipulating Programs. Proc. ACM Program.
    [Show full text]
  • Intel's SL Enhanced Intel486(TM) Microprocessor Family
    Intel's SL Enhanced Intel486(TM) Microprocessor Family http://www.intel.com/design/intarch/applnots/7014.htm Intel's SL Enhanced Intel486(TM) Microprocessor Family Intel's SL Enhanced Intel486™ Microprocessor Family Technical Backgrounder June 1993 Intel's SL Enhanced Intel486™ Microprocessor Family With the announcement of the SL Enhanced Intel486™ microprocessor family, Intel Corporation brings energy efficiency to its entire line of Intel486™ microprocessors. SL Technology, originally developed for mobile PCs, now provides superior power-management features for desktop computer systems. Such energy-efficient systems will be designed to meet or exceed the Energy Star guidelines set by the Environmental Protection Agency. The EPA's Energy Star program is aimed at reducing power consumption of desktop computer systems, thereby reducing their impact on the environment. In addition, SL Enhanced Intel486™ microprocessors will enable a new class of notebook systems -- high-performance Intel486™ DX2 CPU-based notebooks with color displays that do not sacrifice battery life. The SL Enhanced Intel486™ microprocessor family is available in a complete range of price/performance, package and voltage options. This flexibility allows PC makers to develop products that meet the mobile and desktop needs of all their customers in the mobile and desktop markets, from low-cost, entry-level Intel486™ SX microprocessor-based systems to high-performance, high-end Intel486™ DX2 microprocessor-based systems. Since the SL Technology in SL Enhanced Intel486™ microprocessors is the same as in Intel SL CPUs, computer manufacturers with prior experience developing systems based on existing SL BIOS will be able to incorporate System Management Mode's (SMM) power-management features into new systems.
    [Show full text]
  • Intel X86 Considered Harmful
    Intel x86 considered harmful Joanna Rutkowska October 2015 Intel x86 considered harmful Version: 1.0 1 Contents 1 Introduction5 Trusted, Trustworthy, Secure?......................6 2 The BIOS and boot security8 BIOS as the root of trust. For everything................8 Bad SMM vs. Tails...........................9 How can the BIOS become malicious?.................9 Write-Protecting the flash chip..................... 10 Measuring the firmware: TPM and Static Root of Trust........ 11 A forgotten element: an immutable CRTM............... 12 Intel Boot Guard............................. 13 Problems maintaining long chains of trust............... 14 UEFI Secure Boot?........................... 15 Intel TXT to the rescue!......................... 15 The broken promise of Intel TXT.................... 16 Rescuing TXT: SMM sandboxing with STM.............. 18 The broken promise of an STM?.................... 19 Intel SGX: a next generation TXT?................... 20 Summary of x86 boot (in)security.................... 21 2 Intel x86 considered harmful Contents 3 The peripherals 23 Networking devices & subsystem as attack vectors........... 23 Networking devices as leaking apparatus................ 24 Sandboxing the networking devices................... 24 Keeping networking devices outside of the TCB............ 25 Preventing networking from leaking out data.............. 25 The USB as an attack vector...................... 26 The graphics subsystem......................... 29 The disk controller and storage subsystem............... 30 The audio
    [Show full text]
  • Thinkcentre M58p with Intel AMT White Paper
    ThinkCentre M58p with Intel Active Management Technology First Edition (October 2008) Contents About this document . .v Intel ME configuration. .10 Intel AMT setup and configuration . .13 Driver description . .18 Chapter 1. Introduction to Intel vPro and Intel AMT technology . .1 Chapter 6. Web user interface . .19 Acronyms . .1 Access the Web user interface . .19 Provision the Intel AMT system . .19 Chapter 2. Lenovo ThinkCentre Logging onto the client system . .19 computer equipped with Intel AMT Function in Web user interface . .20 technology . .3 Appendix A. Two examples of Intel Chapter 3. ISV solution introduction . .5 AMT setup and configuration: SMB mode and enterprise mode . .23 Chapter 4. Main features of computers Intel AMT setup and configuration steps - SMB built with Intel AMT . .7 mode . .23 Intel AMT setup and configuration steps - Enterprise mode . .23 Chapter 5. Intel AMT setup and configuration based on Lenovo Appendix B. Default configuration ThinkCentre M58p . .9 values for Intel MEBx . .25 Associated Intel AMT setup and configuration in BIOS . .9 Intel MEBx setup and configuration . .10 Appendix C. Notices . .27 Entering MEBx configuration user interface. .10 Trademarks . .28 Changing Intel ME password . .10 iii iv ThinkCentre M58p with Intel AMT White Paper About this document ® This document provides information about the application of the Intel Active ® ® Management Technology (Intel AMT) for Lenovo ThinkCentre M58p desktop computers. It provides a step-by-step approach to successfully use the Intel AMT technology. This document is intended for trained IT professionals, or those responsible for deploying new computers throughout their organizations. The readers should have basic knowledge of network and computer technology, and be familiar with these terms: TCP/IP, DHCP, IDE, DNS, Subnet Mask, Default Gateway, and Domain Name.
    [Show full text]
  • Intra-Unikernel Isolation with Intel Memory Protection Keys
    Intra-Unikernel Isolation with Intel Memory Protection Keys Mincheol Sung Pierre Olivier∗ Virginia Tech, USA The University of Manchester, United Kingdom [email protected] [email protected] Stefan Lankes Binoy Ravindran RWTH Aachen University, Germany Virginia Tech, USA [email protected] [email protected] Abstract ACM Reference Format: Mincheol Sung, Pierre Olivier, Stefan Lankes, and Binoy Ravin- Unikernels are minimal, single-purpose virtual machines. dran. 2020. Intra-Unikernel Isolation with Intel Memory Protec- This new operating system model promises numerous bene- tion Keys. In 16th ACM SIGPLAN/SIGOPS International Conference fits within many application domains in terms of lightweight- on Virtual Execution Environments (VEE ’20), March 17, 2020, Lau- ness, performance, and security. Although the isolation be- sanne, Switzerland. ACM, New York, NY, USA, 14 pages. https: tween unikernels is generally recognized as strong, there //doi.org/10.1145/3381052.3381326 is no isolation within a unikernel itself. This is due to the use of a single, unprotected address space, a basic principle 1 Introduction of unikernels that provide their lightweightness and perfor- Unikernels have gained attention in the academic research mance benefits. In this paper, we propose a new design that community, offering multiple benefits in terms of improved brings memory isolation inside a unikernel instance while performance, increased security, reduced costs, etc. As a keeping a single address space. We leverage Intel’s Memory result,
    [Show full text]
  • Iocheck: a Framework to Enhance the Security of I/O Devices at Runtime
    IOCheck: A Framework to Enhance the Security of I/O Devices at Runtime Fengwei Zhang Center for Secure Information Systems George Mason University Fairfax, VA 22030 [email protected] Abstract—Securing hardware is the foundation for implement- Management Mode (SMM), a CPU mode in the x86 archi- ing a secure system. However, securing hardware devices remains tecture, to quickly check the integrity of I/O configurations an open research problem. In this paper, we present IOCheck, and firmware. Unlike previous systems [11], [12], IOCheck a framework to enhance the security of I/O devices at runtime. enumerates all of the I/O devices on the motherboard, and It leverages System Management Mode (SMM) to quickly check checks the integrity of their corresponding configurations and the integrity of I/O configurations and firmware. IOCheck does not rely on the operating system and is OS-agnostic. In our firmware. IOCheck does not rely on the operating system, preliminary results, IOCheck takes 4 milliseconds to switch to which significantly reduces the Trust Computing Base (TCB). SMM which introduces low performance overhead. In addition, IOCheck is able to achieve better performance compared to TXT or SVM approaches. For example, the SMM Keywords—Integrity, Firmware, I/O Configurations, SMM switching time is much faster than the late launch method in Flicker [10], [13]. We will demonstrate that IOCheck is able to check the integrity of array of I/O devices including the BIOS, I. INTRODUCTION IOMMU, network card, video card, keyboard, and mouse. With the increasing complexity of hardware devices, Contributions. The purpose of this work is to make the firmware functionality is expanding, exposing new vulner- following contributions: abilities to attackers.
    [Show full text]
  • Intel Management Engine Deep Dive
    Intel Management Engine Deep Dive Peter Bosch About me Peter Bosch ● CS / Astronomy student at Leiden University ● Email : [email protected] ● Twitter: @peterbjornx ● GitHub: peterbjornx ● https://pbx.sh/ About me Previous work: ● CVE-2019-11098: Intel Boot Guard bypass through TOCTOU attack on the SPI bus (Co-discovered by @qrs) Outline 1. Introduction to the Management Engine Operating System 2. The Management Engine as part of the boot process 3. Possibilities for opening up development and security research on the ME Additional materials will be uploaded to https://pbx.sh/ in the days following the talk. About the ME About ME ● Full-featured embedded system within the PCH ○ 80486-derived core ○ 1.5MB SRAM ○ 128K mask ROM ○ Hardware cryptographic engine ○ Multiple sets of fuses. ○ Bus bridges to PCH global fabric ○ Access to host DRAM ○ Access to Ethernet, WLAN ● Responsible for ○ System bringup ○ Manageability ■ KVM ○ Security / DRM ■ Boot Guard ■ fTPM ■ Secure enclave About ME ● Only runs Intel signed firmware ● Sophisticated , custom OS ○ Stored mostly in SPI flash ○ Microkernel ○ Higher level code largely from MINIX ○ Custom filesystems ○ Custom binary format ● Configurable ○ Factory programmed fuses ○ Field programmable fuses ○ SPI Flash ● Extensible ○ Native modules ○ JVM (DAL) Scope of this talk Intel ME version 11 , specifically looking at version 11.0.0.1205 Platforms: ● Sunrise Point (Core 6th, 7th generation SoC, Intel 100, 200 series chipset) ● Lewisburg ( Intel C62x chipsets ) Disclaimer ● I am in no way affiliated with Intel Corporation. ● All information presented here was obtained from public documentation or by reverse engineering firmware extracted from hardware found “in the wild”. ● Because this presentation covers a very broad and scarcely documented subject I can not guarantee accuracy of the contents.
    [Show full text]
  • “Sok: Eternal War in Memory”
    “SoK: Eternal War in Memory” Presented by Mengjia Yan MIT 6.888 Fall 2020 Overview • Discuss the paper “SoK: Eternal War in Memory” with concrete examples • Recent progress on memory safety • With a focus on hardware/architecture 2 Motivation • C/C++ is unsafe • EveryboDy runs C/C++ coDe • They surely have exploitable vulnerabilities 3 Low-level Language Basics (C/C++/Assembly) 0x00..0000 • Programmers have more control + Efficient OS memory - Bugs - Programming productivity TEXT (code) Global/Static • Pointers DATA • Address of variables (uint64): index of memory location where variable is stored Heap • Programmers need to do pointer check, e.g. NULL, out-of-bound, use-after-free Stack 0xFF..FFFF 4 Low-level Language Basics 0x00..0000 TEXT (code) Heap Stack 0xFF..FFFF 5 Low-level Language Basics TEXT (code) stack 6 Attacks Code Injection Attack Example TEXT (code) int func (char *str) { Shell code: char buffer[12]; strncpy(buffer, str, len(str)); PUSH “/bin/sh” CALL system stack return 1; } int main() { …. func (input); … } 8 Code Injection Attack TEXT (code) TEXT (code) stack stack buffer Shell code … … Return addr Return addr 9 Attacks 10 Return-Oriented Programming (ROP) int func (char *str) { TEXT (code) TEXT (code) char buffer[12]; strncpy(buffer, str, len(str)); stack stack return 1; } …. int main() { buffer …. … … func (input); Return addr Return addr … } 11 Attacks 12 HeartBleed Vulnerability • Publicly DiscloseD in April 2014 • Bug in the OpenSSL cryptographic software library heartbeat extension • Missing a bound check 13 Attacks
    [Show full text]
  • AMT Implementation on a UTC RETAIL 3170 POS
    VICTOR , NY – CLEVELAND , OH – SCOTTSDALE , AZ AMT Implementation on a UTC RETAIL 3170 POS Controlling POS systems using Intel AMT Features UTC RETAIL 1 November 19, 2012 11823029A VICTOR , NY – CLEVELAND , OH – SCOTTSDALE , AZ Scope The document was written for use by UTC RETAIL 3170 POS customers to enable the AMT feature in the 3170 hardware. It includes step-by-step instructions to configure a 3170 system allowing AMT to be examined and exercised. Background AMT is a feature of the Intel® vPro™ Technology. From the Intel website: “Intel® vPro™ technology is a set of security and manageability capabilities built into the 3rd generation Intel Core vPro processor family, the Intel Xeon processor E3-1200 product family, Intel® chipsets, and network adapters.” Also, vPro: “Uses Intel® Active Management Technology (Intel® AMT) to facilitate remote management of platform applications, even when the platform is turned off, as long as the platform is connected to a power line and network.” A discussion of vPro is beyond the scope and purpose of this document. Full vPro implementation requires a CPU upgrade from the CPU included in a base 3170 and an IT staff that has the resources to dedicate itself to implementation and use. Every 3170 has the Standard AMT . The security features enabled by AMT require a certain level of Intel CPU, an Intel AMT enabled chipset and an Intel network interface IC. These components all exist in the 3170. To use the Standard AMT , the 3170 must have its power cord plugged into an active power plug, must be connected to an active network and its AMT system must be configured.
    [Show full text]
  • MPTEE: Bringing Flexible and Efficient Memory Protection to Intel
    MPTEE: Bringing Flexible and Efficient Memory Protection to Intel SGX Wenjia Zhao Kangjie Lu* Yong Qi* Saiyu Qi Xi’an Jiaotong University University of Minnesota Xi’an Jiaotong University Xidian University University of Minnesota Abstract code, emerge in today’s market. In particular, Intel has pro- Intel Software Guard eXtensions (SGX), a hardware-based vided SGX in its commodity processors, which supports a se- Trusted Execution Environment (TEE), has become a promis- cure region, namely enclave, to protect the internally loaded ing solution to stopping critical threats such as insider attacks code and data. Given its important and practical protection, and remote exploits. SGX has recently drawn extensive re- SGX has been extensively studied and used in practice. For search in two directions—using it to protect the confidentiality example, SCONE [1] uses it to effectively enhance the secu- and integrity of sensitive data, and protecting itself from at- rity of containers with low overhead. JITGuard [17] leverages tacks. Both the applications and defense mechanisms of SGX it to protect the security-critical just-in-time compiler oper- have a fundamental need—flexible memory protection that ations. SGXCrypter[49] utilizes it to securely unpack and updates memory-page permissions dynamically and enforces execute Windows binaries. There are many other useful appli- the least-privilege principle. Unfortunately, SGX does not pro- cations [35], [34], [31],[6], which confirm the practical and vide such a memory-protection mechanism due to the lack of promising applications of SGX. hardware support and the untrustedness of operating systems. Another line of research is to protect SGX itself from at- This paper proposes MPTEE, a memory-protection mech- tacks.
    [Show full text]
  • Intel® Xeon® E3-1200 V5 Processor Family
    Intel® Xeon® E3-1200 v5 Processor Family Specification Update May 2020 Revision 033 Reference Number: 333133-033US Intel technologies’ features and benefits depend on system configuration and may require enabled hardware, software or service activation. Learn more at Intel.com, or from the OEM or retailer. No computer system can be absolutely secure. Intel does not assume any liability for lost or stolen data or systems or any damages resulting from such losses. You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein. No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document. The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade. Intel® Turbo Boost Technology requires a PC with a processor with Intel Turbo Boost Technology capability. Intel Turbo Boost Technology performance varies depending on hardware, software and overall system configuration. Check with your PC manufacturer on whether your system delivers Intel Turbo Boost Technology. For more information, see http://www.intel.com/ content/www/us/en/architecture-and-technology/turbo-boost/turbo-boost-technology.html Copies of documents which have an order number and are referenced in this document may be obtained by calling 1-800-548- 4725 or by visiting www.intel.com/design/literature.htm.
    [Show full text]