Iocheck: a Framework to Enhance the Security of I/O Devices at Runtime
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Intel's SL Enhanced Intel486(TM) Microprocessor Family
Intel's SL Enhanced Intel486(TM) Microprocessor Family http://www.intel.com/design/intarch/applnots/7014.htm Intel's SL Enhanced Intel486(TM) Microprocessor Family Intel's SL Enhanced Intel486™ Microprocessor Family Technical Backgrounder June 1993 Intel's SL Enhanced Intel486™ Microprocessor Family With the announcement of the SL Enhanced Intel486™ microprocessor family, Intel Corporation brings energy efficiency to its entire line of Intel486™ microprocessors. SL Technology, originally developed for mobile PCs, now provides superior power-management features for desktop computer systems. Such energy-efficient systems will be designed to meet or exceed the Energy Star guidelines set by the Environmental Protection Agency. The EPA's Energy Star program is aimed at reducing power consumption of desktop computer systems, thereby reducing their impact on the environment. In addition, SL Enhanced Intel486™ microprocessors will enable a new class of notebook systems -- high-performance Intel486™ DX2 CPU-based notebooks with color displays that do not sacrifice battery life. The SL Enhanced Intel486™ microprocessor family is available in a complete range of price/performance, package and voltage options. This flexibility allows PC makers to develop products that meet the mobile and desktop needs of all their customers in the mobile and desktop markets, from low-cost, entry-level Intel486™ SX microprocessor-based systems to high-performance, high-end Intel486™ DX2 microprocessor-based systems. Since the SL Technology in SL Enhanced Intel486™ microprocessors is the same as in Intel SL CPUs, computer manufacturers with prior experience developing systems based on existing SL BIOS will be able to incorporate System Management Mode's (SMM) power-management features into new systems. -
CIS 4360 Secure Computer Systems Attacks Against Boot And
CIS 4360 Secure Computer Systems Attacks against Boot and RAM Professor Qiang Zeng Spring 2017 Previous Class • BIOS-MBR: Generation I system boot – What BIOS and MBR are? – How does it boot the system? // Jumping to MBR – How does multi-boot work? // Chain-loading • The limitations of BIOS and MBR – Disk, memory, file system, multi-booting, security, … • UEFI-GPT: Generation II system boot – What UEFI and GPT are? – How does it boot the system? // UEFI boot manager – How does multi-boot work? // separate dirs in ESP CIS 4360 – Secure Computer Systems 2 Limitations of BIOS-MBR • MBR is very limited – Support ~2TB disk only – 4 primary partitions at most (so four OSes at most) – A MBR can store only one boot loader • BIOS is very restrictive – 16-bit processor mode; 1MB memory space (little spare space to accommodate a file system driver) – Blindly executes whatever code on MBR CIS 4360 – Secure Computer Systems 3 UEFI vs. BIOS • Disk partitioning schemes – GPT (GUID Partition Table): part of UEFI spec.; to replace MBR – MBR supports disk size 232 x 512B = 2TB, while UEFI supports much larger disks (264 x 512B = 8,000,000,000 TB) – MBR supports 4 partitions, while GPT supports 128 • Memory space – BIOS: 20-bit addressing; UEFI: 32-bit or 64-bit • Pre-OS environment – BIOS only provides raw disk access, while UEFI supports the FAT file system (so you can use file names to read files) • Booting – BIOS supports boot through boot sectors (MBR and VBR) – UEFI provides a boot partition of hundreds of megabytes (and boot manager and secure boot) CIS 4360 – Secure Computer Systems 4 Previous Class How does dual-boo-ng of Linux and Windows work in UEFI-GPT? Each vendor has a separate directory storing its own boot loader code and configuraon files in the ESP (EFI System Par--on). -
Embedded Intel486™ Processor Hardware Reference Manual
Embedded Intel486™ Processor Hardware Reference Manual Release Date: July 1997 Order Number: 273025-001 The embedded Intel486™ processors may contain design defects known as errata which may cause the products to deviate from published specifications. Currently characterized errata are available on request. Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or oth- erwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel retains the right to make changes to specifications and product descriptions at any time, without notice. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 7641 Mt. Prospect, IL 60056-7641 or call 1-800-879-4683 or visit Intel’s web site at http:\\www.intel.com Copyright © INTEL CORPORATION, July 1997 *Third-party brands and names are the property of their respective owners. CONTENTS CHAPTER 1 GUIDE TO THIS MANUAL 1.1 MANUAL CONTENTS .................................................................................................. -
IOMMU-Resistant DMA Attacks
IOMMU-resistant DMA attacks Gil Kupfer Technion - Computer Science Department - M.Sc. Thesis MSC-2018-21 - 2018 Technion - Computer Science Department - M.Sc. Thesis MSC-2018-21 - 2018 IOMMU-resistant DMA attacks Research Thesis Submitted in partial fulfillment of the requirements for the degree of Master of Science in Computer Science Gil Kupfer Submitted to the Senate of the Technion | Israel Institute of Technology Sivan 5778 Haifa May 2018 Technion - Computer Science Department - M.Sc. Thesis MSC-2018-21 - 2018 Technion - Computer Science Department - M.Sc. Thesis MSC-2018-21 - 2018 This research was carried out under the supervision of Prof. Dan Tsafrir and Dr. Nadav Amit, in the Faculty of Computer Science. Acknowledgements who passed ,ז"ל This work is dedicated to my grandfather, Tuvia Kupfer away during the writing of this work. I would like to thank my wife, Odeya, for helping and supporting when needed. Also, I would like to thank all the friends who have been there. Finally, thanks to my advisors, Prof. Dan Tsafrir and Dr. Nadav Amit, for their help and guidance along the way. The generous financial help of the Technion is gratefully acknowledged. Technion - Computer Science Department - M.Sc. Thesis MSC-2018-21 - 2018 Technion - Computer Science Department - M.Sc. Thesis MSC-2018-21 - 2018 Contents List of Figures Abstract 1 Abbreviations and Notations3 1 Introduction5 2 Background9 2.1 DMA Attacks.................................9 2.1.1 Classic DMA Attacks........................9 2.1.2 IOMMU Protection......................... 10 2.1.3 Circumventing the IOMMU..................... 11 2.2 FireWire.................................... 12 3 Attack Mechanics 15 3.1 Sub-Page Granularity Vulnerability.................... -
Sok: Hardware Security Support for Trustworthy Execution
SoK: Hardware Security Support for Trustworthy Execution Lianying Zhao1, He Shuang2, Shengjie Xu2, Wei Huang2, Rongzhen Cui2, Pushkar Bettadpur2, and David Lie2 1Carleton Universityz, Ottawa, ON, Canada 2University of Toronto, Toronto, ON, Canada Abstract—In recent years, there have emerged many new hard- contribute to lowering power consumption, which is critical ware mechanisms for improving the security of our computer for resource-constrained devices. systems. Hardware offers many advantages over pure software Furthermore, hardware is the Root of Trust (RoT) [48], as approaches: immutability of mechanisms to software attacks, better execution and power efficiency and a smaller interface it bridges the physical world (where human users reside) and allowing it to better maintain secrets. This has given birth to the digital world (where tasks run as software). To securely a plethora of hardware mechanisms providing trusted execution perform a task or store a secret, the user trusts at least part of environments (TEEs), support for integrity checking and memory the computer hardware. safety and widespread uses of hardware roots of trust. Dedicated hardware security support has seen its prolif- In this paper, we systematize these approaches through the lens eration since the early days of computers. It can take a of abstraction. Abstraction is key to computing systems, and the interface between hardware and software contains many abstrac- straightforward form as discrete components to assist the tions. We find that these abstractions, when poorly designed, can CPU, ranging from the industrial-grade tamper-responding both obscure information that is needed for security enforcement, IBM Cryptocards (e.g., 4758 [37]), Apple’s proprietary secure as well as reveal information that needs to be kept secret, leading enclave processor (SEP [84]) for consumer electronics, to the to vulnerabilities. -
Bypassing IOMMU Protection Against I/O Attacks Benoît Morgan, Eric Alata, Vincent Nicomette, Mohamed Kaâniche
Bypassing IOMMU Protection against I/O Attacks Benoît Morgan, Eric Alata, Vincent Nicomette, Mohamed Kaâniche To cite this version: Benoît Morgan, Eric Alata, Vincent Nicomette, Mohamed Kaâniche. Bypassing IOMMU Protection against I/O Attacks. 7th Latin-American Symposium on Dependable Computing (LADC’16), Oct 2016, Cali, Colombia. pp.145-150, 10.1109/LADC.2016.31. hal-01419962 HAL Id: hal-01419962 https://hal.archives-ouvertes.fr/hal-01419962 Submitted on 20 Dec 2016 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. Bypassing IOMMU protection against I/O Attacks Benoˆıt Morgan, Eric´ Alata, Vincent Nicomette, Mohamed Kaanicheˆ LAAS-CNRS, Universite´ de Toulouse, CNRS, INSA, Toulouse, France 7 Avenue du Colonel Roche 31000 Toulouse Email: [email protected], [email protected], [email protected], [email protected] Abstract—Attacks targeting computer systems become more and RAM memory segments. These communication channels and more complex and various. Some of them, so-called I/O raise serious concerns about the security of such architectures, attacks, are performed by malicious peripherals that make read since they open some opportunities to attackers to compromise or write accesses to DRAM memory or to memory embedded in other peripherals, through DMA (Direct Memory Access) the system and hosted applications using some malicious requests. -
SMM) Xeno Kovah && Corey Kallenberg Legbacore, LLC All Materials Are Licensed Under a Creative Commons “Share Alike” License
Advanced x86: BIOS and System Management Mode Internals System Management Mode (SMM) Xeno Kovah && Corey Kallenberg LegbaCore, LLC All materials are licensed under a Creative Commons “Share Alike” license. http://creativecommons.org/licenses/by-sa/3.0/ ABribuEon condiEon: You must indicate that derivave work "Is derived from John BuBerworth & Xeno Kovah’s ’Advanced Intel x86: BIOS and SMM’ class posted at hBp://opensecuritytraining.info/IntroBIOS.html” 2 System Management Mode (SMM) God Mode AcEvate 3 Batteries Not Included! From http://support.amd.com/us/Processor_TechDocs/24593.pdf 4 System Management Mode (SMM) Overview • Most privileged x86 processor operating mode • Runs transparent to the operating system • When the processor enters SMM, all other running tasks are suspended • SMM can be invoked only by a System Management Interrupt (SMI) and exited only by the RSM (resume) instruction • Intended use is to provide an isolated operating environment for – Power/Battery management – Controlling system hardware – Running proprietary OEM code – etc. (anything that should run privileged and uninterrupted) 5 System Management Mode (SMM) Overview • The code that executes in SMM (called the SMI handler) is instantiated from the BIOS flash • Protecting SMM is a matter of protecting both the active (running) SMRAM address space but also protecting the flash chip from which it is derived – Protect itself (SMBASE (location), SMRAM Permissions) – Write-Protect Flash • So far in our research, only about 5% of SMRAM configurations were directly unlocked and vulnerable to overwrite • However, since > 50% of the BIOS flash chips we've seen are vulnerable, that means > 50% of SMRAM will follow suit 6 System Management Interrupt (SMI) • SMM can only be invoked by signaling a System Management Interrupt (SMI) • SMI’s can be received via the SMI# pin on the processor or through the APIC bus • SMI’s cannot be masked like normal interrupts (e.g. -
Hardware-Assisted Rootkits: Abusing Performance Counters on the ARM and X86 Architectures
Hardware-Assisted Rootkits: Abusing Performance Counters on the ARM and x86 Architectures Matt Spisak Endgame, Inc. [email protected] Abstract the OS. With KPP in place, attackers are often forced to move malicious code to less privileged user-mode, to ele- In this paper, a novel hardware-assisted rootkit is intro- vate privileges enabling a hypervisor or TrustZone based duced, which leverages the performance monitoring unit rootkit, or to become more creative in their approach to (PMU) of a CPU. By configuring hardware performance achieving a kernel mode rootkit. counters to count specific architectural events, this re- Early advances in rootkit design focused on low-level search effort proves it is possible to transparently trap hooks to system calls and interrupts within the kernel. system calls and other interrupts driven entirely by the With the introduction of hardware virtualization exten- PMU. This offers an attacker the opportunity to redirect sions, hypervisor based rootkits became a popular area control flow to malicious code without requiring modifi- of study allowing malicious code to run underneath a cations to a kernel image. guest operating system [4, 5]. Another class of OS ag- The approach is demonstrated as a kernel-mode nostic rootkits also emerged that run in System Manage- rootkit on both the ARM and Intel x86-64 architectures ment Mode (SMM) on x86 [6] or within ARM Trust- that is capable of intercepting system calls while evad- Zone [7]. The latter two categories, which leverage vir- ing current kernel patch protection implementations such tualization extensions, SMM on x86, and security exten- as PatchGuard. -
80486DX2-66-Intel-Datasheet-7086155.Pdf
Distributed by: www.Jameco.com ✦ 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. EMBEDDED IntelDX2™ PROCESSOR ■ Integrated Floating-Point Unit ■ SL Technology ■ Speed-Multiplying Technology ■ Data Bus Parity Generation and Checking ■ 32-Bit RISC Technology Core ■ Boundary Scan (JTAG) ■ 8-Kbyte Write-Through Cache ■ 3.3-Volt Processor, 50 MHz, 25 MHz CLK ■ Four Internal Write Buffers — 208-Lead Shrink Quad Flat Pack (SQFP) ■ ■ Burst Bus Cycles 5-Volt Processor, 66 MHz, 33 MHz CLK — 168-Pin Pin Grid Array (PGA) ■ Dynamic Bus Sizing for 8- and 16-bit Data Bus Devices ■ Binary Compatible with Large Software Base 64-Bit Interunit Transfer Bus 32-Bit Data Bus Core CLK Clock Clock 32-Bit Data Bus Multiplier Linear Address 32 PCD PWT Bus Interface Barrel Base/ Segmentation 2 A31-A2 Shifter Index Unit Paging Cache Unit 32 Address BE3#- BE0# Bus Unit 20 Drivers Register 32 Descriptor File Registers Physical 8 Kbyte Write Buffers Address 32 4 x 32 Translation Cache ALU Limit and D31-D0 Attribute PLA Lookaside Data Bus Buffer 32 Transceivers Bus Control ADS# W/R# D/C# M/IO# PCD PWT RDY# LOCK# 128 PLOCK# BOFF# A20M# Displacement Bus BREQ HOLD HLDA RESET SRESET INTR 32 NMI SMI# SMIACT# Prefetcher FERR# IGNNE# Micro- STPCLK# Instruction Request Sequencer 32-Byte Code BRDY# BLAST# Queue Burst Bus Code Control Stream 2x16 Bytes Floating Control & Instruction Bus Size BS16# BS8# 24 Point Unit Protection Decode Control Test Unit Cache KEN# FLUSH# Floating Decoded AHOLD EADS# Control Instruction Control Point Path Register File ROM Parity DP3-DP0 PCHK# Generation and Control Boundary TCK TMS TDI TD0 Scan Control A3223-01 Figure 1. -
PERFORMANCE IMPLICATIONS of SYSTEM MANAGEMENT MODE Brian Delgado†, Karen L
In Proceedings of the IEEE International Symposium on Workload Characterization (IISWC), Sept. 2013 (c) IEEE 2013 PERFORMANCE IMPLICATIONS OF SYSTEM MANAGEMENT MODE Brian Delgado†, Karen L. Karavanic Portland State University bdelgado, [email protected] ABSTRACT [4] dramatically change expectations over its use. Since System Management Mode (SMM) is a special x86 processor SMM completely pauses host software execution for the mode that privileged software such as kernels or hypervisors duration of its work and the time required for these new cannot access or interrupt. Previously, it has been assumed usages exceeds common SMI durations, there are clear that time spent in SMM would be relatively small and performance concerns. In recent years, applications have therefore its side effects on privileged software were moved from running on native operating systems where unimportant; recently, researchers have proposed uses, such they were impacted by other processes as well as the as security-related checks, that would greatly increase the operating system to running within virtualized amount of runtime spent in this mode. We present the environments which added virtualization-level impacts. results of a detailed performance study to characterize the SMM RIMMs would cause another source of impact on performance impacts of SMM, using measurement infrastructure we have developed. Our study includes applications as well as the virtualized environments on impact to application, system, and hypervisor. We show which they run. Applications running under hypervisors there can be clear negative effects from prolonged watched by an SMM RIMM would experience the preemptions. However, if SMM duration is kept within combined impacts of each layer. -
Co-Processor-Based Behavior Monitoring
Co-processor-based Behavior Monitoring: Application to the Detection of Attacks Against the System Management Mode Ronny Chevalier, Maugan Villatel, David Plaquin, Guillaume Hiet To cite this version: Ronny Chevalier, Maugan Villatel, David Plaquin, Guillaume Hiet. Co-processor-based Behavior Monitoring: Application to the Detection of Attacks Against the System Management Mode. ACSAC 2017 - 33rd Annual Computer Security Applications Conference, Dec 2017, Orlando, United States. pp.399-411, 10.1145/3134600.3134622. hal-01634566 HAL Id: hal-01634566 https://hal.inria.fr/hal-01634566 Submitted on 6 Dec 2017 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. Co-processor-based Behavior Monitoring: Application to the Detection of Attacks Against the System Management Mode Ronny Chevalier Maugan Villatel HP Labs HP Labs [email protected] [email protected] David Plaquin Guillaume Hiet HP Labs CentraleSupélec [email protected] [email protected] ABSTRACT 1 INTRODUCTION Highly privileged software, such as firmware, is an attractive target Computers often relies on low-level software, like the kernel of for attackers. Thus, BIOS vendors use cryptographic signatures to an Operating System (OS) or software embedded in the hardware, ensure firmware integrity at boot time. -
Chapter 3 Basic Execution Environment
CHAPTER 3 BASIC EXECUTION ENVIRONMENT This chapter describes the basic execution environment of an Intel 64 or IA-32 processor as seen by assembly- language programmers. It describes how the processor executes instructions and how it stores and manipulates data. The execution environment described here includes memory (the address space), general-purpose data registers, segment registers, the flag register, and the instruction pointer register. 3.1 MODES OF OPERATION The IA-32 architecture supports three basic operating modes: protected mode, real-address mode, and system management mode. The operating mode determines which instructions and architectural features are accessible: • Protected mode — This mode is the native state of the processor. Among the capabilities of protected mode is the ability to directly execute “real-address mode” 8086 software in a protected, multi-tasking environment. This feature is called virtual-8086 mode, although it is not actually a processor mode. Virtual-8086 mode is actually a protected mode attribute that can be enabled for any task. • Real-address mode — This mode implements the programming environment of the Intel 8086 processor with extensions (such as the ability to switch to protected or system management mode). The processor is placed in real-address mode following power-up or a reset. • System management mode (SMM) — This mode provides an operating system or executive with a transparent mechanism for implementing platform-specific functions such as power management and system security. The processor enters SMM when the external SMM interrupt pin (SMI#) is activated or an SMI is received from the advanced programmable interrupt controller (API C). In SMM, the processor switches to a separate address space while saving the basic context of the currently running program or task.