DOCSLIB.ORG

Bypassing IOMMU Protection Against I/O Attacks Benoît Morgan, Eric Alata, Vincent Nicomette, Mohamed Kaâniche

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Bypassing IOMMU Protection Against I/O Attacks Benoît Morgan, Eric Alata, Vincent Nicomette, Mohamed Kaâniche Bypassing IOMMU Protection against I/O Attacks Benoît Morgan, Eric Alata, Vincent Nicomette, Mohamed Kaâniche To cite this version: Benoît Morgan, Eric Alata, Vincent Nicomette, Mohamed Kaâniche. Bypassing IOMMU Protection against I/O Attacks. 7th Latin-American Symposium on Dependable Computing (LADC’16), Oct 2016, Cali, Colombia. pp.145-150, 10.1109/LADC.2016.31. hal-01419962 HAL Id: hal-01419962 https://hal.archives-ouvertes.fr/hal-01419962 Submitted on 20 Dec 2016 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. Bypassing IOMMU protection against I/O Attacks Benoˆıt Morgan, Eric´ Alata, Vincent Nicomette, Mohamed Kaanicheˆ LAAS-CNRS, Universite´ de Toulouse, CNRS, INSA, Toulouse, France 7 Avenue du Colonel Roche 31000 Toulouse Email: [email protected], [email protected], [email protected], [email protected] Abstract—Attacks targeting computer systems become more and RAM memory segments. These communication channels and more complex and various. Some of them, so-called I/O raise serious concerns about the security of such architectures, attacks, are performed by malicious peripherals that make read since they open some opportunities to attackers to compromise or write accesses to DRAM memory or to memory embedded in other peripherals, through DMA (Direct Memory Access) the system and hosted applications using some malicious requests. Some protection mechanisms to face these attacks exist peripherals. These attacks are so-called I/O attacks. To cope and have been implemented for several years now in modern with such attacks, some hardware protection components, such architectures. A typical example is the IOMMU proposed by as the IOMMU, from Intel, are included in modern computers. Intel. However, such mechanisms are not necessarily properly This experience report paper is aimed at analyzing the security configured and used by the firmware and the operating system. This experimental paper describes a design weakness that we dis- of such protection component. In particular, it is shown, covered in the configuration of an IOMMU by the Intel IOMMU that even if this component has been introduced 10 years Linux driver and a possible exploitation scenario that would ago, some serious security concerns may be raised about its allow a malicious peripheral to bypass the underlying protection actual efficiency to prevent malicious I/O attacks due to some mechanism. The exploitation scenario is implemented with a design weaknesses in its configuration. Briefly, the weakness is PCI Express peripheral FPGA, based on Intel specifications and Linux source code analysis. related to the fact that the configuration tables of the IOMMU are initialized in a DRAM region which is not protected from I. INTRODUCTION DMA accesses. A malicious peripheral may benefit from this The evolution and sophistication of recent hardware archi- weakness to modify these tables in memory just before the tectures result from the continuously increasing requirements hardware setup of the IOMMU. for software applications in terms of functionalites, processing This paper is organized as follows. The following two power and speed as well as in terms of memory, storage sections describe fundamental components of the architecture, capacities and communication possibilities. Today, software involved in the identified design weakness: Section II presents applications executed by microprocessors, like video games or some basic technical background about PCI Express bus and electronic systems simulators need high performance levels, communications that are used to perform DMA accesses while need to communicate over different networks and require Section III presents the IOMMU component itself as well services which cannot be provided anymore by the processor as some of its internals, that are necessary for the reader to itself, like persistant external data storage or audio digital to understand the vulnerability as well as its potential exploita- analog encoding, etc. All these services are today provided by tion. Section IV briefly presents some examples of I/O attacks dedicated and independent hardware units which are external discovered so far. Section V describes the vulnerability that we to the processor. These units, called peripherals, need to discovered in the configuration of the IOMMU and a scenario communicate with the processor for system configuration and illustrating the possible exploitation of such vulnerability. data sharing. Section VI proposes some countermeasures to cope with this Before the complexification of microarchitectures, early vulnerability. Finally, Section VII concludes and discusses personal computers and their peripherals were mostly de- future work. signed and built by the same compagny. The peripherals themselves used to be much less complex than today (mi- II. TECHNICAL BACKGROUND crocode, firmwares, etc.). Processor manufacturers used to This section presents basic technical background concepts trust the peripherals. However, with the increasing demand for related to PCI Express bus and communications, which are higher performance levels and hardware services, manufactur- useful to understand the rest of the paper. ers improved input/output possibilities. They even specified normalized communication buses to allow tier manufacturers A. PCI Express bus to complement bare architectures with complex peripherals. Several different bus specifications like Industry Standard Then, to relieve the host processor from performing certain Architecture (ISA) or Peripheral Component Interconnect data copies and operation, DMA cycles have been added to (PCI) have been implemented to support the communications these external buses, allowing as a consequence peripherals between the CPU and the peripherals. Today, the PCI Express to perform read/write accesses to a set of other peripherals bus is used in most personal computers or servers. CPU host to know which ids and memory ranges are responsible for downstream (Figure 2). Bridge Host bridge root port RAM CPU Endpoint Endpoint Host bridge {0x0; 0xfff} [00:00.0] RAM Root Complex Endpoint Endpoint DMAR 0 DMAR 2 [01:00.0] [00.01.0] Switch {0x1000; 0x1fff} DMAR 1 {0x2000; 0x2fff} Bridge upstream port {01:yy.z} {0x1000; 0x1fff} RAM data Root Complex RAM read command Bridge {02-03:yy.z} Read(0xffc, 03:00.0) downstream port {0x3000; 0x4fff} Switch Read completion (03:00.0, 00:00.0) PCI Express {addr1; addr2} Device address range link Downstream port {xx:yy.z} Bridge id range Endpoint Endpoint Upstream port PCI Express link {02:yy.z} {03:yy.z} {0x3000; 0x3fff} {0x4000; 0x4fff} Fig. 1. Logical view of a typical PCI Express compliant architecture Endpoint Endpoint [02:00.0] [03:00.0] {0x3000; 0x3fff}{0x4000; 0x4fff} PCI Express devices are connected with ports and links. A Fig. 2. Memory read message routing port connected to a child device is called a downstream port, while a port connected to a parent device is called an upstream At boot time, the devices are not configured (they do not port. There are three main types of PCI Express devices. The know their own identifier). Indeed, the manufacturer can not root complex, root of the bus hierarchy, is connected to the know the bus on which the device will be plugged. However, CPU thanks to the host bridge and to first level PCI Express when the BIOS ”Basic Input Output Systems” looks for all children devices. These devices can be endpoints (so-called available devices (using the simple assembler instruction mov peripherals in the paper) and bridges (Figure 1). A bridge from the PCI Express space mapped in memory), each mem- connects two different logical bus domains with an upstream ory access is processed by the host bridge. The host bridge and a downstream port. Finally, a switch is a collection of then translates this access into a PCI Express configuration bridges. We note that the root complex can host peripherals request which is routed to the corresponding bus. In particular, and bridges. These bridges possess downstream ports only, this request contains the identifier of the contacted device. So, which are called root ports. if this device is available in the system, it receives this request and then knows its identifier. This step is important to allow B. Communications a device to communicate. Each PCI Express device is identified with a PCI logical bus, PCI Express peripherals are able, through DMA requests, device and function identifier (id), noted bus:dev.fun. This to have access to other peripheral memories and to the main identification is used to route PCI Express messages between RAM, even in the kernel memory regions, without any control devices. of the processor. This raises a major concern from the security A PCI Express message type is defined for every kind of point of view if the peripheral behavior can be controlled by an transactions, like configuration or memory read and write for attacker. To mitigate this threat, Intel has developed a hardware example. A transaction can be posted, which means that it does component to filter PCI Express messages. This component, not expect a reply from the requested device, also it can be called IOMMU, is presented in the next section. non-posted where a reply, called the completion, is needed. For example a memory write is posted because the sender III. IOMMU INTERNALS – DMA REMAPPING doesn’t expect any response. At the opposite, a memory read IOMMUs are designed to virtualize the memory space of is non-posted and leads to the transmission of a memory read the peripherals. An architecture can contain several IOMMUs, completion by the receiver. each one being dedicated to a subset of installed devices The receiver of a message is either identified by its identifier (Figure 2).
Load more

Recommended publications
  • CIS 4360 Secure Computer Systems Attacks Against Boot And
    CIS 4360 Secure Computer Systems Attacks against Boot and RAM Professor Qiang Zeng Spring 2017 Previous Class • BIOS-MBR: Generation I system boot – What BIOS and MBR are? – How does it boot the system? // Jumping to MBR – How does multi-boot work? // Chain-loading • The limitations of BIOS and MBR – Disk, memory, file system, multi-booting, security, … • UEFI-GPT: Generation II system boot – What UEFI and GPT are? – How does it boot the system? // UEFI boot manager – How does multi-boot work? // separate dirs in ESP CIS 4360 – Secure Computer Systems 2 Limitations of BIOS-MBR • MBR is very limited – Support ~2TB disk only – 4 primary partitions at most (so four OSes at most) – A MBR can store only one boot loader • BIOS is very restrictive – 16-bit processor mode; 1MB memory space (little spare space to accommodate a file system driver) – Blindly executes whatever code on MBR CIS 4360 – Secure Computer Systems 3 UEFI vs. BIOS • Disk partitioning schemes – GPT (GUID Partition Table): part of UEFI spec.; to replace MBR – MBR supports disk size 232 x 512B = 2TB, while UEFI supports much larger disks (264 x 512B ＝ 8,000,000,000 TB) – MBR supports 4 partitions, while GPT supports 128 • Memory space – BIOS: 20-bit addressing; UEFI: 32-bit or 64-bit • Pre-OS environment – BIOS only provides raw disk access, while UEFI supports the FAT file system (so you can use file names to read files) • Booting – BIOS supports boot through boot sectors (MBR and VBR) – UEFI provides a boot partition of hundreds of megabytes (and boot manager and secure boot) CIS 4360 – Secure Computer Systems 4 Previous Class How does dual-boo-ng of Linux and Windows work in UEFI-GPT? Each vendor has a separate directory storing its own boot loader code and configuraon files in the ESP (EFI System Par--on).
    [Show full text]
  • Iocheck: a Framework to Enhance the Security of I/O Devices at Runtime
    IOCheck: A Framework to Enhance the Security of I/O Devices at Runtime Fengwei Zhang Center for Secure Information Systems George Mason University Fairfax, VA 22030 [email protected] Abstract—Securing hardware is the foundation for implement- Management Mode (SMM), a CPU mode in the x86 archi- ing a secure system. However, securing hardware devices remains tecture, to quickly check the integrity of I/O configurations an open research problem. In this paper, we present IOCheck, and firmware. Unlike previous systems [11], [12], IOCheck a framework to enhance the security of I/O devices at runtime. enumerates all of the I/O devices on the motherboard, and It leverages System Management Mode (SMM) to quickly check checks the integrity of their corresponding configurations and the integrity of I/O configurations and firmware. IOCheck does not rely on the operating system and is OS-agnostic. In our firmware. IOCheck does not rely on the operating system, preliminary results, IOCheck takes 4 milliseconds to switch to which significantly reduces the Trust Computing Base (TCB). SMM which introduces low performance overhead. In addition, IOCheck is able to achieve better performance compared to TXT or SVM approaches. For example, the SMM Keywords—Integrity, Firmware, I/O Configurations, SMM switching time is much faster than the late launch method in Flicker [10], [13]. We will demonstrate that IOCheck is able to check the integrity of array of I/O devices including the BIOS, I. INTRODUCTION IOMMU, network card, video card, keyboard, and mouse. With the increasing complexity of hardware devices, Contributions. The purpose of this work is to make the firmware functionality is expanding, exposing new vulner- following contributions: abilities to attackers.
    [Show full text]
  • IOMMU-Resistant DMA Attacks
    IOMMU-resistant DMA attacks Gil Kupfer Technion - Computer Science Department - M.Sc. Thesis MSC-2018-21 - 2018 Technion - Computer Science Department - M.Sc. Thesis MSC-2018-21 - 2018 IOMMU-resistant DMA attacks Research Thesis Submitted in partial fulfillment of the requirements for the degree of Master of Science in Computer Science Gil Kupfer Submitted to the Senate of the Technion | Israel Institute of Technology Sivan 5778 Haifa May 2018 Technion - Computer Science Department - M.Sc. Thesis MSC-2018-21 - 2018 Technion - Computer Science Department - M.Sc. Thesis MSC-2018-21 - 2018 This research was carried out under the supervision of Prof. Dan Tsafrir and Dr. Nadav Amit, in the Faculty of Computer Science. Acknowledgements who passed ,ז"ל This work is dedicated to my grandfather, Tuvia Kupfer away during the writing of this work. I would like to thank my wife, Odeya, for helping and supporting when needed. Also, I would like to thank all the friends who have been there. Finally, thanks to my advisors, Prof. Dan Tsafrir and Dr. Nadav Amit, for their help and guidance along the way. The generous financial help of the Technion is gratefully acknowledged. Technion - Computer Science Department - M.Sc. Thesis MSC-2018-21 - 2018 Technion - Computer Science Department - M.Sc. Thesis MSC-2018-21 - 2018 Contents List of Figures Abstract 1 Abbreviations and Notations3 1 Introduction5 2 Background9 2.1 DMA Attacks.................................9 2.1.1 Classic DMA Attacks........................9 2.1.2 IOMMU Protection......................... 10 2.1.3 Circumventing the IOMMU..................... 11 2.2 FireWire.................................... 12 3 Attack Mechanics 15 3.1 Sub-Page Granularity Vulnerability....................
    [Show full text]
  • Protecting Data In-Use from Firmware and Physical Attacks
    Protecting Data In-Use from Firmware and Physical Attacks Stephen Weis PrivateCore Palo Alto, CA ABSTRACT 2. PHYSICAL ATTACKS Defending computers from unauthorized physical access, ma- It is generally understood that physical access to an x86 licious hardware devices, or other low-level attacks has proven platform can completely compromise software security. His- extremely challenging. The risks from these attacks are torically, physical security controls such as cages, cameras, exacerbated in cloud-computing environments, where users and locks have been employed to prevent or detect physical lack physical control over servers executing their workloads. access. Yet with adoption of outsourced infrastructure and This paper reviews several firmware and physical attacks cloud computing, x86 platforms are increasingly run outside against x86 platforms, including bootkits, "cold booting", the physical control of the software owner. and malicious devices. We discuss several existing tools and This section briefly summarizes several well-known phys- technologies that can mitigate these risk such as Trusted ical attack vectors against x86 platforms, including DMA Execution Technology (TXT) and main memory encryption. and physical memory extraction. We will also discuss upcoming technologies that may help protect against firmware and physical threats. 2.1 Direct Memory Access By design, x86 architectures provide direct memory access (DMA) from hardware subsystems to main memory without 1. INTRODUCTION invoking the CPU. DMA is generally used to improve per- formance. For example, DMA allows disk, network, and In 2013, journalists revealed that the United States Na- graphics devices to read and write data directly to memory tional Security Agency's (NSA) Tailored Access Operations without incurring CPU cycles.
    [Show full text]
  • IOMMU Protection Against I/O Attacks: a Vulnerability and a Proof-Of-Concept Benoît Morgan, Eric Alata, Vincent Nicomette, Mohamed Kaâniche
    IOMMU protection against I/O attacks: A vulnerability and a proof-of-concept Benoît Morgan, Eric Alata, Vincent Nicomette, Mohamed Kaâniche To cite this version: Benoît Morgan, Eric Alata, Vincent Nicomette, Mohamed Kaâniche. IOMMU protection against I/O attacks: A vulnerability and a proof-of-concept. Journal of the Brazilian Computer Society, Springer Verlag, 2018, 24, pp.Article number: 2. 10.1186/s13173-017-0066-7. hal-02877143 HAL Id: hal-02877143 https://hal.archives-ouvertes.fr/hal-02877143 Submitted on 22 Jun 2020 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. Morgan et al. RESEARCH IOMMU protection against I/O attacks: A vulnerability and a proof-of-concept Beno^ıtMorgan1,2*, Eric´ Alata1,2, Vincent Nicomette1,2 and Mohamed Ka^aniche1 performance levels and hardware services, more so- phisticated architectures have emerged with multiple input/output communication channels. In particular, normalized communication buses have been specified Abstract to allow tier manufacturers to complement bare ar- I/O attacks have received increasing attention chitectures with complex peripherals. Then, to relieve during the last decade. These attacks are the host processor from performing certain data copies performed by malicious peripherals that make read and operations, DMA cycles have been added to these or write accesses to DRAM memory or to memory external buses, allowing peripherals to perform read- embedded in other peripherals, through DMA /write accesses to other peripherals and RAM memory (Direct Memory Access) requests.
    [Show full text]
  • Stealthy System Virtualization with Minimal Target Impact Through DMA-Based Hypervisor Injection
    HyperLeech: Stealthy System Virtualization with Minimal Target Impact through DMA-Based Hypervisor Injection Ralph Palutke Simon Ruderich Friedrich-Alexander-Universität Erlangen Friedrich-Alexander-Universität Erlangen Matthias Wild Felix C. Freiling Friedrich-Alexander-Universität Erlangen Friedrich-Alexander-Universität Erlangen Abstract to alter important kernel structures, as memory forensics and live analysis often rely on their integrity [5, 22, 59]. In ad- In the recent past, malware began to incorporate anti-forensic dition, Zhang et al. [68] bypass state-of-art memory acquisi- techniques in order to hinder analysts from gaining mean- tion by manipulating the physical address layout on x86 plat- ingful results. Consequently, methods that allow the stealthy forms. Besides attacks that target software-based approaches, analysis of a system became increasingly important. Rutkowska [53] demonstrated a method to attack Direct Ac- HyperLeech In this paper, we present , the first approach cess Memory (DMA)-based acquisition by remapping parts which uses DMA to stealthily inject a thin hypervisor into of the Memory Mapped I/O (MMIO) address space. Zdzi- the memory of a target host, transparently shifting its oper- chowski et al. [66] listed further approaches in a recent meta ation into a hardware-accelerated virtual machine. For the study, surveying the landscape of modern anti-forensics. Ap- code injection, we make use of external PCILeech hardware proaches like these indicate the necessity for novel analysis to enable DMA to the target
    [Show full text]
  • True IOMMU Protection from DMA Attacks
    True IOMMU Protection from DMA Attacks: When Copy Is Faster Than Zero Copy Alex Markuze Adam Morrison Dan Tsafrir Hello, my name is Alex and I would like to present today our work from this years at ASPLOS, this work was done by me and my advisors Adam Morrison and Dan Tsafrir from the Technion, “True IOMMU Protection from DMA Attacks, a.k.a When Copy is Faster than Zero Copy” (0:20) DMA &KTGEV/GOQT[#EEGUU /CKP/GOQT[ Lets start with DMA. DMA, or direct memory access is the ability of an attached device to access the main memory without involving the cpu. DMA capable devices are shown on the screen, Devices like GPUs, SSDs and Network Interface Cards have their own cpus and their own code and none of it is controlled by the operating system.(0:45) Problem: DMA Attacks How to develop a rootkit for Broadcom NetExtreme network cards (ESEC 2011) Someone (probably the NSA) has been hiding viruses in hard drive firmware (Kaspersky 2015) This ability to access memory directly, also allows a malicious device to read or modify sensitive data. We call this a DMA attack. This is far from being fiction, for example, one detailed instruction can be easily found on the internet and it describes in great detail how someone could get a malicious code running on a popular NIC, even from remote. A nic which you may probably find in your own university labs. Also recently, Kaspersky Labs have identified attacks in the wild that reprogrammed hard disk firmware so that the drive could reintroduce malware even if the Hardisk got formatted.
    [Show full text]
  • Data Leakage Prevention for Unmodified Programs on ARM Devices
    CryptMe: Data Leakage Prevention for Unmodified Programs on ARM Devices Chen Cao1, Le Guan1, Ning Zhang2, Neng Gao3, Jingqiang Lin3, Bo Luo4, Peng Liu1, Ji Xiang3, and Wenjing Lou2 1 The Pennsylvania State University 2 Virginia Polytechnic Institute and State University 3 Institute of Information Engineering, CAS 4 The University of Kansas fcuc96,lug14,[email protected],fningzh,[email protected], fgaoneng,linjingqiang,[email protected],[email protected] Abstract. Sensitive data (e.g., passwords, health data and private videos) can be leaked due to many reasons, including (1) the misuse of legitimate operating system (OS) functions such as core dump, swap and hibernation, and (2) physical attacks to the DRAM chip such as cold-boot attacks and DMA attacks. While existing software-based mem- ory encryption is effective in defeating physical attacks, none of them can prevent a legitimate OS function from accidentally leaking sensi- tive data in the memory. This paper introduces CryptMe that integrates memory encryption and ARM TrustZone-based memory access controls to protect sensitive data against both attacks. CryptMe essentially ex- tends the Linux kernel with the ability to accommodate the execution of unmodified programs in an isolated execution domain (to defeat OS function misuse), and at the same time transparently encrypt sensitive data appeared in the DRAM chip (to defeat physical attacks). We have conducted extensive experiments on our prototype implementation. The evaluation results show the efficiency and added security of our design. 1 Introduction Driven by the pressures of time-to-market and development cost, Internet-of- Things (IoT) manufacturers tend to build their systems atop existing open- source software stacks, notably the Linux kernel.
    [Show full text]
  • Secure Processor SECURE PROCESSOR Hardware-Supported Security
    2015/6/2 http://LoCCS.sjtu.edu.cn LoCCS @ SJTU December 17, 2012 Secure Processor SECURE PROCESSOR Hardware-supported security THREAT MODEL 攻击模型 • Physical attack on: • Memory • Bus • 方法： • Cold-boot attack • DMA attack • 探针监听 • 温度、电磁攻击等 Cold-boot attack COLD-BOOT ATTACK • Lest We Rember: COLD BOOT ATTACKS ON ENCRYPTION KEYS. 2008, Princeton University • 年年初,普林斯顿大学电子前沿基金会和温瑞尔系统公司的研究人员联合发表了 HOW TO 一篇题为《鲜为人知的秘密鲜为人知的秘密：：：：对密钥的冷启动攻击对密钥的冷启动攻击对密钥的冷启动攻击》》》》的文章，该文详解了从运 ： 行系统获取内存信息的一种新型攻击方式。 -50 ◦C 1 2015/6/2 DMA ATTACK • DMA DMA attack • Direct Memory Access • 将传送到模块的信息复制到 内存 (RAM) ，并允许已处理 的信息自动从内存移到外部 外围装置。所有这些工作皆 独立于目前的 CPU 活动。 HOW TO: Example ：Russ Sevinsky’s Thunderbolt DMA • 实施总线偷听攻击，攻击者可通过 DMA 通道直接 访问小于 4G 物理内存（覆盖敏感数据的几率非常 大）。 • 典型案例： • 火线 (Apple Firewire)攻击 • Thunderbolt 攻击 • PCIe 总线攻击 DMA ATTACK MEMORY DUMP ANALYSIS • Current DMA research • Tool ：：：AESKeyFind • I/O attacks in Intel-PC architectures and • 在镜像中搜索并恢复 AES 密钥 countermeasures • 支持从不完整镜像中恢复密钥 • Understanding DMA malware • After-class reading Paper ： • Lest We Remember: Cold Boot Attacks on Encryption • Current Thunderbolt attacks ： Keys , in Proc. 17th USENIX Security Symposium (Sec ’08), San Jose, CA, July 2008. • Inception——Dump 4GB memory • Daisy chaining Thunderbolt and Firewire • De Mysteriis Dom Jobsivs (Mac EFI Rootkits) 2 2015/6/2 MEMORY DUMP ANALYSIS • Tool ：：：Volatility http://code.google.com/p/volatility/ • 开源内存取证分析框架，以灵活增补插件的方式工作 • 利用某些插件，渗透人员可以抽取出： ATTACKS ON HARDWARE ： • Windows 的hashes • SAM （安全用户帐户信息数据库） • Hardware-targeting • 注册表系统文件地址 • Purpose: • obtain the
    [Show full text]
  • Attack and Defense with Hardware-Aided Security
    Attack and Defense with Hardware-Aided Security Ning Zhang Dissertation submitted to the faculty of the Virginia Polytechnic Institute and State University in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Computer Science and Application Wenjing Lou, Chair Ing-Ray Chen Yiwei T. Hou Elaine R. Shi Kun Sun Danfeng Yao July 22, 2016 Falls Church, Virginia Keywords: Trusted Execution Environment, Hardware-Assisted Security, Secure Execution, Cache, Rootkit Copyright 2016, Raytheon Company Attack and Defense with Hardware-Aided Security Ning Zhang ABSTRACT Riding on recent advances in computing and networking, our society is now experiencing the evolution into the age of information. While the development of these technologies brings great value to our daily life, the lucrative reward from cyber-crimes has also attracted criminals. Unwanted software is delivered to the victims through various methods such as remote exploitation and social engineering. As computing continues to play an increasing role in the society, security has become a pressing issue. Failures in computing systems could result in loss of infrastructure or human life, as demonstrated in both academic research and production environment. With the continuing widespread of malicious software and new vulnerabilities revealing every day, protecting the heterogeneous computing systems across the Internet has become a daunting task. Our approach to this challenge consists of two directions. The first direction aims to gain a better understanding of the inner working of both attacks and defenses in the cyber environment. It was said in Art of War by Sun Tzu that if you know your enemies and know yourself, you will not be imperiled in a hundred battles.
    [Show full text]
  • IOMMU and DMA Attacks
    IOMMU and DMA attacks Date 20/11/2019 At C&ESAR 2019 By Jean-Christophe Delaunay Whoami Jean-Christophe Delaunay @Fist0urs on Twitter Working for Synacktiv: Offensive security company >50 ninjas 3 poles: pentest, reverse engineering, development In reverse engineering team (formerly in pentest): 25 reversers Focus on low level dev, reverse, vulnerability research/exploitation If there is software in it, we can own it :) We are hiring! 2 / 38 Whoami2 Jérémie Boutoille @tlk___ on Twitter Also in RE team... ...is sorry not to be here 3 / 38 Introduction Disclaimer State of the art of current known attacks will be addressed on Intel technology only Attacks will rely on PCI BUS only Presentation will stay “high-level”, please refer to the paper for more details Targeting a stolen laptop or backdooring the “evil maid” way – Computer is considered already switched on. Many IOMMUs have been harmed during tests 5 / 38 Direct Memory Access (DMA) (over)simplified functioning 6 / 38 Technologies PCI AGP [1] [2] FireWire etc. [3] PCI Express [4] [5] [6] 7 / 38 Intel VT-d – IOMMU “Virtualization Technology for Directed I/O”(VT-d) Proceeds to DMA remapping to restrict accesses to some memory locations DMA remapping works as a classical MMU (“IO-MMU”) through multiple layers of page tables Mapping by pages of 4KB, 2MB or 1GB Addresses manipulated by peripherals may be seen as virtual addresses translated to physical 8 / 38 Intel VT-d – IOMMU Peripherals are organized by “domains” Each domain has its proper MMU configuration
    [Show full text]
  • IOMMU and DMA Attacks
    IOMMU and DMA attacks Date 15/05/2020 At NorthSec 2020 By Jean-Christophe Delaunay Whoami Jean-Christophe Delaunay @Fist0urs on Twitter Working for Synacktiv: Offensive security company 75 ninjas 3 poles: pentest, reverse engineering, development In reverse engineering team (formerly in pentest): 30 reversers Focus on low level dev, reverse, vulnerability research/exploitation If there is software in it, we can own it :) We are hiring! 2 / 44 Roadmap Introduction Implementations Attacks Conclusion Ongoing works Introduction Disclaimer State of the art of current known attacks will be addressed on Intel technology only Presentation will stay “high-level” Attacks discussed involve an already switched on computer Many IOMMUs have been harmed during tests 5 / 44 Direct Memory Access (DMA) (over)simplified functioning 6 / 44 Technologies PCI AGP [1] [2] FireWire etc. [3] PCI Express [4] [6] [5] 7 / 44 Intel VT-d – IOMMU “Virtualization Technology for Directed I/O”(VT- d) Proceeds to DMA remapping to restrict accesses to some memory locations DMA remapping works as a classical MMU (“IO- MMU”) through multiple layers of page tables Mapping by pages of 4KB, 2MB or 1GB Addresses manipulated by peripherals may be seen as virtual addresses translated to physical 8 / 44 Intel VT-d – IOMMU Peripherals are organized by “domains” Each domain has its proper MMU configuration All peripherals within a single domain share the same memory mapping Each peripheral is identified by the triplet “bus:dev:fun” Domain may be
    [Show full text]