Secure Processor SECURE PROCESSOR Hardware-Supported Security
Total Page:16
File Type:pdf, Size:1020Kb
Load more
Recommended publications
-
CIS 4360 Secure Computer Systems Attacks Against Boot And
CIS 4360 Secure Computer Systems Attacks against Boot and RAM Professor Qiang Zeng Spring 2017 Previous Class • BIOS-MBR: Generation I system boot – What BIOS and MBR are? – How does it boot the system? // Jumping to MBR – How does multi-boot work? // Chain-loading • The limitations of BIOS and MBR – Disk, memory, file system, multi-booting, security, … • UEFI-GPT: Generation II system boot – What UEFI and GPT are? – How does it boot the system? // UEFI boot manager – How does multi-boot work? // separate dirs in ESP CIS 4360 – Secure Computer Systems 2 Limitations of BIOS-MBR • MBR is very limited – Support ~2TB disk only – 4 primary partitions at most (so four OSes at most) – A MBR can store only one boot loader • BIOS is very restrictive – 16-bit processor mode; 1MB memory space (little spare space to accommodate a file system driver) – Blindly executes whatever code on MBR CIS 4360 – Secure Computer Systems 3 UEFI vs. BIOS • Disk partitioning schemes – GPT (GUID Partition Table): part of UEFI spec.; to replace MBR – MBR supports disk size 232 x 512B = 2TB, while UEFI supports much larger disks (264 x 512B = 8,000,000,000 TB) – MBR supports 4 partitions, while GPT supports 128 • Memory space – BIOS: 20-bit addressing; UEFI: 32-bit or 64-bit • Pre-OS environment – BIOS only provides raw disk access, while UEFI supports the FAT file system (so you can use file names to read files) • Booting – BIOS supports boot through boot sectors (MBR and VBR) – UEFI provides a boot partition of hundreds of megabytes (and boot manager and secure boot) CIS 4360 – Secure Computer Systems 4 Previous Class How does dual-boo-ng of Linux and Windows work in UEFI-GPT? Each vendor has a separate directory storing its own boot loader code and configuraon files in the ESP (EFI System Par--on). -
Iocheck: a Framework to Enhance the Security of I/O Devices at Runtime
IOCheck: A Framework to Enhance the Security of I/O Devices at Runtime Fengwei Zhang Center for Secure Information Systems George Mason University Fairfax, VA 22030 [email protected] Abstract—Securing hardware is the foundation for implement- Management Mode (SMM), a CPU mode in the x86 archi- ing a secure system. However, securing hardware devices remains tecture, to quickly check the integrity of I/O configurations an open research problem. In this paper, we present IOCheck, and firmware. Unlike previous systems [11], [12], IOCheck a framework to enhance the security of I/O devices at runtime. enumerates all of the I/O devices on the motherboard, and It leverages System Management Mode (SMM) to quickly check checks the integrity of their corresponding configurations and the integrity of I/O configurations and firmware. IOCheck does not rely on the operating system and is OS-agnostic. In our firmware. IOCheck does not rely on the operating system, preliminary results, IOCheck takes 4 milliseconds to switch to which significantly reduces the Trust Computing Base (TCB). SMM which introduces low performance overhead. In addition, IOCheck is able to achieve better performance compared to TXT or SVM approaches. For example, the SMM Keywords—Integrity, Firmware, I/O Configurations, SMM switching time is much faster than the late launch method in Flicker [10], [13]. We will demonstrate that IOCheck is able to check the integrity of array of I/O devices including the BIOS, I. INTRODUCTION IOMMU, network card, video card, keyboard, and mouse. With the increasing complexity of hardware devices, Contributions. The purpose of this work is to make the firmware functionality is expanding, exposing new vulner- following contributions: abilities to attackers. -
2014 International Conference on Green Computing Communication and Electrical Engineering
2014 International Conference on Green Computing Communication and Electrical Engineering (ICGCCEE 2014) Coimbatore, India 6-8 March 2014 Pages 1-875 IEEE Catalog Number: CFP1460X-POD ISBN: 978-1-4799-4981-6 1/2 TABLE OF CONTENTS VOLUME 1 A NOVEL ROBUST & FAULT TOLERANCE FRAMEWORK FOR WEBSERVICES USING WS- I* SPECIFICATION.............................................................................................................................................................1 Pandey, Akhilesh Kumar ; Kumar, Abhishek ; Zade, Farahnaz Rezaeian A SURVEY OF SELF ORGANIZING TRUST METHOD TO AVOID MALICIOUS PEERS FROM PEER TO PEER NETWORK ..............................................................................................................................................6 Samuvelraj, G. ; Nalini, N. CONTRIVANCE OF ENERGY EFFICIENT ROUTING ALGORITHM IN WIRELESS BODY AREA NETWORK.............................................................................................................................................................. 10 Sridharan, Srivatsan ; Jammalamadaka, Sridhar EFFECTIVE DEFENDING AGAINST FLOOD ATTACK USING STREAM-CHECK METHOD IN TOLERANT NETWORK................................................................................................................................................... 17 Kuriakose, Divya ; Daniel, D. ANONYMOUS ROUTING TECHNIQUE IN MANET FOR SECURE TRANSMISSION: ART .............................. 21 Vijayan, Aleesha ; Yamini, C. DEFINING THE FRAMEWORK FOR WIRELESS-AMI SECURITY IN SMART GRID....................................... -
PCI PIN Transaction Security (PTS) Point of Interaction (POI)
Payment Card Industry (PCI) PIN Transaction Security (PTS) Point of Interaction (POI) Modular Security Requirements Version 4.0 June 2013 Document Changes Date Version Description February 2010 3.x RFC version April 2010 3.0 Public release October 2011 3.1 Clarifications and errata, updates for non-PIN POIs, encrypting card readers February 2013 4.x RFC version June 2013 4.0 Public release Payment Card Industry PTS POI Security Requirements v4.0 June 2013 Copyright 2013 PCI Security Standards Council LLC Page 1 Table of Contents Document Changes ................................................................................................................. 1 About This Document .............................................................................................................. 4 Purpose .................................................................................................................................. 4 Scope of the Document .......................................................................................................... 4 Main Differences from Previous Version ................................................................................. 5 PTS Approval Modules Selection ........................................................................................... 6 Foreword .................................................................................................................................. 7 Evaluation Domains ............................................................................................................... -
IOMMU-Resistant DMA Attacks
IOMMU-resistant DMA attacks Gil Kupfer Technion - Computer Science Department - M.Sc. Thesis MSC-2018-21 - 2018 Technion - Computer Science Department - M.Sc. Thesis MSC-2018-21 - 2018 IOMMU-resistant DMA attacks Research Thesis Submitted in partial fulfillment of the requirements for the degree of Master of Science in Computer Science Gil Kupfer Submitted to the Senate of the Technion | Israel Institute of Technology Sivan 5778 Haifa May 2018 Technion - Computer Science Department - M.Sc. Thesis MSC-2018-21 - 2018 Technion - Computer Science Department - M.Sc. Thesis MSC-2018-21 - 2018 This research was carried out under the supervision of Prof. Dan Tsafrir and Dr. Nadav Amit, in the Faculty of Computer Science. Acknowledgements who passed ,ז"ל This work is dedicated to my grandfather, Tuvia Kupfer away during the writing of this work. I would like to thank my wife, Odeya, for helping and supporting when needed. Also, I would like to thank all the friends who have been there. Finally, thanks to my advisors, Prof. Dan Tsafrir and Dr. Nadav Amit, for their help and guidance along the way. The generous financial help of the Technion is gratefully acknowledged. Technion - Computer Science Department - M.Sc. Thesis MSC-2018-21 - 2018 Technion - Computer Science Department - M.Sc. Thesis MSC-2018-21 - 2018 Contents List of Figures Abstract 1 Abbreviations and Notations3 1 Introduction5 2 Background9 2.1 DMA Attacks.................................9 2.1.1 Classic DMA Attacks........................9 2.1.2 IOMMU Protection......................... 10 2.1.3 Circumventing the IOMMU..................... 11 2.2 FireWire.................................... 12 3 Attack Mechanics 15 3.1 Sub-Page Granularity Vulnerability.................... -
Bypassing IOMMU Protection Against I/O Attacks Benoît Morgan, Eric Alata, Vincent Nicomette, Mohamed Kaâniche
Bypassing IOMMU Protection against I/O Attacks Benoît Morgan, Eric Alata, Vincent Nicomette, Mohamed Kaâniche To cite this version: Benoît Morgan, Eric Alata, Vincent Nicomette, Mohamed Kaâniche. Bypassing IOMMU Protection against I/O Attacks. 7th Latin-American Symposium on Dependable Computing (LADC’16), Oct 2016, Cali, Colombia. pp.145-150, 10.1109/LADC.2016.31. hal-01419962 HAL Id: hal-01419962 https://hal.archives-ouvertes.fr/hal-01419962 Submitted on 20 Dec 2016 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. Bypassing IOMMU protection against I/O Attacks Benoˆıt Morgan, Eric´ Alata, Vincent Nicomette, Mohamed Kaanicheˆ LAAS-CNRS, Universite´ de Toulouse, CNRS, INSA, Toulouse, France 7 Avenue du Colonel Roche 31000 Toulouse Email: [email protected], [email protected], [email protected], [email protected] Abstract—Attacks targeting computer systems become more and RAM memory segments. These communication channels and more complex and various. Some of them, so-called I/O raise serious concerns about the security of such architectures, attacks, are performed by malicious peripherals that make read since they open some opportunities to attackers to compromise or write accesses to DRAM memory or to memory embedded in other peripherals, through DMA (Direct Memory Access) the system and hosted applications using some malicious requests. -
Covering PCI and PA DSS)
Monetra® Payment Software Secure Implementation Guide (Covering PCI and PA DSS) Revision: 3.0b3 Publication date November, 2012 Copyright © 2012 Main Street Softworks, Inc. Secure Implementation Guide: (Covering PCI and PA DSS) Main Street Softworks, Inc. Revision: 3.0b3 Publication date November, 2012 Copyright © 2012 Main Street Softworks, Inc. Legal Notice The information contained herein is provided As Is without warranty of any kind, express or implied, including but not limited to, the implied warranties of merchantability and fitness for a particular purpose. There is no warranty that the information or the use thereof does not infringe a patent, trademark, copyright, or trade secret. Main Street Softworks, Inc. shall not be liable for any direct, special, incidental, or consequential damages resulting from the use of any information contained herein, whether resulting from breach of contract, breach of warranty, negligence, or otherwise, even if Main Street has been advised of the possibility of such damages. Main Street reserves the right to make changes to the information contained herein at anytime without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of Main Street Softworks, Inc. Table of Contents 1. Monetra Security Validation (PA-DSS) ......................................................................... 1 1.1. Do Not Retain Sensitive Data ........................................................................... -
Css241 Course Title: Basic Security and Security Threats
CSS 241 BASIC SECURITY AND SECURITY THREATS NATIONAL OPEN UNIVERSITY OF NIGERIA COURSE CODE :CSS241 COURSE TITLE: BASIC SECURITY AND SECURITY THREATS 1 CSS 241 BASIC SECURITY AND SECURITY THREATS COURSE GUIDE CSS241 BASIC SECURITY AND SECURITY THREATS Course Developer/Writer Monsuru Adegboyega Kasali Non-Violence and Intercultural Communication Advocacy Initiatives, Ibadan, Nigeria Course Editor Rasidi Okunola, Ph. D Department of Sociology University of Ibadan Oyo State Course Coordinator Adeniyi T. Adegoke, Ph.D Criminology and Security Studies School of Arts and Social Sciences National Open University of Nigeria Programme Leader Prof. Abdul-Rasheed Yesufu Dean, School of Arts and Social Sciences National Open University of Nigeria 2 CSS 241 BASIC SECURITY AND SECURITY THREATS NATIONAL OPEN UNIVERSITY OF NIGERIA National Open University of Nigeria Headquarters 14/16 Ahmadu Bello Way Victoria Island Lagos Abuja Office No. 5 Dar es Salam Street Off Aminu Kano Crescent Wuse II, Abuja Nigeria e-mail: [email protected] URL: www.nou.edu.ng Published by National Open University of Nigeria Printed ISBN: All Rights Reserved CONTENTS PAGE Introduction……………………………………..………....i-ii What You Will Learn in this Course ...................................ii Course Aims…………………………………………..... ..ii-iii Course Objectives……………………………………… …iii-iv Working through this Course ...............................................iv Course Materials……………………………….………. …v 3 CSS 241 BASIC SECURITY AND SECURITY THREATS Study Units…………………………………….………. …v-vi Textbooks and References…………….……….……… ….vi-vii Assignment File ………………………………………. ….vii Assessment ………………………………….………. ……viii Tutor-Marked Assignment……………………………. …..viii Final Examination and Grading…………………..……. …viii Course Marking Scheme ………………………………. …viii Course Overview ………………………………………. …viii-ix Presentation Schedule …………………………………. …x How to Get the Most from this Course ……………………x Reading Section.....................................................................x-xi Facilitators/Tutors and Tutorials ………………………. -
Protecting Data In-Use from Firmware and Physical Attacks
Protecting Data In-Use from Firmware and Physical Attacks Stephen Weis PrivateCore Palo Alto, CA ABSTRACT 2. PHYSICAL ATTACKS Defending computers from unauthorized physical access, ma- It is generally understood that physical access to an x86 licious hardware devices, or other low-level attacks has proven platform can completely compromise software security. His- extremely challenging. The risks from these attacks are torically, physical security controls such as cages, cameras, exacerbated in cloud-computing environments, where users and locks have been employed to prevent or detect physical lack physical control over servers executing their workloads. access. Yet with adoption of outsourced infrastructure and This paper reviews several firmware and physical attacks cloud computing, x86 platforms are increasingly run outside against x86 platforms, including bootkits, "cold booting", the physical control of the software owner. and malicious devices. We discuss several existing tools and This section briefly summarizes several well-known phys- technologies that can mitigate these risk such as Trusted ical attack vectors against x86 platforms, including DMA Execution Technology (TXT) and main memory encryption. and physical memory extraction. We will also discuss upcoming technologies that may help protect against firmware and physical threats. 2.1 Direct Memory Access By design, x86 architectures provide direct memory access (DMA) from hardware subsystems to main memory without 1. INTRODUCTION invoking the CPU. DMA is generally used to improve per- formance. For example, DMA allows disk, network, and In 2013, journalists revealed that the United States Na- graphics devices to read and write data directly to memory tional Security Agency's (NSA) Tailored Access Operations without incurring CPU cycles. -
Trusted Platform Module Explained What It Is, What It Does and What Its Benefits Are
Bosch Security Systems | Video Systems 1 | 9 Trusted Platform Module explained What it is, what it does and what its benefits are Data subject not change without notice | August 2016 Security Systems / Video Systems Bosch Security Systems | Video Systems 2 | 9 Table of contents 1 Introduction 3 2 Trusted Platform Module 4 2.1 What a Trusted Platform Module is ..................................................................................................................... 4 2.2 What a Trusted Platform Module does ................................................................................................................ 5 2.3 What a Trusted Platform Module’s benefits are .................................................................................................. 6 3 Appendix 7 3.1 Standard or not standard? .................................................................................................................................. 7 3.2 How clients or integrations are affected .............................................................................................................. 7 4 Glossary 8 Data subject not change without notice | August 2016 Security Systems / Video Systems Bosch Security Systems | Video Systems 3 | 9 1 Introduction As security systems have transitioned into network devices over the last few decades, system vulnerabilities have transitioned as well. This shift in network utilization brings with it far more vulnerabilities than compared to older analog systems, and due to the very nature of -
IOMMU Protection Against I/O Attacks: a Vulnerability and a Proof-Of-Concept Benoît Morgan, Eric Alata, Vincent Nicomette, Mohamed Kaâniche
IOMMU protection against I/O attacks: A vulnerability and a proof-of-concept Benoît Morgan, Eric Alata, Vincent Nicomette, Mohamed Kaâniche To cite this version: Benoît Morgan, Eric Alata, Vincent Nicomette, Mohamed Kaâniche. IOMMU protection against I/O attacks: A vulnerability and a proof-of-concept. Journal of the Brazilian Computer Society, Springer Verlag, 2018, 24, pp.Article number: 2. 10.1186/s13173-017-0066-7. hal-02877143 HAL Id: hal-02877143 https://hal.archives-ouvertes.fr/hal-02877143 Submitted on 22 Jun 2020 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. Morgan et al. RESEARCH IOMMU protection against I/O attacks: A vulnerability and a proof-of-concept Beno^ıtMorgan1,2*, Eric´ Alata1,2, Vincent Nicomette1,2 and Mohamed Ka^aniche1 performance levels and hardware services, more so- phisticated architectures have emerged with multiple input/output communication channels. In particular, normalized communication buses have been specified Abstract to allow tier manufacturers to complement bare ar- I/O attacks have received increasing attention chitectures with complex peripherals. Then, to relieve during the last decade. These attacks are the host processor from performing certain data copies performed by malicious peripherals that make read and operations, DMA cycles have been added to these or write accesses to DRAM memory or to memory external buses, allowing peripherals to perform read- embedded in other peripherals, through DMA /write accesses to other peripherals and RAM memory (Direct Memory Access) requests. -
Komunikacija Grafičkog I Središnjeg Procesora U Heterogenom Računalnom Sustavu
Komunikacija grafičkog i središnjeg procesora u heterogenom računalnom sustavu Sočković, Augustin Master's thesis / Diplomski rad 2019 Degree Grantor / Ustanova koja je dodijelila akademski / stručni stupanj: University of Rijeka / Sveučilište u Rijeci Permanent link / Trajna poveznica: https://urn.nsk.hr/urn:nbn:hr:195:641511 Rights / Prava: In copyright Download date / Datum preuzimanja: 2021-09-27 Repository / Repozitorij: Repository of the University of Rijeka, Department of Informatics - INFORI Repository Sveučilište u Rijeci – Odjel za informatiku Diplomski studij informatike, smjer Poslovna informatika Augustin Sočković Komunikacija grafičkog i središnjeg procesora u heterogenom računalnom sustavu Diplomski rad Mentor: v. pred. dr. sc. Vedran Miletić Rijeka, 10. prosinca 2019. Sažetak U radu je opisana komunikacija osnovnog i grafičkog procesora u heterogenom računalnom sustavu, definirana heterogenua sustavska arhitektura (HSA), te skiciran "povijesni okvir" razvoja CPU-a i GPU-a do tehnologije koja je omgućila HSA. Opisan je načn rada platforme za razvoj aplikacija za heterogenu sustavsku arhitekturu, specifično način na koji grafički i središnji procesor unutar iste komuniciraju. Odabrana je platforma ROCm zbog otvorenosti i dostupnosti AMD-ovog grafičkog procesora. Ključne riječi CPU, GPU, ROCm, rocBLAS, rocSPARSE, rocRAND, AMD, HPC, heterogeno, računarstvo, arhitektura Sadržaj 1. Uvod................................................................................................................................................1