Direct Memory Access Attacks a Walk Down Memory Lane
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CIS 4360 Secure Computer Systems Attacks Against Boot And
CIS 4360 Secure Computer Systems Attacks against Boot and RAM Professor Qiang Zeng Spring 2017 Previous Class • BIOS-MBR: Generation I system boot – What BIOS and MBR are? – How does it boot the system? // Jumping to MBR – How does multi-boot work? // Chain-loading • The limitations of BIOS and MBR – Disk, memory, file system, multi-booting, security, … • UEFI-GPT: Generation II system boot – What UEFI and GPT are? – How does it boot the system? // UEFI boot manager – How does multi-boot work? // separate dirs in ESP CIS 4360 – Secure Computer Systems 2 Limitations of BIOS-MBR • MBR is very limited – Support ~2TB disk only – 4 primary partitions at most (so four OSes at most) – A MBR can store only one boot loader • BIOS is very restrictive – 16-bit processor mode; 1MB memory space (little spare space to accommodate a file system driver) – Blindly executes whatever code on MBR CIS 4360 – Secure Computer Systems 3 UEFI vs. BIOS • Disk partitioning schemes – GPT (GUID Partition Table): part of UEFI spec.; to replace MBR – MBR supports disk size 232 x 512B = 2TB, while UEFI supports much larger disks (264 x 512B = 8,000,000,000 TB) – MBR supports 4 partitions, while GPT supports 128 • Memory space – BIOS: 20-bit addressing; UEFI: 32-bit or 64-bit • Pre-OS environment – BIOS only provides raw disk access, while UEFI supports the FAT file system (so you can use file names to read files) • Booting – BIOS supports boot through boot sectors (MBR and VBR) – UEFI provides a boot partition of hundreds of megabytes (and boot manager and secure boot) CIS 4360 – Secure Computer Systems 4 Previous Class How does dual-boo-ng of Linux and Windows work in UEFI-GPT? Each vendor has a separate directory storing its own boot loader code and configuraon files in the ESP (EFI System Par--on). -
Iocheck: a Framework to Enhance the Security of I/O Devices at Runtime
IOCheck: A Framework to Enhance the Security of I/O Devices at Runtime Fengwei Zhang Center for Secure Information Systems George Mason University Fairfax, VA 22030 [email protected] Abstract—Securing hardware is the foundation for implement- Management Mode (SMM), a CPU mode in the x86 archi- ing a secure system. However, securing hardware devices remains tecture, to quickly check the integrity of I/O configurations an open research problem. In this paper, we present IOCheck, and firmware. Unlike previous systems [11], [12], IOCheck a framework to enhance the security of I/O devices at runtime. enumerates all of the I/O devices on the motherboard, and It leverages System Management Mode (SMM) to quickly check checks the integrity of their corresponding configurations and the integrity of I/O configurations and firmware. IOCheck does not rely on the operating system and is OS-agnostic. In our firmware. IOCheck does not rely on the operating system, preliminary results, IOCheck takes 4 milliseconds to switch to which significantly reduces the Trust Computing Base (TCB). SMM which introduces low performance overhead. In addition, IOCheck is able to achieve better performance compared to TXT or SVM approaches. For example, the SMM Keywords—Integrity, Firmware, I/O Configurations, SMM switching time is much faster than the late launch method in Flicker [10], [13]. We will demonstrate that IOCheck is able to check the integrity of array of I/O devices including the BIOS, I. INTRODUCTION IOMMU, network card, video card, keyboard, and mouse. With the increasing complexity of hardware devices, Contributions. The purpose of this work is to make the firmware functionality is expanding, exposing new vulner- following contributions: abilities to attackers. -
Direct Memory Access
International Journal of Research in Science And Technology http://www.ijrst.com (IJRST) 2014, Vol. No. 4, Issue No. III, Jul-Sep ISSN: 2249-0604 DIRECT MEMORY ACCESS LokeshMadan1, KislayAnand2and Bharat Bhushan3 1Department of Computer Science, Dronacharya College of Engineering, Gurgaon, India 2Department of Computer Science, Dronacharya College of Engineering, Gurgaon, India 3Department of Computer Science, Dronacharya College of Engineering, Gurgaon, India ABSTRACT Direct Memory Access (DMA) is a feature in all modern computers that allow devices to be able to move large blocks of data without any interaction with the processor. This can be useful, as you may have already seen from the floppy programming chapter. While the device transfers the block of data, the processor is free to continue running the software without worry about the data being transferred into memory, or to another device. The basic idea is that we can schedule the DMA device to perform the task on its own. Different buses and architecture designs have different methods of performing direct memory access. KEYWORDS: Processor register,cyclestealing,busmastering,countregisters,interleaved,c ache invalidation, schematics, gigabit Ethernet. INTRODUCTION A DMA controller can generate memory addresses and initiate memory read or write cycles. It contains several processor registers that can be written and read by the CPU. These include a memory address register, a byte count register, and one or more control registers. The control registers specify the I/O port to use, the direction of the transfer (reading from the I/O device or writing to the I/O device), the transfer unit (byte at a time or word at a time), and the number of bytes to transfer in one burst. -
Tcss 422: Operating Systems
TCSS 422 A – Fall 2018 12/6/2018 School of Engineering and Technology, TCSS 422: OPERATING SYSTEMS Beyond Physical Memory, I/O Devices Wes J. Lloyd School of Engineering and Technology, University of Washington - Tacoma TCSS422: Operating Systems [Fall 2018] December 5, 2018 School of Engineering and Technology, University of Washington - Tacoma FEEDBACK FROM 12/3 Program 3 Write to a proc file? Once we have a reference to a process, we then traverse pages on that process? TCSS422: Operating Systems [Fall 2018] December 5, 2018 L19.2 School of Engineering and Technology, University of Washington - Tacoma FEEDBACK - 2 Which I/O Devices work better with interrupts (other than keyboard)? Interrupt driven I/O - - is off-loaded from the CPU . Via Directory Memory Access (DMA) controller . CPU non involved in the data transfer . Interrupts enable a context-switch to notify data is available . Examples: ISA, PCI bus Polled I/O is - - programmed I/O Data transfers fully occupy CPU for entire data transfer CPU unavailable for other work Examples: ATA (parallel ports), legacy serial/parallel ports, PS/2 keyboard/mouse, MIDI, joysticks TCSS422: Operating Systems [Fall 2018] December 5, 2018 L19.3 School of Engineering and Technology, University of Washington - Tacoma Slides by Wes J. Lloyd L19.1 TCSS 422 A – Fall 2018 12/6/2018 School of Engineering and Technology, FEEDBACK - 3 Does the mouse use interrupts, polling, or a hybrid of both? . Interrupts . Where is the polling (BUSY) process? (see top –d .1) TCSS422: Operating Systems [Fall 2018] December 5, 2018 L19.4 School of Engineering and Technology, University of Washington - Tacoma CLOUD AND DISTRIBUTED SYSTEMS RESEARCH L19.5 CLOUD AND DISTRIBUTED SYSTEMS LAB WES LLOYD, [email protected], HTTP://FACULTY.WASHINGTON.EDU/WLLOYD Serverless Computing (FaaS): How should cloud native applications be composed from microservices to optimize performance and cost? Code structure directly influences hosting costs. -
Setting up MPU-401 and Compatible Cards on Your PC
® Supplemental RAP-10 ®ÂØÒňΠRoland Audio Producer Notes May 21, 1996 Installing the RAP-10 in Windows 95 These notes are designed to help you install the Roland Audio Production Card (RAP-10) and configure it for use in Windows 95. This process will consist of the following four steps: I. First, we will look at computers and peripherals and how they work together. See “Typical Hardware Setup”. II. Second, we will prepare the RAP-10 for installation. See “Changing Hardware Settings”. III. Third, we will install the Windows software. See “Installing the Roland Audio Tools Software”. IV. Finally, we will test the RAP-10 to make sure it has been installed properly. See “Testing the RAP-10 Card”. If you were previously using the RAP-10 successfully under Windows 3.1 in the same computer, you can skip the first two steps and go directly to Section III. I. Typical Hardware Setup Interrupts and Addresses IBM-compatible computers can be expanded to accept many different devices such as a mouse, modem, printer, sound card, or MIDI card. Your computer uses interrupts (also called IRQs) and port addresses (or I/O addresses) to distinguish between these different devices. Since this guide is not intended to explain the concepts of IBM computers in detail, we will not jump into the particular definitions of IRQs and addresses. Just remember that the IRQ and port address numbers must be unique for EVERY device in your computer. DMA Channels The RAP-10 card also uses two DMA channels (Direct Memory Access) for the recording and playback of digital audio. -
Computer Service Technician- CST Competency Requirements
Computer Service Technician- CST Competency Requirements This Competency listing serves to identify the major knowledge, skills, and training areas which the Computer Service Technician needs in order to perform the job of servicing the hardware and the systems software for personal computers (PCs). The present CST COMPETENCIES only address operating systems for Windows current version, plus three older. Included also are general common Linux and Apple competency information, as proprietary service contracts still keep most details specific to in-house service. The Competency is written so that it can be used as a course syllabus, or the study directed towards the education of individuals, who are expected to have basic computer hardware electronics knowledge and skills. Computer Service Technicians must be knowledgeable in the following technical areas: 1.0 SAFETY PROCEDURES / HANDLING / ENVIRONMENTAL AWARENESS 1.1 Explain the need for physical safety: 1.1.1 Lifting hardware 1.1.2 Electrical shock hazard 1.1.3 Fire hazard 1.1.4 Chemical hazard 1.2 Explain the purpose for Material Safety Data Sheets (MSDS) 1.3 Summarize work area safety and efficiency 1.4 Define first aid procedures 1.5 Describe potential hazards in both in-shop and in-home environments 1.6 Describe proper recycling and disposal procedures 2.0 COMPUTER ASSEMBLY AND DISASSEMBLY 2.1 List the tools required for removal and installation of all computer system components 2.2 Describe the proper removal and installation of a CPU 2.2.1 Describe proper use of Electrostatic Discharge -
~ ARTISAN® with Experienced Engineers and Technicians on Staff
Full-service, independent repair center -~ ARTISAN® with experienced engineers and technicians on staff. TECHNOLOGY GROUP ~I We buy your excess, underutilized, and idle equipment along with credit for buybacks and trade-ins. Custom engineering Your definitive source so your equipment works exactly as you specify. for quality pre-owned • Critical and expedited services • Leasing / Rentals/ Demos equipment. • In stock/ Ready-to-ship • !TAR-certified secure asset solutions Expert team I Trust guarantee I 100% satisfaction Artisan Technology Group (217) 352-9330 | [email protected] | artisantg.com All trademarks, brand names, and brands appearing herein are the property o f their respective owners. Find the Measurement Computing / CEC PC-488 at our website: Click HERE Program and documentation copyrighted 1986, 1998, 2003 by Capital Equipment Corporation (CEC). The software interpreter contained in EPROM/ROM is copyrighted and all rights are reserved by Capital Equipment Corporation. Copying or duplicating this product is a violation of law. Application software libraries provided on disk are copyrighted by Capital Equipment Corporation. The purchaser is granted the right to include portions of this software in products which use one of CEC's IEEE-488 interface boards (including those sold through resellers such as Keithley Instruments, etc.). The software may not be distributed other than for the application just mentioned. Purchasers of this product may copy and use the programming examples contained in this book. No other parts of this book may be reproduced or transmitted in any form or by any means, electronic, optical, or mechanical, including photocopying and recording, or by any information storage and retrieval system, without permission in writing from Capital Equipment Corporation. -
IOMMU-Resistant DMA Attacks
IOMMU-resistant DMA attacks Gil Kupfer Technion - Computer Science Department - M.Sc. Thesis MSC-2018-21 - 2018 Technion - Computer Science Department - M.Sc. Thesis MSC-2018-21 - 2018 IOMMU-resistant DMA attacks Research Thesis Submitted in partial fulfillment of the requirements for the degree of Master of Science in Computer Science Gil Kupfer Submitted to the Senate of the Technion | Israel Institute of Technology Sivan 5778 Haifa May 2018 Technion - Computer Science Department - M.Sc. Thesis MSC-2018-21 - 2018 Technion - Computer Science Department - M.Sc. Thesis MSC-2018-21 - 2018 This research was carried out under the supervision of Prof. Dan Tsafrir and Dr. Nadav Amit, in the Faculty of Computer Science. Acknowledgements who passed ,ז"ל This work is dedicated to my grandfather, Tuvia Kupfer away during the writing of this work. I would like to thank my wife, Odeya, for helping and supporting when needed. Also, I would like to thank all the friends who have been there. Finally, thanks to my advisors, Prof. Dan Tsafrir and Dr. Nadav Amit, for their help and guidance along the way. The generous financial help of the Technion is gratefully acknowledged. Technion - Computer Science Department - M.Sc. Thesis MSC-2018-21 - 2018 Technion - Computer Science Department - M.Sc. Thesis MSC-2018-21 - 2018 Contents List of Figures Abstract 1 Abbreviations and Notations3 1 Introduction5 2 Background9 2.1 DMA Attacks.................................9 2.1.1 Classic DMA Attacks........................9 2.1.2 IOMMU Protection......................... 10 2.1.3 Circumventing the IOMMU..................... 11 2.2 FireWire.................................... 12 3 Attack Mechanics 15 3.1 Sub-Page Granularity Vulnerability.................... -
Bypassing IOMMU Protection Against I/O Attacks Benoît Morgan, Eric Alata, Vincent Nicomette, Mohamed Kaâniche
Bypassing IOMMU Protection against I/O Attacks Benoît Morgan, Eric Alata, Vincent Nicomette, Mohamed Kaâniche To cite this version: Benoît Morgan, Eric Alata, Vincent Nicomette, Mohamed Kaâniche. Bypassing IOMMU Protection against I/O Attacks. 7th Latin-American Symposium on Dependable Computing (LADC’16), Oct 2016, Cali, Colombia. pp.145-150, 10.1109/LADC.2016.31. hal-01419962 HAL Id: hal-01419962 https://hal.archives-ouvertes.fr/hal-01419962 Submitted on 20 Dec 2016 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. Bypassing IOMMU protection against I/O Attacks Benoˆıt Morgan, Eric´ Alata, Vincent Nicomette, Mohamed Kaanicheˆ LAAS-CNRS, Universite´ de Toulouse, CNRS, INSA, Toulouse, France 7 Avenue du Colonel Roche 31000 Toulouse Email: [email protected], [email protected], [email protected], [email protected] Abstract—Attacks targeting computer systems become more and RAM memory segments. These communication channels and more complex and various. Some of them, so-called I/O raise serious concerns about the security of such architectures, attacks, are performed by malicious peripherals that make read since they open some opportunities to attackers to compromise or write accesses to DRAM memory or to memory embedded in other peripherals, through DMA (Direct Memory Access) the system and hosted applications using some malicious requests. -
Position Paper:Defending Direct Memory Access with CHERI
Position Paper: Defending Direct Memory Access with CHERI Capabilities A. Theodore Markettos John Baldwin Ruslan Bukin University of Cambridge Ararat River Consulting University of Cambridge [email protected] Peter G. Neumann Simon W. Moore Robert N. M. Watson SRI International University of Cambridge University of Cambridge ABSTRACT We propose new solutions that can efficiently address the problem of malicious memory access from pluggable computer peripherals and microcontrollers embedded within a system-on-chip. This prob- lem represents a serious emerging threat to total-system computer security. Previous work has shown that existing defenses are insuf- ficient and poorly deployed, in part due to performance concerns. In this paper we explore the threat and its implications for system architecture. We propose a range of protection techniques, from lightweight to heavyweight, across different classes of systems. We consider how emerging capability architectures (and specifically the CHERI protection model) can enhance protection and provide Figure 1: A typical computer system contains multiple a convenient bridge to describe interactions among software and components with rights to directly access memory – not hardware components. Finally, we describe how new schemes may only from internal processor cores, but also from peripheral be more efficient than existing defenses. devices. Those which do not have access to DMA typically ACM Reference Format: can intermediate via a host controller that does. A. Theodore Markettos, John Baldwin, Ruslan Bukin, Peter G. Neumann, Simon W. Moore, and Robert N. M. Watson. 2020. Position Paper: Defending Direct Memory Access with CHERI Capabilities. In Proceedings of Hardware and Architectural Support for Security and Privacy (HASP’20). -
DMA, System Buses and Peripheral Buses
EECE 379 : DESIGN OF DIGITAL AND MICROCOMPUTER SYSTEMS 2000/2001 WINTER SESSION, TERM 1 DMA, System Buses and Peripheral Buses Direct Memory Access is a method of transferring data between peripherals and memory without using the CPU. After this lecture you should be able to: identify the advantages and disadvantages of using DMA and programmed I/O, select the most appropriate method for a particular application. System buses are the buses used to interface the CPU with memory and peripherals on separate PC cards. The ISA and PCI buses are used as examples. You should be able to state the most important specifications of both buses. Serial interfaces are typically used to connect computer systems and low-speed external peripherals such as modems and printers. Serial interfaces reduce the cost of interconnecting devices because the bits in a byte are time-multiplexed onto a single wire and connector. After this lecture you should be able to describe the operation and format of data and handshaking signals on an RS-232 interface. Parallel ports are also used to interface the CPU to I/O devices. Two common parallel port standards, the “Centron- ics” parallel printer port and the SCSI interface are described. After this lecture you should be able to design simple input and output I/O ports using address decoders, registers and tri-state buffers. Programmed I/O Approximately how many bus cycles will be required? Programmed I/O (PIO) refers to using input and out- put (or move) instructions to transfer data between Direct Memory Access (DMA) memory and the registers on a peripheral interface. -
Protecting Data In-Use from Firmware and Physical Attacks
Protecting Data In-Use from Firmware and Physical Attacks Stephen Weis PrivateCore Palo Alto, CA ABSTRACT 2. PHYSICAL ATTACKS Defending computers from unauthorized physical access, ma- It is generally understood that physical access to an x86 licious hardware devices, or other low-level attacks has proven platform can completely compromise software security. His- extremely challenging. The risks from these attacks are torically, physical security controls such as cages, cameras, exacerbated in cloud-computing environments, where users and locks have been employed to prevent or detect physical lack physical control over servers executing their workloads. access. Yet with adoption of outsourced infrastructure and This paper reviews several firmware and physical attacks cloud computing, x86 platforms are increasingly run outside against x86 platforms, including bootkits, "cold booting", the physical control of the software owner. and malicious devices. We discuss several existing tools and This section briefly summarizes several well-known phys- technologies that can mitigate these risk such as Trusted ical attack vectors against x86 platforms, including DMA Execution Technology (TXT) and main memory encryption. and physical memory extraction. We will also discuss upcoming technologies that may help protect against firmware and physical threats. 2.1 Direct Memory Access By design, x86 architectures provide direct memory access (DMA) from hardware subsystems to main memory without 1. INTRODUCTION invoking the CPU. DMA is generally used to improve per- formance. For example, DMA allows disk, network, and In 2013, journalists revealed that the United States Na- graphics devices to read and write data directly to memory tional Security Agency's (NSA) Tailored Access Operations without incurring CPU cycles.