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EMBEDDED IntelDX2™ PROCESSOR ■ Integrated Floating-Point Unit ■ SL Technology ■ Speed-Multiplying Technology ■ Data Bus Parity Generation and Checking ■ 32-Bit RISC Technology Core ■ Boundary Scan (JTAG) ■ 8-Kbyte Write-Through Cache ■ 3.3-Volt Processor, 50 MHz, 25 MHz CLK ■ Four Internal Write Buffers — 208-Lead Shrink Quad Flat Pack (SQFP) ■ ■ Burst Bus Cycles 5-Volt Processor, 66 MHz, 33 MHz CLK — 168-Pin Pin Grid Array (PGA) ■ Dynamic Bus Sizing for 8- and 16-bit Data Bus Devices ■ Binary Compatible with Large Software Base 64-Bit Interunit Transfer Bus 32-Bit Data Bus Core CLK Clock Clock 32-Bit Data Bus Multiplier Linear Address 32 PCD PWT Bus Interface Barrel Base/ Segmentation 2 A31-A2 Shifter Index Unit Paging Cache Unit 32 Address BE3#- BE0# Bus Unit 20 Drivers Register 32 Descriptor File Registers Physical 8 Kbyte Write Buffers Address 32 4 x 32 Translation Cache ALU Limit and D31-D0 Attribute PLA Lookaside Data Bus Buffer 32 Transceivers Bus Control ADS# W/R# D/C# M/IO# PCD PWT RDY# LOCK# 128 PLOCK# BOFF# A20M# Displacement Bus BREQ HOLD HLDA RESET SRESET INTR 32 NMI SMI# SMIACT# Prefetcher FERR# IGNNE# Micro- STPCLK# Instruction Request Sequencer 32-Byte Code BRDY# BLAST# Queue Burst Bus Code Control Stream 2x16 Bytes Floating Control & Instruction Bus Size BS16# BS8# 24 Point Unit Protection Decode Control Test Unit Cache KEN# FLUSH# Floating Decoded AHOLD EADS# Control Instruction Control Point Path Register File ROM Parity DP3-DP0 PCHK# Generation and Control Boundary TCK TMS TDI TD0 Scan Control A3223-01 Figure 1. Embedded IntelDX2™ Processor Block Diagram © INTEL CORPORATION, 1997 December 1997 Order Number: 272770-002 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Embedded IntelDX2™ processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Copyright © Intel Corporation, 1997 *Third-party brands and names are the property of their respective owners. Contents EMBEDDED IntelDX2™ PROCESSOR 1.0 INTRODUCTION ........................................................................................................................................ 1 1.1 Features ............................................................................................................................................. 1 1.2 Family Members ................................................................................................................................. 2 2.0 HOW TO USE THIS DOCUMENT ............................................................................................................. 3 3.0 PIN DESCRIPTIONS ................................................................................................................................. 3 3.1 Pin Assignments ................................................................................................................................. 3 3.2 Pin Quick Reference ......................................................................................................................... 16 4.0 ARCHITECTURAL AND FUNCTIONAL OVERVIEW ............................................................................. 25 4.1 CPUID Instruction ............................................................................................................................. 25 4.1.1 Operation of the CPUID Instruction ....................................................................................... 25 4.2 Identification After Reset .................................................................................................................. 26 4.3 Boundary Scan (JTAG) .................................................................................................................... 26 4.3.1 Device Identification ............................................................................................................... 26 4.3.2 Boundary Scan Register Bits and Bit Order ........................................................................... 27 5.0 ELECTRICAL SPECIFICATIONS ........................................................................................................... 28 5.1 Maximum Ratings ............................................................................................................................. 28 5.2 DC Specifications ............................................................................................................................. 28 5.3 AC Specifications ............................................................................................................................. 33 5.4 Capacitive Derating Curves .............................................................................................................. 39 6.0 MECHANICAL DATA .............................................................................................................................. 41 6.1 Package Dimensions ........................................................................................................................ 41 6.2 Package Thermal Specifications ...................................................................................................... 44 FIGURES Figure 1. Embedded IntelDX2™ Processor Block Diagram ...................................................................... i Figure 2. Package Diagram for 208-Lead SQFP Embedded IntelDX2™ Processor ................................ 4 Figure 3. Package Diagram for 168-Pin PGA Embedded IntelDX2™ Processor ................................... 10 Figure 4. CLK Waveform ........................................................................................................................ 35 Figure 5. Input Setup and Hold Timing ................................................................................................... 35 Figure 6. Input Setup and Hold Timing ................................................................................................... 36 Figure 7. PCHK# Valid Delay Timing ...................................................................................................... 36 Figure 8. Output Valid Delay Timing ....................................................................................................... 37 Figure 9. Maximum Float Delay Timing .................................................................................................. 37 Figure 10. TCK Waveform ........................................................................................................................ 38 Figure 11. Test Signal Timing Diagram .................................................................................................... 38 iii Contents Figure 12. Typical Loading Delay versus Load Capacitance under Worst-Case Conditions for a Low-to-High Transition, 3.3 V Processor .........................................................................39 Figure 13. Typical Loading Delay versus Load Capacitance under Worst-Case Conditions for a High-to-Low Transition, 3.3 V Processor .........................................................................39 Figure 14. Typical Loading Delay versus Load Capacitance under Worst-Case Conditions for a Low-to-High Transition, 5 V Processor ......................................40 Figure 15. Typical Loading Delay versus Load Capacitance under Worst-Case Conditions for a High-to-Low Transition, 5 V Processor ......................................40 Figure 16. 208-Lead SQFP Package Dimensions .................................................................................... 41 Figure 17. Principal Dimensions and Data for 168-Pin Pin Grid Array Package .......................................42 TABLES Table 1. The Embedded IntelDX2™ Processor Family ............................................................................2 Table 2. Pinout Differences for 208-Lead SQFP Package ......................................................................5 Table 3. Pin Assignment for 208-Lead SQFP Package ...........................................................................6
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