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Pentium® Processor Family Developer's Manual

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Pentium® Processor Family Developer's Manual D Pentium® Processor Family Developer’s Manual 1997 12/19/96 9:12 AM Front.doc Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Pentium® processor may contain design defects or errors known as errata. Current characterized errata are available on request. MPEG is an international standard for video compression/decompression promoted by ISO. Implementations of MPEG CODECs, or MPEG enabled platforms may require licenses from various entities, including Intel Corporation. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 7641 Mt. Prospect IL 60056-7641 or call 1-800-879-4683 or visit Intel’s website at http:\\www.intel.com Copyright © Intel Corporation 1996, 1997. Third-party brands and names are the property of their respective owners 12/19/96 9:12 AM Front.doc E TABLE OF CONTENTS CHAPTER 1 Page ARCHITECTURAL FEATURES OF THE PENTIUM® PROCESSOR FAMILY 1.1. PROCESSOR FEATURES OVERVIEW....................................................................... 1-1 1.2. COMPONENT INTRODUCTION .................................................................................. 1-2 CHAPTER 2 COMPONENT OPERATION 2.1. PIPELINE AND INSTRUCTION FLOW ........................................................................ 2-1 2.1.1. Pentium® Processor Integer Pipeline Description.................................................... 2-2 2.1.1.1. INSTRUCTION PREFETCH ................................................................................. 2-4 2.1.2. Integer Instruction Pairing Rules .............................................................................. 2-4 2.2. BRANCH PREDICTION................................................................................................ 2-5 2.3. FLOATING-POINT UNIT .............................................................................................. 2-9 2.3.1. Floating-Point Pipeline Stages ................................................................................. 2-9 2.3.2. Instruction Issue ....................................................................................................... 2-9 2.3.3. Safe Instruction Recognition................................................................................... 2-10 2.3.4. FPU Bypasses........................................................................................................ 2-11 2.3.5. Branching Upon Numeric Condition Codes............................................................ 2-12 2.4. MMX™ UNIT .............................................................................................................. 2-13 2.4.1. Overview of the MMX™ Programming Environment .............................................. 2-13 2.4.1.1. MMX™ REGISTERS .......................................................................................... 2-13 2.4.1.2. MMX™ DATA TYPES......................................................................................... 2-14 2.4.1.3. SINGLE INSTRUCTION, MULTIPLE DATA (SIMD) EXECUTION MODEL ....... 2-15 2.4.1.4. MEMORY DATA FORMATS............................................................................... 2-16 2.4.1.5. MMX™ REGISTER DATA FORMATS................................................................ 2-16 2.4.2. MMX™ Instruction Set............................................................................................ 2-16 2.4.3. Intel MMX™ Technology Pipeline Stages .............................................................. 2-17 2.4.4. Instruction Issue ..................................................................................................... 2-19 2.4.4.1. PAIRING TWO MMX™ INSTRUCTIONS ........................................................... 2-19 2.4.4.2. PAIRING AN INTEGER INSTRUCTION IN THE U-PIPE WITH AN MMX™ INSTRUCTION IN THE V-PIPE.......................................................................... 2-20 2.4.4.3. PAIRING AN MMX™ INSTRUCTION IN THE U-PIPE WITH AN INTEGER INSTRUCTION IN THE V-PIPE.......................................................................... 2-20 2.5. ON-CHIP CACHES..................................................................................................... 2-20 2.5.1. Cache Organization................................................................................................ 2-21 2.5.2. Cache Structure...................................................................................................... 2-22 2.5.3. Cache Operating Modes......................................................................................... 2-23 2.5.4. Page Cacheability................................................................................................... 2-25 2.5.4.1. PCD AND PWT GENERATION .......................................................................... 2-25 2.5.5. Inquire Cycles......................................................................................................... 2-28 2.5.6. Cache Flushing....................................................................................................... 2-28 2.5.7. Data Cache Consistency Protocol (MESI Protocol)................................................ 2-28 2.5.7.1. STATE TRANSITION TABLES........................................................................... 2-29 2.5.7.2. PENTIUM® PROCESSOR CODE CACHE CONSISTENCY PROTOCOL......... 2-32 2.6. WRITE BUFFERS AND MEMORY ORDERING......................................................... 2-32 iii 12/19/96 9:13 AM Toc2.doc CONTENTS E Page 2.6.1. External Event Synchronization..............................................................................2-34 2.6.2. Serializing Operations.............................................................................................2-34 2.6.3. Linefill and Writeback Buffers .................................................................................2-35 2.7. EXTERNAL INTERRUPT CONSIDERATIONS ..........................................................2-36 2.8. INTRODUCTION TO DUAL PROCESSOR MODE ....................................................2-37 2.8.1. Dual Processing Terminology.................................................................................2-38 2.8.2. Dual Processing Overview......................................................................................2-38 2.8.2.1. CONCEPTUAL OVERVIEW ...............................................................................2-39 2.8.2.2. ARBITRATION OVERVIEW................................................................................2-40 2.8.2.3. CACHE COHERENCY OVERVIEW ...................................................................2-41 2.9. APIC INTERRUPT CONTROLLER.............................................................................2-43 2.9.1. APIC Configuration Modes .....................................................................................2-46 2.9.1.1. NORMAL MODE.................................................................................................2-46 2.9.1.2. BYPASS MODE..................................................................................................2-46 2.9.1.3. THROUGH LOCAL MODE .................................................................................2-47 2.9.1.4. MASKED MODE .................................................................................................2-47 2.9.1.5. DUAL PROCESSING WITH THE LOCAL APIC .................................................2-48 2.9.2. Loading the APIC ID ...............................................................................................2-48 2.9.3. Response to HOLD.................................................................................................2-49 2.10. FRACTIONAL SPEED BUS........................................................................................2-49 2.11. POWER MANAGEMENT............................................................................................2-52 2.11.1. I/O Instruction Restart.............................................................................................2-52 2.11.2. Stop Clock and AutoHalt Powerdown.....................................................................2-53 2.12. CPUID INSTRUCTION ...............................................................................................2-53 2.13. MODEL SPECIFIC REGISTERS................................................................................2-56
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