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5 Combinatorial Components 5.0 Full Adder Full Subtractor

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5 Combinatorial Components 5.0 Full Adder Full Subtractor 5 Combinatorial Components Use for data transformation, manipulation, interconnection, and for control: • arithmetic operations - addition, subtraction, multiplication and division. • logic operations - AND, OR, XOR, and NOT. • comparison operations - greater than, equal to, and less than. • bit manipulation operations - shift, rotation, extraction, and insertion. • interconnect components - selectors, and buses - used to connect different components together. • conversion components - decoders and encoders - used for conversion between different codes. • universal components - ROMs and programmable-logic arrays (PLAs) - used primarily in the design of control units. 5.0 Full adder x y c c s i i i i+1 i i = xi' yi' ci + xi' yi ci' + xi yi' ci' + xi yi ci 00000 = (xi' yi + xi yi') ci ' + (xi' yi' + xi yi) ci 00101 = (xi ⊕ yi) ci' + (xi ~ yi) ci 01001 = (xi ⊕ yi) ⊕ ci 01110 10001 ci+1 = xi' yi ci + xi yi' ci + xi yi ci' + xi yi ci 10110 = xi yi (ci' + ci) + ci (xi' yi + xi yi') 11010 = xi yi • 1 + ci (xi ⊕ yi) 11111 xi yi XY c i+1 Cout FA Cin ci S si Circuit for Full Adder Full subtractor bin xybout d Comment 0000 0x-bin-y = d = 0-0 = 0 0 0 1 1 1 0-0-1 = borrow 2-1 = 1 0 1 0 0 1 1-0-0=1 with no borrow 0 1 1 0 0 1-0-1=0 with no borrow 1001 1x=0-1=-1 because of bin=1, therefore, borrow 2-1=1. Finally, 1-0=1 1011 0x-bin-y=borrow 2-1-1=0 1 1 0 0 0 1-1-0=0 with no borrow 1111 1x-bin=1-1=0. Then 0-1=borrow 2-1=1 xy 00 01 11 10 xy 00 01 11 10 bin bin 0132x'y 0132 0 1 0 1 1 x'bin 4576 4576 1 1 1 1 ybin 1 1 1 = ′ ′ + + ′ ′ + ′ ′ d x y bin xybin x ybin xy bin = b (x′y′ + xy) + b′ (x′y + xy′) b = x′b + x′y + yb in in out in in = ⊕ ′ + ′ ⊕ bin (x y) bin (x y) = ⊕ ⊕ bin x y xy bin XY bout bout FS bin d d Circuit for Full Subtractor 5.1 Ripple-carry adders x7 y7 x6 y6 x5 y5 x4 y4 x3 y3 x2 y2 x1 y1 x0 y0 c7 c6 c5 c4 c3 c2 c1 cout FA FA FA FA FA FA FA FA c in s7 s6 s5 s4 s3 s2 s1 s0 5.3 Adder / Subtractor x7 y7 x6 y6 x5 y5 x4 y4 x3 y3 x2 y2 x1 y1 x0 y0 S S Function Comment 0 X + Y Addition 1 X + Y ’ + 1 Subtraction c7 c6 c5 c4 c3 c2 c1 c0 cout FA FA FA FA FA FA FA FA f7 f6 f5 f4 f3 f2 f1 f0 5.4 Logic Unit 5.5 Arithmetic-Logic Unit (ALU) a3 b3 a2 b2 a1 b1 a0 b0 S0 S 1 M LE AE LE AE LE AE LE AE FA c 3 FA c 2 FA c 1 FA c 0 c 4 Overflow f3 f2 f1 f0 Arithmetic Extender (AE) The AE modifies the second operand and passes it to the FA to perform the arithmetic. MS1 S0 Function Name Function XYc0 1 0 0 Decrement A – 1 A all 1’s 0 101Add A + BAB 0 1 1 0 Subtract A + B ’ + 1 AB ’1 1 1 1 Increment A + 1 A all 0’s 1 Functional table b i S1S0 00 01 11 10 bi MS1 S0 bi yi 0132 10001 0 1 1 10011 S'0b'i S0 4576 10100 1 1 1 S'1bi S1 10111 M 11001 11010 yi = MS1’bi + MS0’bi’ 11100 11110 Map representation Truth table AE yi yi = MS1’S0’bi’ + MS1’S0’bi + MS1’S0bi + MS1S0’bi’ = MS0’bi’(S1’ + S1) + MS1’bi(S0’+ S0) Schematic diagram = MS0’bi’ + MS1’bi Logic Extender (LE) The logic operations are performed in the logic extender. The FAs are used simply as connections for the outputs. MS1 S0 Function Name Function XYc0 000Complement A ’ A ’00 001AND A AND BA AND B 00 0 1 0 Identity AA00 011OR A OR BA OR B 00 Functional table ai b i MS1 S0 xi Indices in map S0 000 ai’0, 4 S1 001 ai bi 13 M 010 ai 10, 14 011ai + bi 7, 11, 15 1XX ai pass to AE Truth table LE xi Schematic diagram M = 0 M = 1 a b S1S0 00 01 11 10 00 01 11 10 i i ai bi 01320132 00 1 S0 45764576 01 1 1 S1 M 12 1315 14 12 1315 14 11 11 1111 1 8911 10 8911 10 10 111 111 LE xi = M’S1’ S0’ai’ + M’S1 S0bi + S0 ai bi + S1 ai + Mai xi Map representation Simplified schematic diagram Carry in signal c0 – Notice that in the AE functional table, c0 = MS1 Overflow signal c4 – The carry-out of the most significant bit represents an overflow in the case of unsigned arithmetic. Overflow – The XOR of the carry-outs of the two most significant bits represents the overflow in the case of 2’s complement arithmetic. 5.6 Decoders / Demultiplexers To enable only one of n components. A1 A0 EA1 A0 C3 C2 C1 C0 0 ×× 0000 E Decoder 1000001 3210 1010010 1100100 C3C2C1C0 1111000 2-to-4 Decoder E A 2 A 0 A0 E 10 E E 10 10 E E E E 10 10 10 10 C7C6 C5C4 C 3 C 2 C 1 C 0 3-to-8 decoder implemented with 1-to-2 decoders 5.7 Selectors / Multiplexers (MUX) D3D2D1D0 S S Y 1 0 3210 00D 0 S1 MUX 01D1 S0 10D2 11D3 Y 4-to-1 MUX D7D6 D5D4 D 3 D 2 D 1 D 0 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 10 10 10 10 S S S S 0 1 S 0 2 3 S 0 S 1 4 5 S Decoder 6 2 7 10 10 S S S1 10 S2 S y y 8-to-1 mux implemented with 2-to-1 muxes 8-to-1 mux implemented with a decoder 5.8 Buses A bus is for connecting several components together, however, only one component can send data to the bus at any one time. To construct a bus, use a tristate driver, whose output provides three different values, 0, 1, and Z. The value Z represents a high-impedance state which can be thought of as a disconnection from the bus. E0 Y D E Y Bus 0 Z E1 Y 1 D D 5.9 Priority Encoders A priority encoder has: • n inputs, Dn-1, … D0, m • m outputs, Am-1, … A0, where n = 2 , which represents the index (decimal value) of the most significant input bit Di that has a value equal to 1. • an additional output call Any, which will be 1 whenever any of the inputs has a value that is different from 0. 2-to-1 priority encoder D1 D0 D1 D0 A0 Any 1 0 000 0 Encoder 010 1 1X1 1 Any A0 4-to-2 priority encoder D3 D2 D1 D0 A1 A0 Any D3 D2 D1 D0 000000 0 3 2 1 0 000100 1 Encoder 001X01 1 01XX10 1 Any A1 A0 1XXX 1 1 1 5.10 Magnitude Comparators A comparator compares two positive integers X and Y and then generates two boolean results G and L as follows: Test GL X > Y 1 X ≤ Y 0 X < Y 1 X ≥ Y 0 X ≠ Y 11 X = Y 00 For the n-bit integers X and Y, we compare them one bit at a time, starting with the most significant bit, Gi = (xi > yi) or [(xi = yi) and (Gi-1 > Li-1)] Li = (xi < yi) or [(xi = yi) and (Gi-1 < Li-1)] a 0 b 0 00 01 11 10 a1b1 x1 y1 x0 y0 GL 0132 000000 00 1 000101 4576 001010 01 001100 12 1315 14 11 1 010001 8911 10 010101 10 1 111 011001 011101 100010 G = a1b1’ + a1a0b0’ + b1’a0b0’ 100110 101010 101110 110000 a0b0 00 01 11 10 a b 110101 1 1 0132 111010 00 1 111100 4576 01 1 1 1 1 12 1315 14 x1 y1 x0 y0 11 1 8911 10 10 G L = a1’b1 + a1’a0’b0 + b1a0’b0 L 5.11 Shifters and Rotators Use selectors to implement. S2 S1 S0 Y Comment 00×DNo shift 01× Not used 1 0 0 ShiftLeft(D) Shift left 1 0 1 RotateLeft(D) Rotate left 1 1 0 ShiftRight(D) Shift right 1 1 1 RotateRight(D) Rotate right d3 d2 d1 d0 Left Input Right Input 1 0 1 0 Selector S0 Selector 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 Selector Selector Selector Selector S 1 S 2 y3 y2 y1 y0 5.12 Read-Only Memories ROMs can be thought of as a universal logic element that is able to implement concurrently several different Boolean functions that are defined on the same set of variables. A 16 × 4 ROM can implement 4 functions. Programmable ANDs and ORs. a abcd b c = d a abcd b c = d Use a 16 × 4 ROM to implement the following two functions: f0 = w x' y' z + w x' y z' + w' x y' z' f1 = x y + w' z + w x' y OR array 0 1 2 3 z A0 4 5 y A1 6 4-to-16 7 x A2 decoder 8 9 w A3 10 11 12 13 14 15 f 1 f 0 5.13 Programmable Logic Arrays (PLA) ROMs are not very efficient when we use them to implement sparse functions, i.e.
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