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An Automatable Workflow to Analyze and Secure

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An Automatable Workflow to Analyze and Secure AN AUTOMATABLE WORKFLOW TO ANALYZE AND SECURE INTEGRATED CIRCUITS AGAINST POWER ANALYSIS ATTACKS by KEVIN PERERA Submitted in partial fulfillment of the requirements For the degree of Master of Science Thesis Advisor: Dr. Daniel G. Saab Department of Electrical Engineering and Computer Science CASE WESTERN RESERVE UNIVERSITY May, 2017 CASE WESTERN RESERVE UNIVERSITY SCHOOL OF GRADUATE STUDIES We hereby approve the thesis of Kevin Perera Candidate for the degree of Master of Science Committee Chair Dr. Daniel G. Saab Committee Member Dr. Christos Papachristou Committee Member Dr. Ming-Chun Huang Date of Defense March 31st 2017 *We also certify that written approval has been obtained for any proprietary material contained therein. Table of Contents List of Tables ....................................................................................................................... 4 List of Figures ...................................................................................................................... 5 Acknowledgements ............................................................................................................. 7 Abstract ............................................................................................................................... 8 1 Introduction ................................................................................................................. 9 1.1 Focus of Thesis ................................................................................................... 11 2 Background ................................................................................................................ 12 2.1 Side Channel Attacks .......................................................................................... 12 2.1.1 Power Analysis Attacks ............................................................................... 13 2.1.1.1 Simple Power Analysis (SPA) ............................................................... 15 2.1.1.2 Differential Power Analysis (DPA). ...................................................... 16 2.2 AES Algorithm ..................................................................................................... 20 2.2.1 SubBytes sub stage ..................................................................................... 22 2.2.2 ShiftRows sub stage .................................................................................... 23 2.2.3 MixColumns sub stage ................................................................................ 24 2.2.4 AddRoundKey sub stage and Rijndael’s key schedule ................................ 25 2.2.5 ENS Method ................................................................................................ 26 2.3 Testability ........................................................................................................... 26 1 2.3.1 Controllability and Observability ................................................................ 27 2.3.1.1 SCOAP (Sandia Controllability/Observability Analysis Program) ........ 28 3 Literature Review ...................................................................................................... 32 3.1 Security-Aware Design Methodology and Optimization ................................... 32 3.2 Dynamic Voltage and Frequency Scaling ........................................................... 33 3.3 Converter Reshuffling Power Management ...................................................... 34 3.4 Inductive Integrated Voltage Regulator ............................................................. 35 3.5 Signal Independent Power Consumption CMOS Logic ...................................... 37 3.6 Differential Pass Transistor Precharge Logic ...................................................... 38 3.7 Dual Voltage Single Rail Logic ............................................................................. 40 3.8 Masked Gates ..................................................................................................... 41 4 Preliminary Gate Architecture Experiments.............................................................. 43 4.1 Conventional Gates ............................................................................................ 44 4.2 Smaller Feature Length Technology ................................................................... 46 4.3 Complementary Output Gates ........................................................................... 47 4.3.1 Padded Complimentary Gates .................................................................... 50 5 Gate Substitution Workflow ...................................................................................... 51 5.1 Synthesis Stage and Analysis Stage .................................................................... 52 5.2 Substitution Stage .............................................................................................. 53 2 6 Application of Workflow ............................................................................................ 55 6.1 RTL Design .......................................................................................................... 55 6.2 Synthesis and Analysis ........................................................................................ 56 6.3 Substitution and Conversion to a Netlist ........................................................... 58 6.4 SPICE Simulation ................................................................................................. 59 6.5 Experiment Results ............................................................................................. 61 7 Future Work ............................................................................................................... 67 8 Conclusion ................................................................................................................. 68 Appendices ........................................................................................................................ 69 Appendix I: 0.5 micron SPICE Models ........................................................................... 69 Appendix II: 45 nanometer SPICE Models ..................................................................... 70 Appendix III: Conventional Gate Experiment 1 Power Trace ........................................ 74 Appendix IV: Conventional Gate Experiment 2 Power Trace ....................................... 76 Appendix V: Conventional Gate 45nm Power Trace ..................................................... 78 Appendix VI: Complimentary Gate Power Trace .......................................................... 80 Appendix VII: Complimentary Gate 45nm Power Trace ............................................... 82 Appendix VIII: Padded Complimentary Gate Power Trace ........................................... 84 References ........................................................................................................................ 86 3 List of Tables Table 2.1 S-Box lookup table [11] ..................................................................................... 23 Table 5.1 Algorithm Stats and System Info. ...................................................................... 53 Table 6.1 AES Circuit Statistics .......................................................................................... 56 Table 6.2 Changed SPICE options (descriptions from LTSpice help [33]) ......................... 60 Table 6.3 Simulation Times and System information ....................................................... 60 4 List of Figures Figure 2.1 Power consumption of a RSA algorithm that exposes its data [4] .................. 15 Figure 2.2 Sample DPA traces [3] ...................................................................................... 17 Figure 2.3 Flow diagram of the AES algorithm [9] ............................................................ 21 Figure 2.4 Illustration of Subbytes sub stage [10] ............................................................ 22 Figure 2.5 Illustration of the ShiftRows sub stage [10] ..................................................... 24 Figure 2.6 Illustration of Rjindael’s key schedule [11] ...................................................... 25 Figure 2.7 Illustration of the ENS method for the AES algorithm [12] ............................. 26 Figure 2.8 Calculations of combinational controllability for common gates [19] ............ 29 Figure 2.9 Calculations of combinational observability for common gates [19] .............. 30 Figure 3.1 Flow of the proposed algorithm [20] ............................................................... 33 Figure 3.2 DVFS architecture [21] ..................................................................................... 34 Figure 3.3 Power attack and proposed countermeasure [23] .......................................... 36 Figure 3.4 Generic N gate and AND/NAND gate using SABL [24] ..................................... 38 Figure 3.5 (A) Power trace comparison (B) XOR gate in DPPL [25] .................................. 39 Figure 3.6 DSDL AND gate [27] ......................................................................................... 41 Figure 3.7 Masked AND Gate [29] .................................................................................... 42 Figure 4.1 Gate test structure ........................................................................................... 43 Figure 4.2 XOR gate ..........................................................................................................
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