Ez80f91 Module Product Specification

eZ80F915050MODG

eZ80F91 Module

Product Specification

PS019312-0907

Copyright ©2007 by Zilog®, Inc. All rights reserved. www.zilog.com Warning: DO NOT USE IN LIFE SUPPORT LIFE SUPPORT POLICY ZILOG'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION.

As used herein Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness.

Document Disclaimer ©2007 by Zilog, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZILOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZILOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this document has been verified according to the general principles of electrical and mechanical engineering. Z8, Z8 Encore!, Z8 Encore! XP, Z8 Encore! MC, Crimzon, eZ80, ZNEO, Zdots, and eZ80AcclaimPlus! are trademarks or registered trademarks of Zilog, Inc. All other product or service names are the property of their respective owners.

PS019312-0907 eZ80F91 Module Product Specification

iii

Revision History

Each instance in the Revision History reflects a change to this document from its previous revision. For more details, refer to the corresponding pages or appropriate links given in the table below.

Revision Date Level Description Page No September 12 Changed eZ80F915050MOD to i 2007 eZ80F915050MODG July 2006 11 Removed PRELIMINARY All July 2004 10 Formatted to current publication standards All Part number change to AMD MII in Ethernet PHY 12 and RJ45 Connector section Part number change to internal crystal at jumper 21 location Y3 in Table 6 March 2004 09 Updated Schematics 24 Dec 2003 08 Updated eZ80F91 Module Bill of Materials 21

PS019312-0907 Revision History eZ80F91 Module Product Specification

Table of Contents

eZ80F91 Module ...... 1 eZ80F91 Module Features ...... 1 eZ80F91 Controller Features ...... 2 Block Diagram ...... 3

Pin Description ...... 4 Peripheral Bus Connector ...... 4 Input/Output Connector ...... 7

Onboard Component Description ...... 12 Logic-Level Input/Outputs ...... 12 Onboard Battery Backup ...... 12 Ethernet PHY and RJ45 Connector ...... 12 Ethernet LEDs ...... 13 Fast Buffer (U10) ...... 13 Memory ...... 15 IrDA Transceiver ...... 15 Reset Generator ...... 16 Serial Interface Ports ...... 16 Physical Dimensions ...... 16 Absolute Maximum Ratings ...... 19 eZ80F91 Module Bill of Materials ...... 21

Schematics ...... 24

Customer Support ...... 27

PS019312-0907 Table of Contents eZ80F91 Module Product Specification

1 eZ80F91 Module

Zilog’s eZ80F91 Module is a compact, high-performance Ethernet module specially designed for the rapid development and deployment of embedded systems requiring control and internet/intranet connectivity. This expandable module is powered by Zilog’s latest power-efficient, high-speed, optimized pipeline architecture eZ80F91 microcontroller, a member of Zilog’s family of eZ80Acclaim! Flash microcontrollers. The eZ80F91 is a high-speed single-cycle instruction-fetch microcontroller, which operates with a clock speed of 50 MHz. It can also operate in Z80®-compatible addressing mode (64 KB) or full 24-bit addressing mode (16 MB). The rich-peripheral set of the eZ80F91 Module makes it suitable for a variety of applications including industrial control, IrDA connectivity, communication, security, automation, point-of-sale terminals, and embedded networking applications. eZ80F91 Module Features

Features of eZ89F91 Module include: • Factory-default operating clock frequency at 50 MHz • 10/100 Base-T Ethernet PHY with RJ45 connector • 512 KB fast SRAM • 256 KB on-chip Flash memory • 1 MB OFF-chip NOR Flash memory • Battery-backed Real-time clock • Input/Output connector which provides 32 general-purpose 5 V-tolerant I/O pinouts • Zilog’s industry-leading IrDA transceiver—Zilog ZHX1810 • Onboard connector provides I/O bus for external peripheral connections (IRQ, CS, 24 address, and 8 data) • Low-cost connection to carrier board via two 2 x 30 pin headers • Small footprint 63.5 mm x 78.7 mm • 3.3 V power supply • Standard operating temperature range: 0 ºC to +70 ºC

PS019312-0907 eZ80F91 Module eZ80F91 Module Product Specification

2 eZ80F91 Controller Features

Features of eZ80F91 Controller include: • The eZ80F91 device contains 256 KB of Flash memory and 8 KB of SRAM • Single-cycle instruction fetch, high-performance, pipelined eZ80 CPU core • 10/100 Mbps Ethernet MAC with 8 KB frame buffer • Low power features including SLEEP mode, HALT mode, and selective peripheral power-down control • Two UARTs with independent baud rate generators and support for 9-bit operation • SPI with independent clock generator • I2C with independent clock generator • Infrared data association (IrDA)-compliant infrared encoder/decoder • New DMA-like eZ80 instructions for efficient block data transfer • External interface with 4 chip selects, individual wait state generators, and an external WAIT input pin—supports Intel- and Motorola-style buses • Flexible-priority vectored interrupts (both internal and external) and interrupt controller • Real-time clock with on-chip 32 kHz oscillator, selectable 50/60 Hz input, and separate VDD pin for battery backup • Four 16-bit Counter/Timers with prescalers and direct input/output drive • Watchdog Timer (WDT) • 32 bits of general-purpose input/output (GPIO) • JTAG and ZDI debug interfaces • 144-pin LQFP package • 3.0–3.6 V supply voltage with 5 V tolerant inputs • Standard operating temperature range: 0 ºC to +70 ºC

PS019312-0907 eZ80F91 Module eZ80F91 Module Product Specification

Block Diagram Figure 1 illustrates the block diagram of eZ80F91 Module.

32KHz XTAL

eZ80F91 GPIO BATTERY (256KB FLASH, Bus (JP2)

8KB SRAM, External GPIO EMAC) CONTROL & ADDRESS BUS 50MHz XTAL (JP1) DATA BUS External Perpheral Bus MII CS0

Ethernet AM79874

FLASH

(1 MB, CS0) BUFFER FAST

SRAM (512 KB, CS1)

IrDA IrDA

Figure 1. eZ80F91 Module Functional Block Diagram

PS019312-0907 eZ80F91 Module eZ80F91 Module Product Specification

Pin Description

Peripheral Bus Connector

Figure 2 illustrates the pin layout of the 60-pin Peripheral Bus Connector (JP1) of the eZ80F91 Module. The eZ80 development platform, however, features a 50-pin connector. The eZ80F91 Module is designed to interface pin 60 of its JP1 connector to pin 50 of the eZ80 development platform’s JP1 connector so that pins 1–10 of the eZ80F91 Module overlap the edge of the eZ80 development platform. Table 1 on page 5 describes the pins and their functions.

Figure 2. eZ80F91 Module Peripheral Bus Connector Pin Configuration—JP1

PS019312-0907 Pin Description eZ80F91 Module Product Specification

Note: All signals with an overline are active Low. For example, B/W, for which WORD is active Low, and B/W, for which BYTE is active Low.

Table 1. eZ80F91 Module Peripheral Bus Connector Pin Identification*

Pull Pin No Symbol Up/Down* Signal Direction Comments 1 Reserved 2 Reserved 3 Reserved 4 Reserved 5TRSTN Input Reset for on-chip instrumentation (OCI). 6 Reserved 7 F91_WE PU 10 kΩ Input A Low enables a Write to on-chip Flash memory. If this pin is unconnected, on-chip Flash memory is write-protected. 8 Reserved

9GND VSS/Ground (0 V).

10 VCC 3.3 V supply input pin. 11 A6 Bidirectional 12 A0 Bidirectional 13 A10 Bidirectional 14 A3 Bidirectional

15 GND VSS/Ground (0 V).

16 VCC 3.3 V supply input pin. 17 A8 Bidirectional 18 A7 Bidirectional 19 A13 Bidirectional 20 A9 Bidirectional 21 A15 Bidirectional 22 A14 Bidirectional 23 A18 Bidirectional 24 A16 Bidirectional

PS019312-0907 Pin Description eZ80F91 Module Product Specification

Table 1. eZ80F91 Module Peripheral Bus Connector Pin Identification* (Continued)

Pull Pin No Symbol Up/Down* Signal Direction Comments 25 A19 Bidirectional

26 GND VSS/Ground (0 V). 27 A2 Bidirectional 28 A1 Bidirectional 29 A11 Bidirectional 30 A12 Bidirectional 31 A4 Bidirectional 32 A20 Bidirectional 33 A5 Bidirectional 34 A17 Bidirectional 35 Reserved 36 DIS_Flash PU 10 kΩ Input A Low disables onboard Flash memory. Flash is enabled if DIS_Flash is not connected; CMOS Input 3.3 V (5 V tolerant). 37 A21 Bidirectional

38 VCC 3.3 V supply input pin. 39 A22 Bidirectional 40 A23 Bidirectional 41 CS0 Output 42 CS1 Output 43 CS2 Output 44 D0 PU 4 kΩ Bidirectional 45 D1 PU 4 kΩ Bidirectional 46 D2 PU 4 kΩ Bidirectional 47 D3 PU 4 kΩ Bidirectional 48 D4 PU 4 kΩ Bidirectional 49 D5 PU 4 kΩ Bidirectional

50 GND VSS/Ground (0 V). 51 D7 PU 4 kΩ Bidirectional

PS019312-0907 Pin Description eZ80F91 Module Product Specification

Table 1. eZ80F91 Module Peripheral Bus Connector Pin Identification* (Continued)

Pull Pin No Symbol Up/Down* Signal Direction Comments 52 D6 Bidirectional 53 MREQ Bidirectional 54 IORQ Bidirectional

55 GND VSS/Ground (0 V). 56 RD Bidirectional 57 WR Bidirectional 58 INSTRD Output 59 BUSACK Output 60 BUSREQ PU 2 kΩ Input *Notes 1.External capacitive loads on RD, WR, IORQ, MREQ, D0–D7, and A0–A23 must be below 10 pF to satisfy timing requirements for the CPU. 2.All unused inputs must be pulled to either VDD or GND, depending on their inactive levels, to reduce power consumption and to reduce noise sensitivity. 3.All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted.

Input/Output Connector

Figure 3 on page 8 illustrates the pin layout of the 60-pin I/O Connector (JP2) of the eZ80F91 Module. However, the eZ80 development platform features a 50-pin connector. The eZ80F91 Module is designed to interface pin 60 of its JP2 connector to pin 50 of the eZ80 development platform’s JP2 connector so that pins 1–10 of the eZ80F91 Module overlap the edge of the eZ80 development platform. Table 2 on page 8 describes the pins and their functions.

PS019312-0907 Pin Description eZ80F91 Module Product Specification

Figure 3. eZ80F91 Module Input/Output Connector Pin Configuration—JP2

Table 2. eZ80F91 Module Input/Output Connector Pin Identification*

Pull Signal Pin No Symbol Up/Down Direction Comments 1 PA7 Bidirectional 2 PA6 Bidirectional 3 PA5 Bidirectional 4 PA4 Bidirectional 5 PA3 Bidirectional 6 PA2 Bidirectional 7 PA1 Bidirectional 8 PA0 Bidirectional

PS019312-0907 Pin Description eZ80F91 Module Product Specification

Table 2. eZ80F91 Module Input/Output Connector Pin Identification* (Continued)

Pull Signal Pin No Symbol Up/Down Direction Comments

9VCC 3.3 V supply input pin.

10 GND VSS/Ground (0 V). 11 PB7 Bidirectional 12 PB6 Bidirectional 13 PB5 Bidirectional 14 PB4 Bidirectional 15 PB3 Bidirectional 16 PB2 Bidirectional 17 PB1 Bidirectional 18 PB0 Bidirectional

19 GND VSS/Ground (0 V). 20 PC7 Bidirectional 21 PC6 Bidirectional 22 PC5 Bidirectional 23 PC4 Bidirectional 24 PC3 Bidirectional 25 PC2 Bidirectional 26 PC1 Bidirectional 27 PC0 Bidirectional 28 PD7 Bidirectional 29 PD6 Bidirectional

30 GND VSS/Ground (0 V). 31 PD5 Bidirectional 32 PD4 PD 4 kΩ Bidirectional 33 PD3 Bidirectional 34 PD2 Bidirectional 35 PD1 Bidirectional 36 PD0 Bidirectional 37 TDO Output JTAG Data Output pin.

PS019312-0907 Pin Description eZ80F91 Module Product Specification

Table 2. eZ80F91 Module Input/Output Connector Pin Identification* (Continued)

Pull Signal Pin No Symbol Up/Down Direction Comments 38 TDI/ZDA Input JTAG Data Input pin.

39 GND VSS/Ground (0 V). 40 TRIGOUT Output Active High trigger event indicator. 41 TCK/ZCL PU 10 kΩ Input JTAG Input. High on reset enables ZDI mode; Low on reset enables OCI debug. 42 TMS PU 10 kΩ Input JTAG Test Mode Select Input.

43 RTC_VDD RTC supply. For proper operation of the eZ80F91 Module, this pin must be connected to the same power source that powers the module (as is done on the Zilog development platform). 44 EZ80CLK Output Synchronous CPU clock output. 45 I2CSCL PU 4 kΩ Bidirectional I2C Bus Clock.

46 GND VSS/Ground (0 V). 47 I2CSDA PU 4 kΩ Bidirectional I2C Data Clock.

48 GND Power VSS/Ground (0 V). 49 FlashWE PU 10 kΩ Input A Low enables a Write to external Flash memory boot block area. If this pin is unconnected, the Flash memory boot block area is write-protected.

50 GND VSS/Ground (0 V). 51 CS3 Output Used on the eZ80190, eZ80L92, eZ80F92, eZ80F93 devices and connected to the CS8900 EMAC. 52 DIS_IRDA PU 10 kΩ Input A Low disables the onboard IRDA transceiver to use PC0/PC1 UART pins externally. 53 RESET PU 2 kΩ Bidirectional Reset Output from module or push-button reset. 54 WAIT PU 2 kΩ Input Driving the WAIT pin Low forces the CPU to provide additional clock cycles for an external peripheral or external memory to complete its Read or Write operation.

55 VCC 3.3 V supply input pin.

56 GND VSS/Ground (0 V).

PS019312-0907 Pin Description eZ80F91 Module Product Specification

Table 2. eZ80F91 Module Input/Output Connector Pin Identification* (Continued)

Pull Signal Pin No Symbol Up/Down Direction Comments 57 HALT_SLP Output, Active A Low on this pin indicates that the CPU enters Low either HALT or SLEEP mode because of execution of either a HALT or SLP instruction. 58 NMI PU 10 kΩ Schmitt Trigger The NMI input is a higher priority input than the Input, Active maskable interrupts. It is always recognized at Low the end of an instruction, regardless of the state of the interrupt enable control bits. This input includes a Schmitt trigger to allow RC rise times. This external NMI signal is combined with an internal NMI signal generated from the WDT block before being connected to the NMI input of the CPU.

59 VCC 3.3 V supply input pin. 60 Reserved NC Reserved—No Connection. *Notes 1.External capacitive loads on RD, WR, IORQ, MREQ, D0–D7, and A0–A23 must be below 10 pF to satisfy timing requirements for the CPU. 2.All unused inputs must be pulled to either VDD or GND, depending on their inactive levels, to reduce power consumption and to reduce noise sensitivity. 3.All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted.

PS019312-0907 Pin Description eZ80F91 Module Product Specification

Onboard Component Description

Logic-Level Input/Outputs

The I/O connector features 32 general-purpose 3.3 V CMOS I/O pins that can be used as outputs or inputs interfacing to external logic. All I/Os are 5 V tolerant. Some of the general-purpose I/O pins support dual mode functions (SPI, Timer I/O, UARTs, and bit I/O with edge- or level-triggered interrupt functions on each pin). For more information on eZ80F91 dual modes, refer to eZ80F91 Product Specification (PS0192).

Onboard Battery Backup

An onboard Panasonic VL-1220-1VC 3 V Lithium battery powers the 32 kHz real-time clock when external power is removed. The battery is charged through diode CR1 and resistor R28 when external power is applied to the board.

Ethernet PHY and RJ45 Connector

The eZ80F92 Ethernet Module contains Advanced Micro Devices’ Am79C874 Media- Independent Interface (MII) and a HALO RJ45 with integrated magnetics (transformer and common-mode chokes) and two LED indicators. The MII enables different modes of Ethernet communication, configurable by resistors R19, R21, R23, and R24. The eZ80F92 Ethernet Module is shipped with all four resistors installed. Table 3 lists the available resistor settings and is excerpted from the Am79C874 data sheet published by AMD.

Table 3. eZ80F92 Ethernet Module MII Resistor Configuration

R24 R19 R23 R21 ANEG (Tech[2]) (Tech[1]) (Tech[0]) Speed Full-Duplex ANEG-EN Capabilities ANEG IN IN IN IN Yes1 Yes1 No All Disabled IN IN IN OUT No No No 10HD Disabled IN IN OUT IN No No No 100HD Disabled IN IN OUT OUT No No No 100HD Disabled IN OUT IN IN Yes1 Yes1 No All Disabled IN OUT IN OUT No No No 10FD Disabled IN OUT OUT IN No No No 100FD Disabled

PS019312-0907 Onboard Component Description eZ80F91 Module Product Specification

Table 3. eZ80F92 Ethernet Module MII Resistor Configuration (Continued)

R24 R19 R23 R21 ANEG (Tech[2]) (Tech[1]) (Tech[0]) Speed Full-Duplex ANEG-EN Capabilities ANEG IN OUT OUT OUT No No No 100FD Disabled OUTINININYes2 Yes2 Yes3 None Enabled OUT IN IN OUT Yes2 Yes2 Yes3 10HD Enabled OUT IN OUT IN Yes2 Yes2 Yes3 100HD Enabled OUT IN OUT OUT Yes2 Yes2 Yes3 100HD, Enabled 10HD OUT OUT IN IN Yes2 Yes2 Yes3 None Enabled OUT OUT IN OUT Yes2 Yes2 Yes3 10FD/HD Enabled OUT OUT OUT IN Yes2 Yes2 Yes3 100FD/HD Enabled OUT OUT OUT OUT Yes3 Yes2 Yes3 All Enabled *Notes 1.MII Register 0 (Speed and Duplex Bits) must be set by a MAC to achieve a link. 2.When autonegotiation is enabled, these bits are written but will be ignored by PHY. 3.The advertised abilities of MII Register 4 cannot exceed the abilities of MII Register 1. Autonegotiation must always be enabled.

Ethernet LEDs The Ethernet connection is provided by the HALO RJ45 connector. It consists of two green LEDs that are located next to each other on the eZ80F91 Module. When PHY is receiving data, the left LED is ON. When the PHY is transmitting data, the right LED is ON.

Fast Buffer (U10)

The eZ80F91 Module’s fast buffer (see Figure 1 on page 3) exists to prevent bus contention that occurs because of slow turn-off time of the module’s external Flash and the fast bus turn-around time of the eZ80F91 (generic feature of the eZ80 family when it is used in NATIVE mode). The problem related to bus contention when using eZ80 family of the microprocessors in NATIVE eZ80 mode is explained below, see Figure 4 on page 14. For more details, refer to eZ80F91 Product Specification (PS0192). Bus contention occurs when two or more devices drive a common bus. The eZ80F91's CS0 drives the Flash CE. After the access to Flash, CS0 is driven High a maximum of 8.8 ns after the next rising edge of the Clock (T6 in Figure 4). The Flash turn-off time (TOD) is 25 ns, which is the time from OE or CE going High to the Flash output drivers going into

PS019312-0907 Onboard Component Description eZ80F91 Module Product Specification

High-Z mode. That is, after the end of the eZ80F91 Read access to Flash, it takes 8.8 ns+25 ns = 33.8 ns before Flash stops driving the data bus. At this point, the eZ80F91 device is already well into the next bus cycle. Consider the next cycle is Memory Write. During the Memory Write cycle, data (output) from the eZ80F91 device is valid not later than T3 = 7.5 ns, and the Write pulse is asserted not later than 4.5 ns after the falling edge of the Clock (14.5 ns from the Rising edge if Clock is 50 MHz). It means that during TCON = (33.8 ns – 7.5 ns) = 26.3 ns; two devices drive the common Data Bus—the eZ80F91 device and Flash. In turn, data that is being written during the Write operation might be corrupted. The part used to isolate a slow Flash data bus from a fast eZ80F91 bus has 5.5 ns turn-off time, which reduces 25 ns part of the TCON to 5.5 ns. As a result, bus contention still occurs, but its duration is not 26.3 ns, as the following equation explains: Time of contention= () 8.8 ns– 7.5 ns+ 5.5 ns = 6.8 ns

Data being written is not corrupted because the Write pulse is not yet asserted.

Clock T3

-CS0

F91 Data Data IN Data OUT Bus

-RD

Bus contention

Tod FLash Data Bus

-CS1

-WR

Figure 4. Bus Contention without the eZ80F91 Module Fast Buffer Feature

PS019312-0907 Onboard Component Description eZ80F91 Module Product Specification

Memory

The eZ80F91 Module contains external Flash memory and the eZ80F91 MCU contains internal Flash memory. To allow Read/Write access to Flash memory on the eZ80F91 Module, there are two signals provided on connectors JP1 and JP2. A jumper JP3 on the module enables programming of on-chip Flash. There is also a signal that duplicates the function of this jumper. Table 4 describes the states of the signals and the status of the jumper for different modes.

Table 4. Flash Memory Programming Signals and Jumpers

Signal/Jumper Function State/Status DIS_FLASH Controls Read/Write access to eZ80F91 Module external Flash When Low, access memory is enabled FlashWE Controls Write operations to the boot block of eZ80F91 Module When Low, Write is external Flash memory enabled JP3 Controls Write access to eZ80F91 MCU on-chip Flash memory When IN, Write is enabled F91_WE Controls Write access to eZ80F91 MCU on-chip Flash memory When Low, Write is enabled

The external Flash memory of eZ80F91 Module has an access time of 100 ns. At least five wait states must be added to the cycle when accessing external Flash at 50 MHz clock speed. eZ80F91 MCU on-chip Flash is faster; its minimum access time is 60 ns, which requires only three wait states at 50 MHz. There is 512 KB of fast SRAM on the eZ80F91 Module. Access time is 12 ns, which requires one wait-state access. The eZ80F91’s on-chip SRAM is used with zero wait states.

IrDA Transceiver

An onboard IrDA transceiver (Zilog ZHX1810) is connected to PD0 (TX), PD1 (RX), and PD2 (Shutdown, R_SD). The IrDA transceiver is of the LED type 870 nm Class 1. The receiver supply current is 90 µA to 150 µA and the transmitter supply current is 260 mA when the LED is active. The IrDA transceiver is accessible via the IrDA controller attached to UART0 on the eZ80F91 device. The UART0 console and the IrDA transceiver cannot be used simultaneously.

PS019312-0907 Onboard Component Description eZ80F91 Module Product Specification

To use the UART0 for console or to save power, the transceiver is disabled by the software or by an off-board signal when using the proper jumper selection. The transceiver is disabled by setting PD2 (IR_SD) High or by pulling the DIS_IRDA pin on the I/O connector Low. The shutdown is used for power savings. To enable the IrDA transceiver, DIS_IRDA is left floating and PD2 is set to Low.

Reset Generator

The onboard Reset Generator Chip performs reliable Power-on reset. The chip generates a reset pulse with a duration of 200 ms if the power supply drops below 2.93 V. This reset pulse ensures that the board always starts in a defined condition. The RESET pin on the I/O connector reflects the status of the RESET line. It is a bidirectional pin for resetting external peripheral components or for resetting the eZ80F91 Module with a low-impedance output (for example, a 100 Ω pushbutton).

Serial Interface Ports

The CPU contains two UARTs with programmable baud rate generators. UART0 is connected to GPIO PD[0:7] on the I/O connector. UART1 is connected to GPIO PC[0:7] on the I/O connector. Note: Do not connect an RS232 interface without level shifters. There are no RS232-level shifters on the eZ80F91 Module.

Physical Dimensions

The footprint of the eZ80F91 Module PCB is 63.5 mm x 78.7 cm. With an RJ-45 Ethernet connector, the overall height is 25 mm, see Figure 5 on page 17.

PS019312-0907 Onboard Component Description eZ80F91 Module Product Specification

16.5 mm

56.0 mm

JP1 eZ80F91 MODULE JP2 1 2 1 R15 R14 R23 R21 R16 R13 Y1 R24 R19 R25 R28

U6 +

P2 R17 CR1 JP3 R18 R36 ISO R22 VL1 R20 ZiLOG PCA: 99C0879-001 U8 COPYRIGHT ZiLOG XTOOLS 2002

Y2 78.7 mm C18 C19 C20 C21

C40 C22 R37 U1 Y3 U4 C12 C11 R3 C3

R4 R10 R6 U2 C42 C1 R29 U3

31.8 mm

63.5 mm

Figure 5. Physical Dimensions of the eZ80F91 Module

PS019312-0907 Onboard Component Description eZ80F91 Module Product Specification

Figure 6 illustrates the top layer silk-screen of the eZ80F91 Module.

JP1 eZ80F91 MODULE JP2 1 2 1 R15 R14 R23 R21 R16 R13 Y1 R24 R19 R25 R28

U6 +

P2 R17 CR1 JP3 R18 R36 ISO R22 VL1 R20 ZiLOG PCA: 99C0879-001 U8 COPYRIGHT ZiLOG XTOOLS 2002

Y2 C18 C19 C20 C21

C40 C22 R37 U1 Y3 U4 C12

C11 R3 C3

R4 R10 R6 U2 C42 C1 R29 U3

Figure 6. eZ80F91 Module—Top Layer

PS019312-0907 Onboard Component Description eZ80F91 Module Product Specification

Figure 7 illustrates the bottom layer silk-screen of the eZ80F91 Module.

JP2 R35 R34 JP1 DJP 2002 1 2

C7 C16 C13

C14

C39 C51 C52 C53 R11 R33 C50 R31 R32 C17 C15 C49 C44 C48 C45

C47 C46

C34 C35 C33 C26 C29 C36 C25 L1 C27 U9

C32 C9

C38 C24 C30 C31 R27 C8 C10

R9 C28

C5 R26 C23 R8

R7 C6 U10 C43 R2 C37

R30

R12 C41 R5

C2 MADE IN U.S.A. ZiLOG FAB: 98C0879-001 REV A

Figure 7. eZ80F91 Module—Bottom Layer

Absolute Maximum Ratings Stresses greater than those listed in Table 5 on page 20 causes permanent damage to the device. These ratings are stress ratings only. Operation of the device at any condition outside those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. For improved reliability, unused inputs must be tied to one of the supply voltages (VDD or VSS).

PS019312-0907 Onboard Component Description eZ80F91 Module Product Specification

Table 5. Absolute Maximum Ratings

Parameter Minimum Maximum Units Standard operating temperature 0 +70 ºC Storage temperature –45 +85 ºC Operating Humidity (RH @ 50 ºC) 25% 90% Operating Voltage — 3.6 V

PS019312-0907 Onboard Component Description eZ80F91 Module Product Specification

eZ80F91 Module Bill of Materials Table 6 lists the installed components of the eZ80F91 Module.

Table 6. Bill of Materials for the eZ80F91 Module

Jumper Part Number Part Name Quantity Location Manufacturer 98C0879-001 Fab, eZ80F91 Module, Rev. B 1 — Prime Technologies 35-0180-12 IC, SRAM, 512Kx8, 12 ns, 3 V, 36-SOJ 1 U8 Alliance Semi. AS7C34096-12JC 35-0016-05 IC, 74LVC04, 3.3 V, GATE, 14-SOIC 1 U1 Texas Instruments SN74LVC04AD 35-0720-10 IC, Flash, 1Mx8, 100 ns, 3 V, 40-TSSOP 1 U9 Micron Technologies MT28F008B3VG-10B 35-0719-00 IC, MAX6328, RESET, SOT-23 1 U3 Maxim Inc. MAX6328UR29-T ZHX1810 IC, IR Transceiver, Low Profile 1 U2 Zilog Inc. ZHX1810MV115THTR 35-0062-01 IC, 74LCX32, LV, QUAD OR, 14-TSSOP 1 U4 Fairchild Semi. 74LCX32MTC 35-0022-01 IC, AM7C874, PHY XCVR, 80QFP 1 U6 AMD AM79C874VC eZ80F91 IC, eZ80F91, 50 MHZ, 144VQFP 1 U5 Zilog Inc. eZ80F91 35-0731-00 IC, 74CBTLV3861PWR, 24-TSSOP 1 U10 Texas Instruments SN74CBTLV3861PWR 48-1013-01 Diode, TVS Array, XCVR Prot, 8-SOIC 1 U9 Semtec LCDA15C-6 17-2005-70 CAP, 1000 pF, 50 V, Ceramic Chip, 0603 15 C13, C14, Panasonic C31-43 ECJ-1VC1H561J 17-2005-66 CAP, 0.1 µF, 16 V, Ceramic Chip, 0603 28 C2,10, Kemet Inc. C15-30, C0603C104K5RAC C44-53 17-2005-54 CAP, 0.01 µF, 50 V, Ceramic Chip, 0603 1 C3 Panasonic ECJ-1VB1C103K 17-2005-83 CAP, 0.33 µF, 16 V, Ceramic Chip, 0603 1 C1 Panasonic ECJ-1VF1C334Z 17-2005-63 CAP, 560 pF, 50 V, Ceramic Chip, 0603 1 C6 Panasonic ECJ-1VC1H563K

PS019312-0907 Onboard Component Description eZ80F91 Module Product Specification

Table 6. Bill of Materials for the eZ80F91 Module (Continued)

Jumper Part Number Part Name Quantity Location Manufacturer 17-2001-03 CAP, 12 pF, 50 V, Ceramic Chip, 0603 4 C9, C11, Panasonic C12 ECJ-1VC1H120J 17-2001-05 CAP, 22 pF, 50 V, CER CHIP, 0603 2 C4, C7 PANASONIC ECJ-1VC1H220J 17-2001-20 CAP, 270 pF, 50 V, CER CHIP, 0603 1 C5 PANASONIC ECJ-1VC1H271J 17-2001-01 CAP, 5 pF, 50 V, CER CHIP, 0603 1 C8 PANASONIC ECJ-1VC1H050C 48-0051-00 DIODE, 1N5817, RCTFR 1 CR1 MOTOROLA 1N5817 16-9005-33 INDUCTOR, 3.3 µH, 20%, 1210 SMD 1 L1 PANASONIC ELJ-PA3R3MF 46-3001-03 Resistor, 10 K¾, 1%, 1/16 W, 0603 SMT 15 R3, 8, 10, Sprague R12-18, 420CK472X2PD R20, 25, 29, 30, 37 46-3000-00 Resistor, 0 ¾, 1%, 1/16 W, 0603 SMT 4 R19, 21, " 23, 24 46-3000-71 Resistor, 2.21 K¾, 1%, 1/16W, 0603 SMT 2 R5, R6 " 46-3000-35 Resistor, 68 ¾, 1%, 1/16 W, 0603 SMT 1 R3 " 46-3000-02 RES, 2.2 ¾, 1%, 1/16W, 0603 SMT 1 R4 " 46-3000-32 RES, 49.9 ¾, 1%, 1/16W, 0603 SMT 4 R11, 31, " 32, 33 46-3000-63 RES, 1 K¾, 1%, 1/16W, 0603 SMT 1 R22 " 46-3000-56 RES, 499 ¾,1%, 1/16W, 0603 SMT 1 R26 " 46-3001-34 RES, 200 K¾, 1%, 1/16W, 0603 SMT 1 R27 " 46-3000-47 RES, 221 ¾, 1%, 1/16W, 0603 SMT 1 R28 " 46-3000-51 RES, 332 ¾, 1%, 1/16W, 0603 SMT 2 R34, R35 " 46-3001-75 RES, 10 M¾, 1%, 1/16W, 0603 SMT 1 R38 " 23-0000-25 XTAL, 25.0000 MHz, SER/RESN, HC49S 1 Y1 CITIZEN HC49US25.000MABJ 23-0000-50 XTAL, 50.0000 MHz, SER/RESN, HC49S 1 Y2 CITIZEN HC49US50.000MABJ

PS019312-0907 Onboard Component Description eZ80F91 Module Product Specification

Table 6. Bill of Materials for the eZ80F91 Module (Continued)

Jumper Part Number Part Name Quantity Location Manufacturer 23-0006-00 Internal crystal, 32.768 kHz, SER/RESN, 1 Y3 Fox NC-38 TF case 21-0907-01 Connector, RJ45, Fast jack,10/100 Base-T 1 P2 Halo Electronics HFJ11-2450E-L11 21-0055-02 Connector, HDR/PIN, .025SQ, double row 2 JP1, JP2 Harwin (backside) M-20-976-3622

PS019312-0907 Onboard Component Description eZ80F91 Module Product Specification

Schematics 24 Figure 8 through Figure 10 describes the layout of the eZ80F91 Module. Ethernet circuiting devices are not loaded on the eZ80F91 Module. However, these devices appear in the following schematics for reference.

VCCVCC A[0..23] A[0..23] U1A D[0..7] R1 D[0..7] Connector 1 Connector 2 R2 -F91_WE -F91_WP 1 2 -F91_WP -CS[0..3] 4.7K 4.7K JP1 JP2 -CS[0..3] 1 2 PA7 1 2 PA6 74LCX04 IICSDA IICSDA PA5 PA4 R37 IICSDA 3 4 3 4 TSSOP14 IICSCL IICSCL -TRSTN PA3 PA2 10K IICSCL 5 6 5 6 -F91_WE 7 8 PA1 7 8 PA0 CLK_OUT EZ80CLK GND VCC VCC GND CLK_OUT 9 10 9 10 A6 11 12 A0 PB7 11 12 PB6 VCC -DIS_FLASH A10 A3 PB5 PB4 -DIS_FLASH JP3 13 14 13 14 GND 15 16 VCC PB3 15 16 PB2 1 A8 A7 PB1 PB0 R3 C1 2 17 18 17 18 A13 19 20 A9 GND 19 20 PC7 A15 21 22 A14 PC6 21 22 PC5 -FLASHWE A18 A16 PC4 PC3 R4 68R -FLASHWE WR_EN 23 24 23 24 330nF A19 25 26 GND PC2 25 26 PC1 RTC_VDD A2 A1 PC0 PD7 2R7 U2 RTC_VDD 27 28 27 28 A11 29 30 A12 PD6 29 30 GND 5 PA[0..7] A4 A20 PD5 PD4 VCC PA[0..7] 31 32 31 32 (MMA 0204) A5 33 34 A17 PD3 33 34 PD2 1 PB[0..7] -DIS_FLASH PD1 PD0 LEDA PB[0..7] 35 36 35 36 A21 37 38 VCC TDO 37 38 TDI PD0 2 PC[0..7] A22 A23 GND TRIGOUT TXD PC[0..7] 39 40 39 40 -CS0 41 42 -CS1 TCK 41 42 TMS IRDA_SD 4 PD[0..7] -CS2 D0 RTC_VDD EZ80CLK SD PD[0..7] 43 44 43 44 VCC D1 45 46 D2 IICSCL 45 46 PD1 3 -RESET D3 D4 IICSDA GND RXD -RESET 47 48 47 48 D5 49 50 GND -FLASHWE49 50 6 -RD D7 D6 -CS3 -DIS_IRDA GND T -RD 51 52 51 52 -WR -MREQ -IOREQ -RESET -WAIT -WR 53 54 53 54 ZHX1810 GND 55 56 -RD VCC 55 56 GND 0 -IOREQ R5 R6 -WR -INSTRD -HALT_SLP -NMI -IOREQ 57 58 57 58 -MREQ 2.2K 2.2K -BUSACK -BUSREQ VCC -MREQ 59 60 59 60 -INSTRD -INSTRD -WAIT -WAIT -WAIT -HALT_SLP HEADER 30x2/SM HEADER 30x2/SM -HALT_SLP -BUSREQ -BUSREQ -BUSREQ -BUSACK -BUSACK VCC VCC -NMI -NMI R7 R8 VCC 10K 10K

U1B U4A TDI TDI 1 TDO R20 3 4 3 TDO TRIGOUT 10K TRIGOUT 2 TCK TCK TMS 74LCX04 74LCX32 TMS -TRSTN -TRSTN TSSOP14 TSSOP14 U1F U4D 12 R9 13 12 11 VCC 4.7K 13 VCC 74LCX04 74LCX32 TSSOP14 TSSOP14 GND GND R12 VCC R10 10K 3 U3 10K U1C U4B -DIS_IRDA DISABLE_IRDA C2 -RESET 5 6 4 RESET 2 6 IRDA_SD 0.1 F open-drain PD2 = IR_SD 5 74LCX04 GND VDD TSSOP14 74LCX32 MAX6328UR29 C3

1 0.01 F TSSOP14 SOT-23-L3

VCC alternative: Maxim MAX6802UR 29D3

VCC VCC

GND GND

GND Figure 8. eZ80F91 Module Schematic Diagram—Connectors and Miscellaneous

PS019312-0907 Schematics eZ80F91 Module Product Specification

GND D[0:7] U5 A[0:23] VCC D0 A0 39 D0 A0 1 D1 40 2 A1 R13 R14 R15 R16 R17 D2 D1 A1 A2 R18 10K 10K 10K 10K 10K 41 D2 A2 3 D3 42 4 A3 VCC D3 A3 U6 10 13 27 36 49 52 59 60 73 79 80 D4 43 5 A4 R19 0 10K 0.1% D5 D4 A4 A5 44 D5 A5 8 1 PCSB INTR 43 D6 45 9 A6 2 53 D6 A6 A7 ISODEF TECH_SEL2 R23 D7 46 10 3 VDD1 VDD2 54 0

A7 ISO TVCC1 TVCC2 TECH_SEL1

D7 OVDD1 OVDD2 A8 EQVCC R21 0 11 5 PLLVCC 55 REFVCC CRVVCC -WAIT A8 A9 REFCLK ADOVCC TECH_SEL0 -WAIT 54 WAIT A9 12 7 BURN_IN ANEGA 56 13 A10 -RESET 8 R24 0 -BUSREQ A10 A11 R22 1K RST -BUSREQ 57 BUSREQ A11 16 9 PWRDN IBREF 72 17 A12 GND 14 -NMI A12 A13 PHYAD4_0RXD- -NMI 56 NMI A13 18 15 PHYAD3_10RXD+ RPTR 61 19 A14 16 TMS A14 A15 PHYAD2_10TXD++ R25 10K TMS 66 TMS A15 20 17 PHYAD1_10TXD- LEDSPD0_LEDBTA_FXSEL 44 TCK 67 21 A16 18 TCK TDI TCK A16 A17 PHYAD0_10TXD-- TDI 69 TDI A17 24 19 GPIO0_10TXD-- LECOL_SCRAMEN 45 -TRSTN 71 25 A18 20 -TRSTN TRSTN A18 A19 GPIO1_TP125 -LEDRX A19 26 LEDRX_LEDSEL 46 -RESET 55 27 A20 MDI0 21 -RESET RESET A20 A21 MDC MDIO A21 28 22 MDC LEDTX_LEDBTB 47 -F91_WP 144 29 A22 RXCLK 30 -F91_WP WP A22 A23 RXCLK -LEDLNK A23 30 LEDLNK_LED_10LNK 48 CRS 124 RXD3 23 COL MII_CRS TXD3 RXD2 RXD3 125 MII_COL MII_TXD3 126 24 RXD2 LESPD1_LEDTXA_CLK25EN 57 RXER 135 127 TXD2 RXD1 25 C6 RXDV MII_RXER MII_TXD2 TXD1 RXD0 RXD1 137 MII_RXDV MII_TXD1 128 26 RXD0 LEDDPX_LEDTXB 58 GND RXD3 141 129 TXD0 MII_RXD3 MII_TXD0 C4 RXD2 140 130 TXEN RXDV 29 62 18pF RXD1 MII_RXD2 MII_TXEN TXER RXER RXDV TEST3_SDI+ 139 MII_RXD1 MII_TXER 132 31 RXER_RXD4 TEST2 68 0.056 F R26 RXD0 138 142 MDC TXCLK 33 67 RXCLK MII_RXD0 MII_MDC MDI0 TXCLK_PCSBPCLK TEST1_FXR+ 499 136 MII_RXCLK MII_MDIO 143 TEST0_FXR- 66 C5 TXCLK 131 TXD3 40 69 Y1 220pF MII_TXCLK -IORQ TXD2 TXD3 FXT+ 49 -IORQ 39 70 IORQ -MREQ TXD1 TXD2 FXT- 25 MHz C7 18pF 83 50 -MREQ 38 74 FILT_IN MRQ -RD TXD0 TXD1 XTL- GND RD 51 -RD 37 TXD0 XTL+ 75 52 -WR 77 Y2 WR -WR TX+ 85 58 TXEN 34 78 VCC XOUT BUSACK -CS0 -BUSACK TXER TXEN TX- 33 -CS0 32 50MHz CS0 -CS1 COL TXER_TXD4 86 34 -CS1 41 64 XIN CS1 -CS2 CRS COL RX+ C17 CS2 35 -CS2 42 CRS RX- 63 36 -CS3 0.1 F

R27 CS3 -CS3 TGND1 PLLGND OGND1 DGND1 DGND2 OGND2 CRVGND EQGND REFGND TGND2 SCL SCL 110 IICSCL AM79C874 SDA 4 11 12 28 35 50 51 65 71 76 SDA 109 IICSDA L1 200K 6 C8 VDD PA7 R11 49.9 P2 14 VDD PA7_PWM3 121 C9 22 120 PA6 GND 1 3.3 H 5pF VDD PA6_PWM2_EC1 PA5 TX+ 10pF 31 VDD PA5_PWM1_TOUT1 119 4 TXCT 47 118 PA4 VCC 2 VDD PA4_PWM0_TOUT0 PA3 C44 C45 C46 C47 C48 R32 49.9 TX- 59 VDD PA3_PWM3_OC3 117 81 116 PA2 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F R31 49.9 3 VDD PA2_PWM2_OC2 PA1 VCC R34 R35 RX+ 87 PLL_VDD PA1_PWM1_OC1 115 5 RXCT 88 114 PA0 330 330 6 C10 VDD PA0_PWM0_OC0 RX- 98 PA[0:7] 0.1 F VDD PB7 C49 C50 C51 C52 C53 R33 49.9 C16 112 VDD PB7_MOSI 107 8 GND 122 106 PB6 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F C15 VCC VDD PB6_MISO PB5 GND 0.1 F 0.1 F 133 VDD PB4_ICB3 105 104 PB4 9 RTC_VDD PB4_ICA3 PB3 Put caps between pairs of U6,10:11, 51:52, 59:65 AN1 RTC_VDD PB3_SCK 103 10 CT1 102 PB2 and 71:73 as close to thepins as possible 11 VCC PB2_SS PB1 AN2 7 VSS PB0_IC1 101 12 CT2 15 100 PB0 2 VSS PB0_IC0_EC0 -LEDRX HFJ11-2450E-L11 23 VSS PB[0:7] CR1 32 97 PC7 VSS PC7_RI1 PC6 -LEDLNK 1N5817 38 VSS PC6_DCD1 96 48 95 PC5 VSS PC5_DSR1 PC4 VCC 60 VSS PC4_DTR1 94 1 64 93 PC3 VSS PC3_CTS1 PC2 72 VSS 92 R28 PC2_RTS1 PC1 82 VSS PC1_RXD1 91 220 84 90 PC0 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 PLL_VSS PC0_TXD1 0.001 F 0.001 F 0.001 F 0.001 F 0.001 F 0.001 F 0.001 F 0.001 F 0.001 F 0.001 F 0.001 F 0.001 F 0.001 F 89 VSS PC[0:7] 99 80 PD7 GND VSS PD7_RI0 PD6 108 VSS PD6_DCD0 79 Y3 113 78 PD5 32.768KHz VSS PD5_DSR0 PD4 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 123 VSS PD4_DTR0 77 VL1 134 76 PD3 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F VSS PD3_CTS0 PD2 PD2_RTS0 75 R38 10M 63 74 PD1 VCC RTC_VDD PD1_RXD0_IRRXD PD0 62 RTC_XOUT PD0_TXD0_IRTXD 73 61 RTC_XIN PD[0:7] 65 HALT_SLP -HALT_SLP VCC PHI 111 CLK_OUT VCC VCC C11 C12 53 12pF 12pF INSTRD -INSTRD 70 TDO GND TDO GND TRIGOUT 68 TRIGOUT GND EZ80F91 GND Figure 9. eZ80F91 Module Schematic Diagram—CPU and PHY

PS019312-0907 Schematics eZ80F91 Module Product Specification

U8 A18 1 36 A0 A0 N.C. A16 2 A1 A18 35 A1 3 34 A15 A2 A2 A17 A14 4 A3 A16 33 A3 5 32 A13 -CS1 -CS1 A4 A15 -RD -CS1 6 CE OE 31 VCC D0 7 30 D7 VCC D1I/O0 I/O7 D6 8 I/O1 I/O6 29 9 28 VCC VDD VSS 10 VSS VDD 27 D2 11 26 D5 D3 I/O2 I/O5 D4 12 I/O3 I/O4 25 -WR 13 24 A11 A12 WE A14 A8 14 A5 A13 23 C13 A9 15 22 A10 0.001uF A6 A6 A12 A7 16 A7 A11 21 A4 17 20 A5 A17 A8 A10 18 A9 N.C. 19 512KB x 8 SRAM SOJ36.400

D[0:7] VCC

A[0..23] A[0..23] A[0:23] U9 30 31 U10 A0 21 25 DFLASH0 2 3 D0

A0 VDD VDD DQ0 1B1 1A1 A1 20 26 DFLASH1 5 4 D1 A2 A1 DQ1 DFLASH2 1B2 1A2 D2 19 A2 DQ2 27 6 1B3 1A3 7 A3 18 28 DFLASH3 9 8 D3 A4 A3 DQ3 DFLASH4 1B4 1A4 D4 17 A4 DQ4 32 10 1B5 1A5 11 A5 16 33 DFLASH5 15 14 D5 VCC A6 A5 DQ5 DFLASH6 2B1 2A1 D6 15 A6 DQ6 34 16 2B2 2A2 17 A7 14 35 DFLASH7 19 18 D7 A8 A7 DQ7 2B3 2A3 8 A8 20 2B4 2A4 21 A9 7 23 22 A10 A9 -CSFLASH 2B5 2A5 36 A10 CE 22 C14 A11 6 24 -RD 1 0.001 F A12 A11 OE -WR 1OE -CSFLASH 5 A12 WE 9 2OE 13 A13 4 10 -RESET A14 A13 RP -WP 3 12 74CBTLV3384 A15 A14 WP 2 SO24.300 A16 A15 1 11 VCC A17 A16 VPP 40 A17 A18 13 29 A21 A19 A18 N.C. A20 37 A19 N.C. 38

VCC VSS VSS Flash 1Mx8 3.3V 23 39 TSOP40.20MM MT28F008B3VG

R29 U4C U1D 10K -CS0 9 8 -CSFLASH -DIS_FLASH -FLASH_EN -DIS_FLASH 9 8 10 74LCX32 -RD -RD 74LCX04 TSSOP14 TSSOP14 -WR -WR VCC VCC -CS0 -CS0 VCC

R30 GND -RESET 10K -RESET U1E GND -FLASHWE -WP -FLASHWE 11 10

74LCX04 TSSOP14 Figure 10. eZ80F91 Module Schematic Diagram—Module Memory

PS019312-0907 Schematics eZ80F91 Module Product Specification

Customer Support

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PS019312-0907 Customer Support