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Z80182/Z8L182 Zilog PRELIMINARY ZILOG INTELLIGENT PERIPHERAL

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Z80182/Z8L182 Zilog PRELIMINARY ZILOG INTELLIGENT PERIPHERAL Z80182/Z8L182 Zilog PRELIMINARY ZILOG INTELLIGENT PERIPHERAL PRELIMINARY PRODUCT SPECIFICATION Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL CONTROLLER (ZIP™) FEATURES ■ Z8S180 MPU ■ Two ESCC™ Channels with 32-Bit CRC - Code Compatible with Zilog Z80®/Z180™ CPU - Extended Instructions ■ Three 8-Bit Parallel I/O Ports - Operating Frequency: 33 MHz/5V or 20 MHz/3.3V - Two DMA Channels ■ 16550 Compatible MIMIC Interface for - On-Chip Wait State Generators Direct Connection to PC, XT, AT Bus - Two UART Channels - Two 16-Bit Timer Counters ■ 100-Pin Package Styles (QFP, VQFP) - On-Chip Interrupt Controller (0.8 Micron CMOS 5120 Technology) - On-Chip Clock Oscillator/Generator - Clocked Serial I/O Port ■ Individual WSG for RAMCS and ROMCS - Fully Static - Low EMI Option GENERAL DESCRIPTION The Z80182/Z8L182 is a smart peripheral controller IC for error correction on outgoing and incoming data. In external modem (in particular V. Fast applications), fax, voice applications, three 8-bit parallel ports are available for messaging and other communications applications. It driving LEDs or other devices. Figure 1 shows the Z80182/ uses the Z80180 microprocessor (Z8S180 MPU core) Z8L182 block diagram, while the pin assignments for the linked with two channels of the industry standard Z85230 QFP and the VQFP packages are shown in Figures 2 and ESCC (Enhanced Serial Communications Controller), 24 3, respectively. All references in this document to the bits of parallel I/O, and a 16550 MIMIC for direct connection Z80182, or Z182 refer to both the Z80182 and Z8L182. to the IBM PC, XT, AT bus. Notes: The Z80182/Z8L182 allows complete flexibility for both All Signals with a preceding front slash, "/", are active Low, e.g., internal PC and external applications. Also current PC B//W (WORD is active Low); /B/W (BYTE is active Low, only). modem software compatibility can be maintained with the Z80182/Z8L182 ability to mimic the 16550 UART chip. The Power connections follow conventional descriptions below: Z80180 acts as an interface between the ESCC™ and Connection Circuit Device 16550 MIMIC interface when used in internal applications, Power V V and between the two ESCC channels in the external CC DD Ground GND V applications. This interface allows data compression and SS DS971820600 3-1 Z80182/Z8L182 Zilog PRELIMINARY ZILOG INTELLIGENT PERIPHERAL GENERAL DESCRIPTION (Continued) D7-D0 Control GLU EV1 A19-A0 Logic EV2 Bus Transceiver Z8S180 Tx Data (Static Z80180) MPU Core 85230 85230 Rx Data ESCC ESCC Channel Channel A B ESCC /TRxCB Control /ROMCS Address 16550 Decode MIMIC /RAMCS Interface 8-Bit Parallel 8-Bit Parallel 8-Bit Parallel Port C Port B Port A MUX MUX MUX 85230 ESCC Ch. A 16550 MIMIC or Port C or ESCC 85230 Ch. B Z180 Signals and Port A or Port B Note: Conventional use of the term "MPU side" refers to all interface through the Z180 MPU core and "PC side" refers to all interface through the16550 MIMIC interface. Figure 1. Z80182/Z8L182 Functional Block Diagram 3-2 DS971820600 Z80182/Z8L182 Zilog PRELIMINARY ZILOG INTELLIGENT PERIPHERAL /WAIT EXTAL VSS /RESET /BUSACK XTAL PHI /RD /WR E /IORQ /RFSH /HALT /SYNCB//HCS /RTXCB/HA2 RXDB/HA1 /NMI /BUSREQ /M1 /MRD//MREQ /INT0 100 80 /TRXCB/HA0 1 95 90 85 /INT1/PC6 TXDB//HDDIS /INT2/PC7 /CTSB//HWR ST /DCDB//HRD A0 5 TXDA A1 75 /TRXCA A2 RXDA A3 VDD A4 IEI A5 10 /IOCS/IEO A6 70 VSS A7 /RTXCA A8 /SYNCA/PC4 A9 /DCDA/PC0 A10 15 Z80182/Z8L182 /CTSA/PC1 A11 100-Pin QFP 65 /MWR/PC2//RTSA A12 /DTR//REQA/PC3 VSS /W//REQA/PC5 A13 PA7/HD7 A14 20 PA6/HD6 A15 60 PA5/HD5 A16 PA4/HD4 A17 PA3/HD3 A18/TOUT PA2/HD2 VDD 25 PA1/HD1 A19 55 PA0/HD0 D0 EV2 D1 EV1 D2 /ROMCS D3 30 35 40 45 50 /RAMCS D4 D5 D6 D7 VSS VDD /DREQ1 TXA0/PB3 RXA1/PB6 RXA0/PB4 TXA1/PB5 /CTS0/PB1 /RTS0/PB0 /DCD0/PB2 CKA1//TEND0 CKA0//DREQ0 RXS//CTS1/PB7 CKS//W//REQB//HTXRDY /TEND1//RTSB//HRXRDY TXS//DTR//REQB//HINTR Figure 2. Z80182/Z8L182 100-Pin QFP Pin Configuration DS971820600 3-3 Z80182/Z8L182 Zilog PRELIMINARY ZILOG INTELLIGENT PERIPHERAL GENERAL DESCRIPTION (Continued) RXDA /DCDB//HRD TXDA VDD IEI /MWR/PC2//RTSA EV2 /CTSB//HWR /TRXCA /IOCS/IEO VSS /SYNCA/PC4 /DCDA/PC0 /CTSA/PC1 /DTR//REQA/PC3 /W//REQA/PC5 PA6/HD6 PA5/HD5 PA4/HD4 PA3/HD3 PA2/HD2 PA1/HD1 PA0/HD0 /RTXCA PA7/HD7 75 7065 60 55 51 TXDB//HDDIS 76 50 EV1 /TRXCB/HA0 /ROMCS RXDB/HA1 /RAMCS /RTXCB/HA2 /TEND1//RTSB//HRXRDY /SYNCB//HCS 80 VDD /HALT 45 /DREQ1 /RFSH CKS//W//REQB//HTXRDY /IORQ TXS//DTR//REQB/HINTR /MRD//MREQ CKA1//TEND0 E 85 VSS /M1 40 CKA0//DREQ0 /WR RXS//CTS1/PB7 /RD Z80182/Z8L182 RXA1/PB6 PHI 100-Pin VQFP TXA1/PB5 VSS 90 RXA0/PB4 XTAL 35 TXA0/PB3 EXTAL /DCD0/PB2 /WAIT /CTS0/PB1 /BUSACK /RTS0/PB0 /BUSREQ 95 D7 /RESET 30 D6 /NMI D5 /INT0 D4 /INT1/PC6 D3 /INT2/PC7 100 26 D2 125 10 15 20 5 A1 D1 ST A0 A2 A3 A5 D0 A4 A6 A7 A8 A9 A11 A14 A15 A16 A17 A19 A10 A12 A13 VDD VSS A18/TOUT Figure 3. Z80182/Z8L182 100-Pin VQFP Pin Configuration 3-4 DS971820600 Z80182/Z8L182 Zilog PRELIMINARY ZILOG INTELLIGENT PERIPHERAL Z180 CPU SIGNALS A19-A0. Address Bus (input/output, active High, tri-state). /MRD. Memory Read (input/output, active Low, tri-state). A19-A0 form a 20-bit address bus. The Address Bus /MRD is active when both the internal /MREQ and /RD are provides the address for memory data bus exchanges up active. /MRD is multiplexed with /MREQ on the /MRD to 1 Mbyte, and I/O data bus exchanges up to 64K. The //MREQ pin. The /MRD//MREQ pin is an input during address bus enters a high impedance state during reset adapter modes; is tri-state during bus acknowledge if and external bus acknowledge cycles, as well as during /MREQ function is selected; and is inactive High if /MRD SLEEP and HALT states. This bus is an input when the function is selected. The default function on power up is external bus master is accessing the on-chip peripherals. /MRD and may be changed by programming bit 3 of the Address line A18 is multiplexed with the output of PRT Interrupt Edge/Pin MUX Register (xxDFH). channel 1 (TOUT, selected as address output on reset). /MWR. Memory Write (input/output, active Low, tri-state). D7-D0. Data Bus (bi-directional, active High, tri-state). D7- /MWR is active when both the internal /MREQ and /WR are D0 constitute an 8-bit bi-directional data bus, used for the active. This /RTSA or PC2 combination is pin multiplexed transfer of information to and from I/O and memory devices. with /MWR on the /MWR/PC2//RTSA pin. The default function The data bus enters the high impedance state during reset of this pin on power up is /MWR, which may be changed by and external bus acknowledge cycles, as well as during programming bit 3 in the Interrupt Edge/Pin MUX Register SLEEP and HALT states. (xxDFH). /RD. Read (input/output, active Low, tri-state). /RD indicates /WAIT. (input/output active Low). /WAIT indicates to the that the CPU wants to read data from memory or an I/O MPU that the addressed memory or I/O devices are not device. The addressed I/O or memory device should use ready for a data transfer. This input is used to induce this signal to gate data onto the CPU data bus. additional clock cycles into the current machine cycle. The /WAIT input is sampled on the falling edge of T2 (and /WR. Write (input/output, active Low, tri-state). /WR indicates subsequent wait states). If the input is sampled Low, then that the CPU data bus holds valid data to be stored at the additional wait states are inserted until the /WAIT input is addressed I/O or memory location. sampled High, at which time execution will continue. /IORQ. I/O Request (input/output, active Low, tri-state). /HALT. Halt/Sleep Status (input/output, active Low). This /IORQ indicates that the address bus contains a valid I/O output is asserted after the CPU has executed either the address for an I/O read or I/O write operation. /IORQ is also HALT or SLEEP instruction, and is waiting for either non- generated, along with /M1, during the acknowledgment of maskable or maskable interrupts before operation can the /INT0 input signal to indicate that an interrupt response resume. It is also used with the /M1 and ST signals to vector can be placed onto the data bus. This signal is decode status of the CPU machine cycle. On exit of HALT/ analogous to the IOE signal of the Z64180. SLEEP mode, the first instruction fetch can be delayed by 16 clock cycles after the /HALT pin goes High, if HALT 16 /M1. Machine Cycle 1 (input/output, active Low). Together feature is selected. with /MREQ, /M1 indicates that the current cycle is the opcode fetch cycle of an instruction execution; unless /BUSACK. Bus Acknowledge (input/output, active Low). /M1E bit in the OMCR is cleared to 0. Together with /IORQ, /BUSACK indicates to the requesting device, the MPU /M1 indicates that the current cycle is for an interrupt address and data bus, and some control signals, have acknowledge. It is also used with the /HALT and ST signals entered their high impedance state. to decode status of the CPU machine cycle.
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