Zilog Corporation (Z80)

Distributed by: www.Jameco.com ✦ 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. Z80 Family

CPU User Manual

User Manual

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This publication is subject to replacement by a later edition. To determine whether a later edition exists, or to request copies of publications, contact:

ZiLOG Worldwide Headquarters 910 E. Hamilton Avenue Campbell, CA 95008 Telephone: 408.558.8500 Fax: 408.558.8300 www.ZiLOG.com

Document Disclaimer ZiLOG is a registered trademark of ZiLOG Inc. in the United States and in other countries. All other products and/or service names mentioned herein may be trademarks of the companies with which they are associated. ©2001 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Except with the express written approval of ZiLOG, use of information, devices, or technology as critical components of life support systems is not authorized. No licenses are conveyed, implicitly or otherwise, by this document under any intellectual property rights.

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Table of Contents

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List of Instructions

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List of Figures

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List of Tables

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This user manual describes the architecture and instruction set of the Z80 CPU.

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ZiLOG recommends that the user read and understand everything in this manual before setting up and using the product. However, we recognize that users have different styles of learning: some will want to set up and use their new evaluation kit while they read about it; others will open these pages only to check on a particular specification. Therefore, we have designed this manual to be used either as a how to procedural manual or a reference guide to important data.

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This document is written for ZiLOG customers who are experienced at working with microprocessors or in writing assembly code or compilers.

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The Z80 CPU User’s Manual is divided into four chapters.

2YHUYLHZ Presents an overview of the User’s Manual Architecture, Pin descriptions, timing and Interrupt Response.

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=&38,QVWUXFWLRQ'HVFULSWLRQ Presents the User’s Manual instruction types, addressing modes and instruction Op Codes.

=,QVWUXFWLRQ6HW Presents an overview of the User’s Manual assenbly language, status indicator flags and the Z80 instructions.

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Part Number Title DC number Part Number Title DC number Part Number Title DC number

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The following assumptions and conventions are adopted to provide clarity and ease of use:

8VHRIWKH:RUGV6HWDQG&OHDU The words set and clear imply that a register bit or a condition contains the values logical 1 and logical 0, respectively. When either of these terms is followed by a number, the word logical may not be included, but it is implied.

1RWDWLRQIRU%LWVDQG6LPLODU5HJLVWHUV A field of bits within a register is designated as: Register (n–n). For example: PWM_CR (31–20). A field of bits within a bus is designated as: Busn–n. For example: PCntl7–4. A range of similar (whole) registers is designated as: Registern–Registern. For example: OPBCS5–OPBCS0.

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8VHRIWKH7HUPV/6%DQG06% In this document, the terms LSB and MSB, when appearing in upper case, mean least significant byte and most significant byte, respectively. The lowercase forms, msb and lsb, mean least significant bit and most significant bit, respectively.

&RXULHU)RQW Commands, code lines and fragments, register (and other) mnemonics, values, equations, and various executable items are distinguished from general text by the use of the Courier font. This convention is not used within tables. For example: The STP bit in the CNTR register must be 1. Where the use of the font is not possible, as in the Index, the name of the entity is presented in upper case.

+H[DGHFLPDO9DOXHV'HVLJQDWHGE\+ Hexadecimal values are designated by a uppercase H and appear in the Courier typeface. For example: STAT is set to F8H.

8VHRI$OO8SSHUFDVH/HWWHUV The use of all uppercase letters designates the names of states and commands. For example: The receiver can force the SCL line to Low to force the transmitter into a WAIT state. The bus is considered BUSY after the Start condition. A START command triggers the processing of the initialization sequence.

8VHRI,QLWLDO8SSHUFDVH/HWWHUV Initial uppercase letters designate settings, modes, and conditions in general text. For example: The Slave receiver leaves the data line High. In Transmit mode, the byte is sent most significant bit first. The Master can generate a Stop condition to abort the transfer.

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5HJLVWHU$FFHVV$EEUHYLDWLRQV Register access is designated by the following abbreviations:

Designation Description R Read Only R/W Read/Write WWrite Only – Unspecified or indeterminate

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Z80, Z180, Z380 and Z80382 are trademarks of ZiLOG, Inc.

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The ZiLOG Z80 CPU family of components are fourth-generation enhanced microprocessors with exceptional computational power. They offer higher system throughput and more efficient memory utilization than comparable second- and third-generation microprocessors. The speed offerings from 6–20 MHz suit a wide range of applications which migrate software. The internal registers contain 208 bits of read/write memory that are accessible to the programmer. These registers include two sets of six general purpose registers which may be used individually as either 8-bit registers or as 16-bit register pairs. In addition, there are two sets of accumulator and flag registers. The Z80 CPU also contains a Stack Pointer, Program Counter, two index registers, a REFRESH register, and an INTERRUPT register. The CPU is easy to incorporate into a system since it requires only a single +5V power source. All output signals are fully decoded and timed to control standard memory or peripheral circuits; the Z80 CPU is supported by an extensive family of peripheral controllers. Figure 1 illustrates the internal architecture and major elements of the Z80 CPU.

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The Z80 CPU contains 208 bits of R/W memory that are available to the programmer. Figure 2 illustrates how this memory is configured to eighteen 8-bit registers and four 16-bit registers. All Z80 registers are implemented using static RAM. The registers include two sets of six general-purpose registers that may be used individually as 8-bit registers or in pairs as 16-bit registers. There are also two sets of accumulator and flag registers and six special-purpose registers.

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3URJUDP&RXQWHU 3& The program counter holds the 16-bit address of the current instruction being fetched from memory. The PC is automatically incremented after its contents have been transferred to the address lines. When a program jump occurs, the new value is automatically placed in the PC, overriding the incrementer.

6WDFN3RLQWHU 63 The stack pointer holds the 16-bit address of the current top of a stack located anywhere in external system RAM memory. The external stack memory is organized as a last-in first-out (LIFO) file. Data can be pushed onto the stack from specific CPU registers or popped off of the stack to specific CPU registers through the execution of PUSH and POP instructions. The data popped from the stack is always the last data pushed onto it. The

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stack allows simple implementation of multiple level interrupts, unlimited subroutine nesting and simplification of many types of data manipulation.

7ZR,QGH[5HJLVWHUV ,;DQG,< The two independent index registers hold a 16-bit base address that is used in indexed addressing modes. In this mode, an index register is used as a base to point to a region in memory from which data is to be stored or retrieved. An additional byte is included in indexed instructions to specify a displacement from this base. This displacement is specified as a two’s complement signed integer. This mode of addressing greatly simplifies many types of programs, especially where tables of data are used.

,QWHUUXSW3DJH$GGUHVV5HJLVWHU , The Z80 CPU can be operated in a mode where an indirect call to any memory location can be achieved in response to an interrupt. The I register is used for this purpose and stores the high order eight bits of the indirect address while the interrupting device provides the lower eight bits of the address. This feature allows interrupt routines to be dynamically located anywhere in memory with minimal access time to the routine.

0HPRU\5HIUHVK5HJLVWHU 5 The Z80 CPU contains a memory refresh counter, enabling dynamic memories to be used with the same ease as static memories. Seven bits of this 8-bit register are automatically incremented after each instruction fetch. The eighth bit remains as programmed, resulting from an LD R, A instruction. The data in the refresh counter is sent out on the lower portion of the address bus along with a refresh control signal while the CPU is decoding and executing the fetched instruction. This mode of refresh is transparent to the programmer and does not slow the CPU operation. The programmer can load the R register for testing purposes, but this register is normally not used by the programmer. During refresh, the contents of the I register are placed on the upper eight bits of the address bus.

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The CPU includes two independent 8-bit accumulators and associated 8- bit flag registers. The accumulator holds the results of 8-bit arithmetic or logical operations while the FLAG register indicates specific conditions for 8-bit or 1 16-bit operations, such as indicating whether or not the result of an operation is equal to zero. The programmer selects the accumulator and flag pair with a single exchange instruction so that it is possible to work with either pair.

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Two matched sets of general-purpose registers, each set containing six 8-bit registers, may be used individually as 8-bit registers or as 16-bit register pairs. One set is called BC, DE, and HL while the complementary set is called BC’, DE’, and HL’. At any one time, the programmer can select either set of registers to work through a single exchange command for the entire set. In systems that require fast interrupt response, one set of general-purpose registers and an ACCUMULATOR/FLAG register may be reserved for handling this fast routine. One exchange command is executed to switch routines. This greatly reduces interrupt service time by eliminating the requirement for saving and retrieving register contents in the external stack during interrupt or subroutine processing. These general-purpose registers are used for a wide range of applications. They also simplify programing, specifically in ROM-based systems where little external read/write memory is available.

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The 8-bit arithmetic and logical instructions of the CPU are executed in the ALU. Internally, the ALU communicates with the registers and the external data bus by using the internal data bus. Functions performed by the ALU include:

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• Add • Subtract • Logical AND • Logical OR • Logical Exclusive OR • Compare • Left or Right Shifts or Rotates (Arithmetic and Logical) • Increment • Decrement • Set Bit • Reset Bit • Test bit

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As each instruction is fetched from memory, it is placed in the INSTRUCTION register and decoded. The control sections performs this function and then generates and supplies the control signals necessary to read or write data from or to the registers, control the ALU, and provide required external control signals.

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The Z80 CPU I/O pins are illustrated in Figure 3 and the function of each is described in the following paragraphs.

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27 30 M1 A0 31 A1 19 MREQ 32 A2 20 33 System IORQ A3 21 34 Control RD A4 22 35 WR A5 36 A6 28 37 RFSH A7 Address 38 A8 Bus 18 HALT 39 A9 40 A10 24 1 WAIT A11 2 CPU A12 16 Z80 CPU 3 Control INT A13 17 4 NMI A14 5 A15 26 RESET 25 CPU BUSRQ Bus 23 BUSACK Control 14 D0 15 D1 6 12 CLK D2 11 8 +5V D3 Data 29 7 GND D4 Bus 9 D5 10 D6 13 D7

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$±$ Address Bus (output, active High, tristate). A15-A0 form a 16-bit address bus. The Address Bus provides the address for memory data bus exchanges (up to 64 Kbytes) and for I/O device exchanges.

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%86$&> Bus Acknowledge (output, active Low). Bus Acknowledge indicates to the requesting device that the CPU address bus, data bus, and control signals MREQ, IORQ RD, and WR have entered their high-impedance states. The external circuitry can now control these lines.

%865(4 Bus Request (input, active Low). Bus Request has a higher priority than NMI and is always recognized at the end of the current machine cycle. BUSREQ forces the CPU address bus, data bus, and control signals MREQ IORQ, RD, and WR to go to a high-impedance state so that other devices can control these lines. BUSREQ is normally wired-OR and requires an external pull-up for these applications. Extended BUSREQ periods due to extensive DMA operations can prevent the CPU from properly refreshing dynamic RAMS.

'±' Data Bus (input/output, active High, tristate). D7–D0 constitute an 8-bit bidirectional data bus, used for data exchanges with memory and I/O.

+$/7 HALT State (output, active Low). HALT indicates that the CPU has executed a HALT instruction and is waiting for either a non-maskable or a maskable interrupt (with the mask enabled) before operation can resume. During HALT, the CPU executes NOPs to maintain memory refresh.

,17 Interrupt Request (input, active Low). Interrupt Request is generated by I/O devices. The CPU honors a request at the end of the current instruction if the internal software-controlled interrupt enable flip-flop (IFF) is enabled. INT is normally wired-OR and requires an external pull-up for these applications.

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,254 Input/Output Request (output, active Low, tristate). IORQ indicates that the lower half of the address bus holds a valid I/O address for an I/O read or write operation. IORQ is also generated concurrently with M1 during an interrupt acknowledge cycle to indicate that an interrupt response vector can be placed on the data bus.

0 Machine Cycle One (output, active Low). M1, together with MREQ, indicates that the current machine cycle is the opcode fetch cycle of an instruction execution. M1 together with IORQ, indicates an interrupt acknowledge cycle.

05(4 Memory Request (output, active Low, tristate). MREQ indicates that the address bus holds a valid address for a memory read of memory write operation.

10, Non-Maskable Interrupt (input, negative edge-triggered). NMI has a higher priority than INT. NMI is always recognized at the end of the current instruction, independent of the status of the interrupt enable flip- flop, and automatically forces the CPU to restart at location 0066H.

5' Read (output, active Low, tristate). RD indicates that the CPU wants to read data from memory or an I/O device. The addressed I/O device or memory should use this signal to gate data onto the CPU data bus.

5(6(7 Reset (input, active Low). RESET initializes the CPU as follows: it resets the interrupt enable flip-flop, clears the PC and registers I and R, and sets

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the interrupt status to Mode 0. During reset time, the address and data bus go to a high-impedance state, and all control output signals go to the inactive state. Notice that RESET must be active for a minimum of three full clock cycles before the reset operation is complete.

5)6+ Refresh (output, active Low). RFSH, together with MREQ indicates that the lower seven bits of the system’s address bus can be used as a refresh address to the system’s dynamic memories.

:$,7 WAIT (input, active Low). WAIT communicates to the CPU that the addressed memory or I/O devices are not ready for a data transfer. The CPU continues to enter a WAIT state as long as this signal is active. Extended WAIT periods can prevent the CPU from properly refreshing dynamic memory.

:5 Write (output, active Low, tristate). WR indicates that the CPU data bus holds valid data to be stored at the addressed memory or I/O location.

&/> Clock (input). Single-phase MOS-level clock.

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