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FAN53525 3.0A, 2.4Mhz, Digitally Programmable Tinybuck® Regulator
FAN53525 — 3.0 A, 2.4 MHz, June 2014 FAN53525 3.0A, 2.4MHz, Digitally Programmable TinyBuck® Regulator Digitally Programmable TinyBuck Digitally Features Description . Fixed-Frequency Operation: 2.4 MHz The FAN53525 is a step-down switching voltage regulator that delivers a digitally programmable output from an input . Best-in-Class Load Transient voltage supply of 2.5 V to 5.5 V. The output voltage is 2 . Continuous Output Current Capability: 3.0 A programmed through an I C interface capable of operating up to 3.4 MHz. 2.5 V to 5.5 V Input Voltage Range Using a proprietary architecture with synchronous . Digitally Programmable Output Voltage: rectification, the FAN53525 is capable of delivering 3.0 A - 0.600 V to 1.39375 V in 6.25 mV Steps continuous at over 80% efficiency, maintaining that efficiency at load currents as low as 10 mA. The regulator operates at Programmable Slew Rate for Voltage Transitions . a nominal fixed frequency of 2.4 MHz, which reduces the . I2C-Compatible Interface Up to 3.4 Mbps value of the external components to 330 nH for the output inductor and as low as 20 µF for the output capacitor. PFM Mode for High Efficiency in Light Load . Additional output capacitance can be added to improve . Quiescent Current in PFM Mode: 50 µA (Typical) regulation during load transients without affecting stability, allowing inductance up to 1.2 µH to be used. Input Under-Voltage Lockout (UVLO) ® At moderate and light loads, Pulse Frequency Modulation Regulator Thermal Shutdown and Overload Protection . (PFM) is used to operate in Power-Save Mode with a typical . -
An Emerging Architecture in Smart Phones
International Journal of Electronic Engineering and Computer Science Vol. 3, No. 2, 2018, pp. 29-38 http://www.aiscience.org/journal/ijeecs ARM Processor Architecture: An Emerging Architecture in Smart Phones Naseer Ahmad, Muhammad Waqas Boota * Department of Computer Science, Virtual University of Pakistan, Lahore, Pakistan Abstract ARM is a 32-bit RISC processor architecture. It is develop and licenses by British company ARM holdings. ARM holding does not manufacture and sell the CPU devices. ARM holding only licenses the processor architecture to interested parties. There are two main types of licences implementation licenses and architecture licenses. ARM processors have a unique combination of feature such as ARM core is very simple as compare to general purpose processors. ARM chip has several peripheral controller, a digital signal processor and ARM core. ARM processor consumes less power but provide the high performance. Now a day, ARM Cortex series is very popular in Smartphone devices. We will also see the important characteristics of cortex series. We discuss the ARM processor and system on a chip (SOC) which includes the Qualcomm, Snapdragon, nVidia Tegra, and Apple system on chips. In this paper, we discuss the features of ARM processor and Intel atom processor and see which processor is best. Finally, we will discuss the future of ARM processor in Smartphone devices. Keywords RISC, ISA, ARM Core, System on a Chip (SoC) Received: May 6, 2018 / Accepted: June 15, 2018 / Published online: July 26, 2018 @ 2018 The Authors. Published by American Institute of Science. This Open Access article is under the CC BY license. -
Sitara™ Am57x Processor with Dual ARM® Cortex®-A15 Cores
Sitara™ AM57x processor with dual ARM® Cortex®-A15 cores In today’s industrial automation market, (PLCs) and industrial computers consumers are seeing an evolution to human machine interface (HMI), that requires new technology featuring industrial peripherals and factory amplified performance and capabilities. communication, automation systems The factory automation floor is rapidly require cuttingedge technologies to advancing to become more user meet stringent customer requirements friendly with the incorporation of ele for high reliability in missioncritical ments like user interfaces that are environments. increasingly similar to those we use in our everyday lives and video compe Texas Instruments Incorporated (TI) has tencies that grant the ability to view a strategic commitment to the factory machines running on the opposite side automation industry, ranging from an of factories. This shift necessitates extensive, reliable solution portfolio to solutions very complex, expensive new processors that afford industrial a long product life supply as well as a and resistant to evolution even though system developers the capacity to suc strong localbased support. Industrial industry standards are changing. cessfully address these everevolving automation applications have been challenges. With applications ranging implemented using a variety of external Meeting the need for high from programmable logic controllers components making yesterday’s performance AM57x block diagram In industrial HMI and PLC systems, there is an increasing trend towards achieving x86level performance in fanless enclosures and smaller form factors. At the same time, communica tions requirements are ever increasing for these systems, as is the need for intuitive user interface and highperfor mance graphics in HMI systems. -
OMAP 3 Family of Multimedia Applications
OMAP™ 3 family of multimedia applications processors Revolutionizing entertainment and productivity Key features in wireless handheld commumications • Combines mobile entertainment and high-performance productivity applications. Product Bulletin • Integrates the advanced Superscalar ARM Cortex-A8 RISC core, enabling up to The OMAP™ 3 family of multimedia applications processors from Texas Instruments (TI) 3x gain in performance versus ARM11. introduces a new level of performance that enables laptop-like productivity and advanced • Designed in 45-nm (OMAP36x platform) entertainment in multimedia-enabled handsets. OMAP 3 devices support all levels of and 65-nm (OMAP34x platform) CMOS handsets, from the entry-level multimedia-enabled handsets to high-end Mobile Internet process technologies for less power Devices (MIDs). consumption and increased device performance. Entry-level Mid-level High-end • Includes integrated IVA hardware multimedia-enabled multimedia-enabled multimedia-enabled accelerators to enable multi-standard encode handsets handsets handsets decode up to HD resolution. OMAP3410 OMAP3420 OMAP3430/3440 • Available integrated image signal OMAP3610 OMAP3620 OMAP3630/3640 processor (ISP) enables faster, higher quality image capture, lower system cost TI’s OMAP 3 family of applications processors These devices can operate at a higher and lower power consumption. • Provides seamless connectivity to hard integrate the ARM Cortex-A8 superscalar frequency than previous-generation OMAP diskdrive (HDD) devices for mass storage. microprocessor -
A3MAP: Architecture-Aware Analytic Mapping for Networks-On-Chip Wooyoung Jang and David Z
6C-2 A3MAP: Architecture-Aware Analytic Mapping for Networks-on-Chip Wooyoung Jang and David Z. Pan Department of Electrical and Computer Engineering University of Texas at Austin [email protected], [email protected] Abstract - In this paper, we propose a novel and global A3MAP formulation, we seek to embed a task graph into the metric (Architecture-Aware Analytic Mapping) algorithm applied to space of network. Then, the quality of task mapping is NoC (Networks-on-Chip) based MPSoC (Multi-Processor measured by the total distortion of metric embedding. System-on-Chip) not only with homogeneous cores on regular Through this formulation, our A3MAP can map a task mesh architecture as done by most previous mapping adaptively to any different sized tile both on a algorithms but also with heterogeneous cores on irregular mesh or custom architecture. As a main contribution, we develop a regular/irregular mesh and on a custom network. Fig. 1 simple yet efficient interconnection matrix that models any task shows the methodology of our A3MAP. Given a task graph graph and network. Then, task mapping problem is exactly and a network as inputs, an interconnection matrix that can formulated to an MIQP (Mixed Integer Quadratic model any task graph and network along interconnection is Programming). Since MIQP is NP-hard [15], we propose two generated. Then, task mapping problem is exactly effective heuristics, a successive relaxation algorithm and a formulated to an MIQP (Mixed Integer Quadratic genetic algorithm. Experimental results show that A3MAP by Programming) and is solved by two effective heuristics since the successive relaxation algorithm reduces an amount of the MIQP is NP-hard [15]. -
Comparative Study of Various Systems on Chips Embedded in Mobile Devices
Innovative Systems Design and Engineering www.iiste.org ISSN 2222-1727 (Paper) ISSN 2222-2871 (Online) Vol.4, No.7, 2013 - National Conference on Emerging Trends in Electrical, Instrumentation & Communication Engineering Comparative Study of Various Systems on Chips Embedded in Mobile Devices Deepti Bansal(Assistant Professor) BVCOE, New Delhi Tel N: +919711341624 Email: [email protected] ABSTRACT Systems-on-chips (SoCs) are the latest incarnation of very large scale integration (VLSI) technology. A single integrated circuit can contain over 100 million transistors. Harnessing all this computing power requires designers to move beyond logic design into computer architecture, meet real-time deadlines, ensure low-power operation, and so on. These opportunities and challenges make SoC design an important field of research. So in the paper we will try to focus on the various aspects of SOC and the applications offered by it. Also the different parameters to be checked for functional verification like integration and complexity are described in brief. We will focus mainly on the applications of system on chip in mobile devices and then we will compare various mobile vendors in terms of different parameters like cost, memory, features, weight, and battery life, audio and video applications. A brief discussion on the upcoming technologies in SoC used in smart phones as announced by Intel, Microsoft, Texas etc. is also taken up. Keywords: System on Chip, Core Frame Architecture, Arm Processors, Smartphone. 1. Introduction: What Is SoC? We first need to define system-on-chip (SoC). A SoC is a complex integrated circuit that implements most or all of the functions of a complete electronic system. -
Nomadik Application Processor Andrea Gallo Giancarlo Asnaghi ST Is #1 World-Wide Leader in Digital TV and Consumer Audio
Nomadik Application Processor Andrea Gallo Giancarlo Asnaghi ST is #1 world-wide leader in Digital TV and Consumer Audio MP3 Portable Digital Satellite Radio Set Top Box Player Digital Car Radio DVD Player MMDSP+ inside more than 200 million produced chips January 14, 2009 ST leader in mobile phone chips January 14, 2009 Nomadik Nomadik is based on this heritage providing: – Unrivalled multimedia performances – Very low power consumption – Scalable performances January 14, 2009 BestBest ApplicationApplication ProcessorProcessor 20042004 9 Lowest power consumption 9 Scalable performance 9 Video/Audio quality 9 Cost-effective Nominees: Intel XScale PXA260, NeoMagic MiMagic 6, Nvidia MQ-9000, STMicroelectronics Nomadik STn8800, Texas Instruments OMAP 1611 January 14, 2009 Nomadik Nomadik is a family of Application Processors – Distributed processing architecture ARM9 + multiple Smart Accelerators – Support of a wide range of OS and applications – Seamless integration in the OS through standard API drivers and MM framework January 14, 2009 roadmap ... January 14, 2009 Some Nomadik products on the market... January 14, 2009 STn8815 block diagram January 14, 2009 Nomadik : a true real time multiprocessor platform ARM926 SDRAM SRAM General (L1 + L2) Purpose •Unlimited Space (Level 2 •Limited Bandwidth Cache System for Video) DMA Master OS Memory Controller Peripherals multi-layer AHB bus RTOS RTOS Multi-thread (Scheduler FSM) NAND Flash MMDSP+ Video •Unlimited Space MMDSP+ Audio 66 MHz, 16-bit •“No” Bandwidth 133 MHz, 24-bit •Mass storage -
ARM Was Developed at Acron Computer Limited Of
MEH420 Intro. To Embedded Systems ARM Processors ARM Processors • ARM was developed at Acron Computer • Based upon RISC Architecture with Limited of Cambridge, England between enhancements to meet requirements of 1983 & 1985 embedded applications. • RISC concept introduced in 1980 at Stanford • A large uniform register file and Berkley • Load-store architecture, where data processing operations operate on register contents only • ARM Limited founded in 1990 • Uniform and fixed length instruction • ARM Cores • 32-bit processor • Licensed to partners to develop and fabricate new • Instructions are 32-bit long microcontrollers • Good speed / power consumption ratio • Soft core • High code density -1- -2- -3- ARM Processors ARM Processors ARM Processors • Version 1 (1983-1985) (obsolete) • Version 5T • Enhancement to Basic RISC Features: • 26-bit addressing, no multiply or coprocessor • Superset of 4T adding new instruction • Version 5TE • Control over ALU and barrel shifter for every data • Version 2 (obsolete) processing operation to maximize their usage • Includes 32-bit result multiply co-processor • Add signal processing extension • Auto-increment and auto-decrement addressing • Version 3 • Examples: • ARM9E-S: v5TE (Sony Ericsson K-W series, TI modes to optimize program loops • 32-bit addressing • Load and Store multiple instructions to maximize OMAPs) data throughput • Version 4 • XScale: v4 (Samsung Omnia, Blackberry) • Conditional execution of instructions to maximize • Add signed, unsigned half-word and signed byte • Version 6 execution throughput load and store instructions • ARM11: ARMv6 (iPhone, Nokia E90, N95 etc) • Version 4T: Thumb compressed form of • Cortex-M0-M1: ARMv6 (STM32, NXP LPC, FPGA instruction introduced. Softcore) -4- -5- -6- ARM Processors ARM Processors: Common Features (till v5) ARM Processors: Basic ARM Organization • ARM v7: (M,E-M,R,A): Cortex-M3-M4, Cortex-R4-R5- R7, Cortex-A5-A7-A8-A9,A12, A15. -
Mediatek Inc
01 May 2015 Asia Pacific/Taiwan Equity Research Semiconductor Devices MediaTek Inc. (2454.TW / 2454 TT) Rating NEUTRAL* Price (30 Apr 15, NT$) 395.00 RESULTS Target price (NT$) 405.00¹ Upside/downside (%) 2.5 Mkt cap (NT$ mn) 708,117 (US$ 23,121) 2Q lacks growth, but a high bar is set for 2H Enterprise value (NT$ mn) 544,619 ■ 1Q15 results in line with CS, but below street. 1Q15 sales were already Number of shares (mn) 1,792.70 Free float (%) 89.1 reported at NT$47.5 bn, -14.3% QoQ. Smartphone shipments were 85 mn 52-week price range 535.0 - 390.0 (30mn LTE), down from 95-100mn in 4Q14 due to seasonality and emerging ADTO - 6M (US$ mn) 101.0 market weakness. GMs met our 47.3% vs 46-48% guidance and OpM was also *Stock ratings are relative to the coverage universe in each analyst's or each team's respective sector. in line at 16.1% on cost controls. Lower non-op income kept EPS only in line ¹Target price is for 12 months. with our NT$4.62 and below street's NT$4.97. Research Analysts ■ 2Q15 guidance below, inventory elevated. Sales were guided -5% to +3% Randy Abrams, CFA QoQ, below CS/street's +9%/+18% QoQ on 3G price pressure and 4G mix 886 2 2715 6366 [email protected] skewed to the entry level. Margins are in line, with GMs at 45.5-47.5% and Nickie Yue OpM at 12.5-16.5%. Inventory is elevated, at 102 days and guided to stay 886 2 2715 6364 98-110 days in 2Q15, requiring 2H15 acceleration. -
OMAP-L137 C6000 DSP+ARM Processor
Product Sample & Technical Tools & Support & Folder Buy Documents Software Community OMAP-L137 www.ti.com SPRS563F –SEPTEMBER 2008–REVISED FEBRUARY 2013 OMAP-L137 Low-Power Applications Processor Check for Samples: OMAP-L137 1 OMAP-L137 Low-Power Applications Processor 1.1 Features 1234 • Highlights – 8K-Byte RAM (Vector Table) – Dual Core SoC – 64K-Byte ROM • 375/456-MHz ARM926EJ-S™ RISC MPU • C674x Instruction Set Features • 375/456-MHz C674x VLIW DSP – Superset of the C67x+™ and C64x+™ ISAs – TMS320C674x Fixed/Floating-Point VLIW – Up to 3648/2736 C674x MIPS/MFLOPS DSP Core – Byte-Addressable (8-/16-/32-/64-Bit Data) – Enhanced Direct-Memory-Access Controller – 8-Bit Overflow Protection 3 (EDMA3) – Bit-Field Extract, Set, Clear – 128K-Byte RAM Shared Memory – Normalization, Saturation, Bit-Counting – Two External Memory Interfaces – Compact 16-Bit Instructions – Three Configurable 16550 type UART • C674x Two Level Cache Memory Architecture Modules – 32K-Byte L1P Program RAM/Cache – LCD Controller – 32K-Byte L1D Data RAM/Cache – Two Serial Peripheral Interfaces (SPI) – 256K-Byte L2 Unified Mapped RAM/Cache – Multimedia Card (MMC)/Secure Digital (SD) – Flexible RAM/Cache Partition (L1 and L2) – Two Master/Slave Inter-Integrated Circuit • Enhanced Direct-Memory-Access Controller 3 – One Host-Port Interface (HPI) (EDMA3): – USB 1.1 OHCI (Host) With Integrated PHY – 2 Transfer Controllers (USB1) – 32 Independent DMA Channels • Applications – 8 Quick DMA Channels – Industrial Diagnostics – Programmable Transfer Burst Size – Test and measurement -
Table of Contents
43rdDAC-2C 7/3/06 9:16 AM Page 1 The 43rd Design Automation Conference • July 24 - 28, 2006 • San Francisco, CA Table of Contents 44th DAC Call For Papers ........................................................................................64-65 Keynote Addresses Additional Conference and Hotel Information........................................inside back cover • Monday Keynote Address . 6 • Conference Shuttle Bus Service • Tuesday Keynote Address. 7 • First Aid Rooms • Thursday Keynote Address. .8 • Guest/Family Program MEGa Sessions..............................................................................................................5 • Hotel Locations Monday Schedule ........................................................................................................13 • On-Site Information Desk Monday Tutorial Descriptions..................................................................................42 • San Francisco Attractions New Exhibitors ............................................................................................................4 • Weather Panel Committee ........................................................................................................67 • Wednesday Night Party Pavilion Panels ..............................................................................................................9-12 Additional Meetings ....................................................................................................61-63 Proceedings ..................................................................................................................56 -
Parallel Applications Mapping Onto Heterogeneous Mpsocs Interconnected Using Network on Chip Dihia Belkacemi, Daoui Mehammed, Samia Bouzefrane
Parallel Applications Mapping onto Heterogeneous MPSoCs interconnected using Network on Chip Dihia Belkacemi, Daoui Mehammed, Samia Bouzefrane To cite this version: Dihia Belkacemi, Daoui Mehammed, Samia Bouzefrane. Parallel Applications Mapping onto Hetero- geneous MPSoCs interconnected using Network on Chip. The 6th International Conference on Mobile, Secure and Programmable Networking, Oct 2020, Paris (virtuel), France. 10.1007/978-3-030-67550- 9_9. hal-03122083 HAL Id: hal-03122083 https://hal.archives-ouvertes.fr/hal-03122083 Submitted on 26 Jan 2021 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. Parallel Applications Mapping onto Heterogeneous MPSoCs interconnected using Network on Chip Dihia Belkacemi1, Mehammed Daoui1, and Samia Bouzefrane2 1 Laboratoire de Recherche en Informatique, Universit´ede Tizi-Ouzou, Algeria 2 CEDRIC Lab, CNAM, France [email protected] Abstract. To meet the growing requirements of today's applications, multiprocessor architectures (MPSoCs) interconnected with a network on chip (NoC) are considered as a major solution for future powerful embedded systems. Mapping phase is one of the most critical challenge in designing these systems. It consists of assigning application' tasks on the target platform which can have a considerable influence on the per- formance of the final system.