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Rtvax 300 Hardware User's Guide

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Rtvax 300 Hardware User's Guide rtVAX 300 Hardware User’s Guide Order Number: EK–382AB–UG–002 This manual contains technical and physical specifications of the rtVAX 300 processor and information necessary for configuring it into host and target configurations—that is, information on the following interfaces: memory system, console and boot ROM, network interconnect, and I/O device. Revision/Update Information: This manual supersedes the rtVAX 300 Hardware User’s Guide, EK–382AA–UG– 001. Software Revision: VAXELN Version 4.2 Hardware Revision: rtVAX 300 Version C1 Firmware Revision: Version 1.1 Digital Equipment Corporation Maynard, Massachusetts First Printing, May 1990 Revised, April 1991 The information in this document is subject to change without notice and should not be construed as a commitment by Digital Equipment Corporation. Digital Equipment Corporation assumes no responsibility for any errors that may appear in this document. Any software described in this document is furnished under a license and may be used or copied only in accordance with the terms of such license. No responsibility is assumed for the use or reliability of software or equipment that is not supplied by Digital Equipment Corporation or its affiliated companies. Restricted Rights: Use, duplication, or disclosure by the U.S. Government is subject to restrictions as set forth in subparagraph (c)(1)(ii) of the Rights in Technical Data and Computer Software clause at DFARS 252.227–7013. © Digital Equipment Corporation 1990, 1991. All rights reserved. Printed in U.S.A. The following are trademarks of Digital Equipment Corporation: DDCMP, DEC, DECnet, DECnet–VAX, DECwindows, DELUA, DEQNA, DEUNA, DSSI, IVAX, MicroVAX, PDP, Q22-bus, RQDX, RQDX, rtVAX 300, ThinWire, VAX, VAXcluster, VAX DOCUMENT, VAXELN, VMS, and the DIGITAL Logo. IBM PC/AT is a registered trademark of the International Business Machines Corporation. PROMLINK is a registered trademark of the DATA I/O Corporation. S1537 This document was prepared with VAX DOCUMENT, Version 1.2. Contents Preface ..................................................... xix 1 Overview of the rtVAX 300 Processor 1.1 Central Processor . ................................... 1–2 1.2 Floating-Point Accelerator . ........................... 1–2 1.3 Ethernet Coprocessor .................................. 1–3 1.4 System Support Functions . ........................... 1–3 1.5 Resident Firmware ................................... 1–3 2 Technical Specification 2.1 Functional Description ................................. 2–1 2.1.1 Architecture Summary . ........................... 2–2 2.1.2 CPUandCFPA................................... 2–2 2.1.3 ROM and Reserved Memory Locations ................. 2–2 2.1.4 Network Interface ................................. 2–2 2.1.5 Decode and Control Logic . ........................... 2–4 2.1.6 Interrupt Structure ................................ 2–4 2.1.7 DMA Structure ................................... 2–4 2.1.8 Interval Timer . ................................... 2–4 2.1.9 Internal Cache . ................................... 2–5 2.2 Minimum Hardware Configuration ....................... 2–5 2.2.1 System RAM . ................................... 2–5 2.2.2 Console ......................................... 2–5 2.3 Bus Connections . ................................... 2–6 2.3.1 Power Connections ................................. 2–6 2.3.2 Reset and Power-Up Requirements . ................... 2–6 2.3.3 Power-Down Sequencing: Power-Fail ................... 2–7 2.4 Pin and Signal Description . ........................... 2–8 2.4.1 Data and Address Bus . ........................... 2–11 2.4.2 Ethernet Connections ............................... 2–12 2.4.3 Bus Control Signals ................................ 2–14 iii 2.4.4 Bus Retry Cycles .................................. 2–17 2.4.5 Status and Parity Control Signals . ................... 2–17 2.4.6 Interrupt Control .................................. 2–19 2.4.7 DMA Control Signals ............................... 2–19 2.4.8 System Control Signals . ........................... 2–20 2.4.9 Clock Signals . ................................... 2–20 2.4.10 Power Supply Connections ........................... 2–21 2.5 Memory and I/O Space ................................. 2–21 2.5.1 Address Decode and Boot ROM ....................... 2–23 2.5.2 Boot ROM ....................................... 2–23 2.5.3 Programming the User ROMs ........................ 2–24 2.5.4 Network Interface Registers ......................... 2–24 2.5.5 Board-Level Initialization and Diagnostic ROMs .......... 2–24 2.6 Bus Cycles and Protocols ............................... 2–25 2.6.1 Microcycle Definition ............................... 2–25 2.6.2 Single-Transfer Read Cycle .......................... 2–25 2.6.3 Quadword-Transfer Read Cycle ....................... 2–27 2.6.4 Octaword-Transfer Read Cycle ........................ 2–30 2.6.5 Single-Transfer Write Cycle .......................... 2–33 2.6.6 Octaword-Transfer Write Cycle ....................... 2–35 2.6.7 Interrupt Acknowledge Cycle ......................... 2–36 2.6.8 External IPR Cycles ................................ 2–38 2.6.8.1 External IPR Read Cycle ......................... 2–38 2.6.8.2 External IPR Write Cycle ......................... 2–40 2.6.9 Internal Cycles . ................................... 2–41 2.6.10 DMA Cycle ....................................... 2–41 2.6.11 Cache Invalidate Cycle . ........................... 2–43 3 Hardware Architecture 3.1 Central Processor . ................................... 3–2 3.1.1 Data Types ....................................... 3–2 3.1.2 Instruction Set . ................................... 3–2 3.1.3 Microcode-Assisted Emulated Instructions ............... 3–3 3.1.4 Processor State ................................... 3–5 3.1.4.1 General Purpose Registers ........................ 3–5 3.1.4.2 Processor Status Longword ....................... 3–6 3.1.4.3 Internal Processor Registers . ................... 3–7 3.1.5 Interval Timer . ................................... 3–10 3.1.6 ROM Address Space ................................ 3–11 3.1.7 Resident Firmware Operation ........................ 3–11 iv 3.1.8 Memory Management . ........................... 3–11 3.1.8.1 Translation Buffer . ........................... 3–11 3.1.8.2 Memory Management Control Registers . .......... 3–12 3.1.9 Exceptions and Interrupts ........................... 3–13 3.1.10 Interrupt Control .................................. 3–14 3.1.11 Internal Hardware Interrupts ........................ 3–14 3.1.12 Dispatching Interrupts: Vectors ....................... 3–14 3.1.12.1 Interrupt Action ................................ 3–14 3.1.12.2 Halting the Processor . ........................... 3–16 3.1.12.3 Exceptions . ................................... 3–17 3.1.12.4 Information Saved on a Machine Check Exception . 3–19 3.1.12.5 System Control Block . ........................... 3–24 3.1.12.6 Hardware Detected Errors ........................ 3–27 3.1.12.7 Hardware Halt Procedure ........................ 3–27 3.1.13 System Identification ............................... 3–29 3.1.14 CPU References ................................... 3–29 3.1.14.1 Instruction-Stream Read References ................ 3–29 3.1.14.2 Data-Stream Read References . ................... 3–30 3.1.14.3 Write References ............................... 3–30 3.2 Floating-Point Accelerator . ........................... 3–30 3.2.1 Floating-Point Accelerator Instructions ................. 3–31 3.2.2 Floating-Point Accelerator Data Types .................. 3–31 3.3 Cache Memory ....................................... 3–31 3.3.1 Cacheable References ............................... 3–31 3.3.2 Internal Cache . ................................... 3–32 3.3.2.1 Internal Cache Organization . ................... 3–32 3.3.2.2 Internal Cache Address Translation ................. 3–33 3.3.2.3 Internal Cache Data Block Allocation ............... 3–34 3.3.2.4 Internal Cache Behavior on Writes ................. 3–35 3.3.2.5 Cache Disable Register .......................... 3–36 3.3.2.6 Memory System Error Register . ................... 3–38 3.3.2.7 Internal Cache Error Detection . ................... 3–39 3.4 Hardware Initialization ................................ 3–40 3.4.1 Power-Up Initialization . ........................... 3–40 3.4.2 I/O Bus Initialization ............................... 3–41 3.4.3 Processor Initialization . ........................... 3–41 3.5 Console Interface Registers . ........................... 3–41 3.5.1 Boot Register . ................................... 3–41 3.5.2 Console DUART Register . ........................... 3–42 3.5.3 Memory System Control/Status Register ................ 3–43 3.5.4 Status LED Register ............................... 3–45 3.6 Ethernet Coprocessor .................................. 3–46 v 3.6.1 Control/Status Registers . ........................... 3–47 3.6.1.1 Vector Address, IPL, Sync/Asynch (CSR0) . .......... 3–48 3.6.1.2 Transmit/Receive Polling Demands (CSR1, CSR2)...... 3–50 3.6.1.3 Descriptor List Addresses (CSR3, CSR4) . .......... 3–51 3.6.1.4 Status Register (CSR5) .......................... 3–52 3.6.1.5 Command and Mode Register (CSR6) ............... 3–57 3.6.1.6 System Base Register (CSR7) . ................... 3–61 3.6.1.7 Watchdog Timer Register (CSR9) ................... 3–62 3.6.1.8 Revision Number and Missed Frame Count (CSR10) . 3–63 3.6.1.9 Boot Message Registers (CSR11, CSR12, CSR13) ....... 3–64 3.6.1.10
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